mmc: sdhci: change sdhci-pltfm into a module
There are a couple of problems left from the sdhci pltfm and OF consolidation changes. * When building more than one sdhci-pltfm based drivers in the same image, linker will give multiple definition error on the sdhci-pltfm helper functions. For example right now, building sdhci-of-esdhc and sdhci-of-hlwd together is a valid combination from Kconfig view. * With the current build method, there is error with building the drivers as module, but module installation fails with modprobe. The patch fixes above problems by changing sdhci-pltfm into a module. To avoid EXPORT_SYMBOL on so many big endian IO accessors, it moves these accessors into sdhci-pltfm.h as the 'static inline' functions. As a result, sdhci.h needs to be included in sdhci-pltfm.h, and in turn can be removed from individual drivers which already include sdhci-pltfm.h. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Chris Ball <cjb@laptop.org>
This commit is contained in:
Shawn Guo
Chris Ball
Родитель
100e918610
Коммит
f0de836923
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@ -81,19 +81,32 @@ config MMC_RICOH_MMC
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If unsure, say Y.
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config MMC_SDHCI_OF_ESDHC
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bool "SDHCI OF support for the Freescale eSDHC controller"
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config MMC_SDHCI_PLTFM
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tristate "SDHCI platform and OF driver helper"
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depends on MMC_SDHCI
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help
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This selects the common helper functions support for Secure Digital
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Host Controller Interface based platform and OF drivers.
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If you have a controller with this interface, say Y or M here.
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If unsure, say N.
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config MMC_SDHCI_OF_ESDHC
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tristate "SDHCI OF support for the Freescale eSDHC controller"
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depends on MMC_SDHCI_PLTFM
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depends on PPC_OF
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select MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER
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help
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This selects the Freescale eSDHC controller support.
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If you have a controller with this interface, say Y or M here.
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If unsure, say N.
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config MMC_SDHCI_OF_HLWD
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bool "SDHCI OF support for the Nintendo Wii SDHCI controllers"
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depends on MMC_SDHCI
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tristate "SDHCI OF support for the Nintendo Wii SDHCI controllers"
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depends on MMC_SDHCI_PLTFM
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depends on PPC_OF
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select MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER
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help
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@ -101,43 +114,51 @@ config MMC_SDHCI_OF_HLWD
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found in the "Hollywood" chipset of the Nintendo Wii video game
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console.
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If you have a controller with this interface, say Y or M here.
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If unsure, say N.
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config MMC_SDHCI_CNS3XXX
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tristate "SDHCI support on the Cavium Networks CNS3xxx SoC"
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depends on ARCH_CNS3XXX
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depends on MMC_SDHCI
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depends on MMC_SDHCI_PLTFM
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help
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This selects the SDHCI support for CNS3xxx System-on-Chip devices.
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If you have a controller with this interface, say Y or M here.
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If unsure, say N.
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config MMC_SDHCI_ESDHC_IMX
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tristate "SDHCI platform support for the Freescale eSDHC i.MX controller"
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depends on ARCH_MX25 || ARCH_MX35 || ARCH_MX5
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depends on MMC_SDHCI
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depends on MMC_SDHCI_PLTFM
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select MMC_SDHCI_IO_ACCESSORS
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help
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This selects the Freescale eSDHC controller support on the platform
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bus, found on platforms like mx35/51.
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If you have a controller with this interface, say Y or M here.
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If unsure, say N.
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config MMC_SDHCI_DOVE
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tristate "SDHCI support on Marvell's Dove SoC"
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depends on ARCH_DOVE
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depends on MMC_SDHCI
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depends on MMC_SDHCI_PLTFM
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select MMC_SDHCI_IO_ACCESSORS
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help
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This selects the Secure Digital Host Controller Interface in
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Marvell's Dove SoC.
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If you have a controller with this interface, say Y or M here.
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If unsure, say N.
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config MMC_SDHCI_TEGRA
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tristate "SDHCI platform support for the Tegra SD/MMC Controller"
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depends on ARCH_TEGRA
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depends on MMC_SDHCI
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depends on MMC_SDHCI_PLTFM
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select MMC_SDHCI_IO_ACCESSORS
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help
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This selects the Tegra SD/MMC controller. If you have a Tegra
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@ -44,18 +44,13 @@ obj-$(CONFIG_MMC_JZ4740) += jz4740_mmc.o
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obj-$(CONFIG_MMC_VUB300) += vub300.o
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obj-$(CONFIG_MMC_USHC) += ushc.o
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obj-$(CONFIG_MMC_SDHCI_PLTFM) += sdhci-pltfm.o
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obj-$(CONFIG_MMC_SDHCI_CNS3XXX) += sdhci-cns3xxx.o
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sdhci-cns3xxx-objs := sdhci-pltfm.o
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obj-$(CONFIG_MMC_SDHCI_ESDHC_IMX) += sdhci-esdhc-imx.o
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sdhci-esdhc-imx-objs := sdhci-pltfm.o
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obj-$(CONFIG_MMC_SDHCI_DOVE) += sdhci-dove.o
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sdhci-dove-objs := sdhci-pltfm.o
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obj-$(CONFIG_MMC_SDHCI_TEGRA) += sdhci-tegra.o
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sdhci-tegra-objs := sdhci-pltfm.o
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obj-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhci-of-esdhc.o
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sdhci-of-esdhc-objs := sdhci-pltfm.o
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obj-$(CONFIG_MMC_SDHCI_OF_HLWD) += sdhci-of-hlwd.o
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sdhci-of-hlwd-objs := sdhci-pltfm.o
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ifeq ($(CONFIG_CB710_DEBUG),y)
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CFLAGS-cb710-mmc += -DDEBUG
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@ -16,7 +16,6 @@
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#include <linux/device.h>
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#include <linux/mmc/host.h>
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#include <mach/cns3xxx.h>
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#include "sdhci.h"
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#include "sdhci-pltfm.h"
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static unsigned int sdhci_cns3xxx_get_max_clk(struct sdhci_host *host)
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@ -22,7 +22,6 @@
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#include <linux/io.h>
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#include <linux/mmc/host.h>
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#include "sdhci.h"
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#include "sdhci-pltfm.h"
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static u16 sdhci_dove_readw(struct sdhci_host *host, int reg)
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@ -22,7 +22,6 @@
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#include <linux/mmc/sdio.h>
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#include <mach/hardware.h>
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#include <mach/esdhc.h>
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#include "sdhci.h"
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#include "sdhci-pltfm.h"
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#include "sdhci-esdhc.h"
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@ -17,7 +17,6 @@
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#include <linux/delay.h>
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#include <linux/mmc/host.h>
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#include "sdhci-pltfm.h"
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#include "sdhci.h"
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#include "sdhci-esdhc.h"
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static u16 esdhc_readw(struct sdhci_host *host, int reg)
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@ -22,7 +22,6 @@
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#include <linux/delay.h>
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#include <linux/mmc/host.h>
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#include "sdhci-pltfm.h"
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#include "sdhci.h"
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/*
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* Ops and quirks for the Nintendo Wii SDHCI controllers.
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@ -33,69 +33,11 @@
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#ifdef CONFIG_PPC
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#include <asm/machdep.h>
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#endif
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#include "sdhci.h"
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#include "sdhci-pltfm.h"
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static struct sdhci_ops sdhci_pltfm_ops = {
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};
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#ifdef CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER
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/*
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* These accessors are designed for big endian hosts doing I/O to
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* little endian controllers incorporating a 32-bit hardware byte swapper.
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*/
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u32 sdhci_be32bs_readl(struct sdhci_host *host, int reg)
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{
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return in_be32(host->ioaddr + reg);
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}
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u16 sdhci_be32bs_readw(struct sdhci_host *host, int reg)
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{
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return in_be16(host->ioaddr + (reg ^ 0x2));
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}
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u8 sdhci_be32bs_readb(struct sdhci_host *host, int reg)
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{
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return in_8(host->ioaddr + (reg ^ 0x3));
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}
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void sdhci_be32bs_writel(struct sdhci_host *host, u32 val, int reg)
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{
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out_be32(host->ioaddr + reg, val);
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}
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void sdhci_be32bs_writew(struct sdhci_host *host, u16 val, int reg)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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int base = reg & ~0x3;
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int shift = (reg & 0x2) * 8;
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switch (reg) {
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case SDHCI_TRANSFER_MODE:
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/*
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* Postpone this write, we must do it together with a
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* command write that is down below.
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*/
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pltfm_host->xfer_mode_shadow = val;
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return;
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case SDHCI_COMMAND:
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sdhci_be32bs_writel(host,
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val << 16 | pltfm_host->xfer_mode_shadow,
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SDHCI_TRANSFER_MODE);
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return;
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}
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clrsetbits_be32(host->ioaddr + base, 0xffff << shift, val << shift);
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}
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void sdhci_be32bs_writeb(struct sdhci_host *host, u8 val, int reg)
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{
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int base = reg & ~0x3;
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int shift = (reg & 0x3) * 8;
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clrsetbits_be32(host->ioaddr + base , 0xff << shift, val << shift);
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}
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#endif /* CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER */
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#ifdef CONFIG_OF
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static bool sdhci_of_wp_inverted(struct device_node *np)
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{
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@ -136,6 +78,7 @@ void sdhci_get_of_property(struct platform_device *pdev)
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#else
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void sdhci_get_of_property(struct platform_device *pdev) {}
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#endif /* CONFIG_OF */
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EXPORT_SYMBOL_GPL(sdhci_get_of_property);
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struct sdhci_host *sdhci_pltfm_init(struct platform_device *pdev,
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struct sdhci_pltfm_data *pdata)
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@ -202,6 +145,7 @@ err:
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dev_err(&pdev->dev, "%s failed %d\n", __func__, ret);
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return ERR_PTR(ret);
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}
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EXPORT_SYMBOL_GPL(sdhci_pltfm_init);
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void sdhci_pltfm_free(struct platform_device *pdev)
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{
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@ -213,6 +157,7 @@ void sdhci_pltfm_free(struct platform_device *pdev)
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sdhci_free_host(host);
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platform_set_drvdata(pdev, NULL);
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}
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EXPORT_SYMBOL_GPL(sdhci_pltfm_free);
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int sdhci_pltfm_register(struct platform_device *pdev,
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struct sdhci_pltfm_data *pdata)
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@ -232,6 +177,7 @@ int sdhci_pltfm_register(struct platform_device *pdev,
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return ret;
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}
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EXPORT_SYMBOL_GPL(sdhci_pltfm_register);
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int sdhci_pltfm_unregister(struct platform_device *pdev)
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{
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@ -243,6 +189,7 @@ int sdhci_pltfm_unregister(struct platform_device *pdev)
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return 0;
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}
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EXPORT_SYMBOL_GPL(sdhci_pltfm_unregister);
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#ifdef CONFIG_PM
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int sdhci_pltfm_suspend(struct platform_device *dev, pm_message_t state)
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@ -251,6 +198,7 @@ int sdhci_pltfm_suspend(struct platform_device *dev, pm_message_t state)
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return sdhci_suspend_host(host, state);
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}
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EXPORT_SYMBOL_GPL(sdhci_pltfm_suspend);
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int sdhci_pltfm_resume(struct platform_device *dev)
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{
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@ -258,4 +206,22 @@ int sdhci_pltfm_resume(struct platform_device *dev)
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return sdhci_resume_host(host);
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}
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EXPORT_SYMBOL_GPL(sdhci_pltfm_resume);
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#endif /* CONFIG_PM */
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static int __init sdhci_pltfm_drv_init(void)
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{
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pr_info("sdhci-pltfm: SDHCI platform and OF driver helper\n");
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return 0;
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}
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module_init(sdhci_pltfm_drv_init);
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static void __exit sdhci_pltfm_drv_exit(void)
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{
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}
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module_exit(sdhci_pltfm_drv_exit);
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MODULE_DESCRIPTION("SDHCI platform and OF driver helper");
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MODULE_AUTHOR("Intel Corporation");
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MODULE_LICENSE("GPL v2");
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@ -12,9 +12,8 @@
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#define _DRIVERS_MMC_SDHCI_PLTFM_H
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#include <linux/clk.h>
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#include <linux/types.h>
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#include <linux/platform_device.h>
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#include <linux/mmc/sdhci.h>
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#include "sdhci.h"
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struct sdhci_pltfm_data {
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struct sdhci_ops *ops;
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@ -31,13 +30,63 @@ struct sdhci_pltfm_host {
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};
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#ifdef CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER
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extern u32 sdhci_be32bs_readl(struct sdhci_host *host, int reg);
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extern u16 sdhci_be32bs_readw(struct sdhci_host *host, int reg);
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extern u8 sdhci_be32bs_readb(struct sdhci_host *host, int reg);
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extern void sdhci_be32bs_writel(struct sdhci_host *host, u32 val, int reg);
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extern void sdhci_be32bs_writew(struct sdhci_host *host, u16 val, int reg);
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extern void sdhci_be32bs_writeb(struct sdhci_host *host, u8 val, int reg);
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#endif
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/*
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* These accessors are designed for big endian hosts doing I/O to
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* little endian controllers incorporating a 32-bit hardware byte swapper.
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*/
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static inline u32 sdhci_be32bs_readl(struct sdhci_host *host, int reg)
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{
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return in_be32(host->ioaddr + reg);
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}
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static inline u16 sdhci_be32bs_readw(struct sdhci_host *host, int reg)
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{
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return in_be16(host->ioaddr + (reg ^ 0x2));
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}
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static inline u8 sdhci_be32bs_readb(struct sdhci_host *host, int reg)
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{
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return in_8(host->ioaddr + (reg ^ 0x3));
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}
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static inline void sdhci_be32bs_writel(struct sdhci_host *host,
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u32 val, int reg)
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{
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out_be32(host->ioaddr + reg, val);
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}
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static inline void sdhci_be32bs_writew(struct sdhci_host *host,
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u16 val, int reg)
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{
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struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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int base = reg & ~0x3;
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int shift = (reg & 0x2) * 8;
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switch (reg) {
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case SDHCI_TRANSFER_MODE:
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/*
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* Postpone this write, we must do it together with a
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* command write that is down below.
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*/
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pltfm_host->xfer_mode_shadow = val;
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return;
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case SDHCI_COMMAND:
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sdhci_be32bs_writel(host,
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val << 16 | pltfm_host->xfer_mode_shadow,
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SDHCI_TRANSFER_MODE);
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return;
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}
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clrsetbits_be32(host->ioaddr + base, 0xffff << shift, val << shift);
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}
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static inline void sdhci_be32bs_writeb(struct sdhci_host *host, u8 val, int reg)
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{
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int base = reg & ~0x3;
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int shift = (reg & 0x3) * 8;
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clrsetbits_be32(host->ioaddr + base , 0xff << shift, val << shift);
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}
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#endif /* CONFIG_MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER */
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extern void sdhci_get_of_property(struct platform_device *pdev);
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@ -24,7 +24,6 @@
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#include <mach/gpio.h>
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#include <mach/sdhci.h>
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#include "sdhci.h"
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#include "sdhci-pltfm.h"
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static u32 tegra_sdhci_readl(struct sdhci_host *host, int reg)
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