drivers: net: xgene: fix: Coalescing values for v2 hardware
Changing the interrupt trigger region id to 2 and the corresponding threshold set0/set1 values to 8/16. Signed-off-by: Iyappan Subramanian <isubramanian@apm.com> Signed-off-by: Toan Le <toanle@apm.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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f126df8503
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@ -55,8 +55,10 @@ enum xgene_enet_rm {
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#define PREFETCH_BUF_EN BIT(21)
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#define CSR_RING_ID_BUF 0x000c
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#define CSR_PBM_COAL 0x0014
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#define CSR_PBM_CTICK0 0x0018
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#define CSR_PBM_CTICK1 0x001c
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#define CSR_PBM_CTICK2 0x0020
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#define CSR_PBM_CTICK3 0x0024
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#define CSR_THRESHOLD0_SET1 0x0030
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#define CSR_THRESHOLD1_SET1 0x0034
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#define CSR_RING_NE_INT_MODE 0x017c
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@ -30,7 +30,7 @@ static void xgene_enet_ring_init(struct xgene_enet_desc_ring *ring)
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ring_cfg[0] |= SET_VAL(X2_INTLINE, ring->id & RING_BUFNUM_MASK);
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ring_cfg[3] |= SET_BIT(X2_DEQINTEN);
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}
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ring_cfg[0] |= SET_VAL(X2_CFGCRID, 1);
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ring_cfg[0] |= SET_VAL(X2_CFGCRID, 2);
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addr >>= 8;
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ring_cfg[2] |= QCOHERENT | SET_VAL(RINGADDRL, addr);
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@ -192,13 +192,15 @@ static u32 xgene_enet_ring_len(struct xgene_enet_desc_ring *ring)
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static void xgene_enet_setup_coalescing(struct xgene_enet_desc_ring *ring)
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{
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u32 data = 0x7777;
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u32 data = 0x77777777;
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xgene_enet_ring_wr32(ring, CSR_PBM_COAL, 0x8e);
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xgene_enet_ring_wr32(ring, CSR_PBM_CTICK0, data);
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xgene_enet_ring_wr32(ring, CSR_PBM_CTICK1, data);
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xgene_enet_ring_wr32(ring, CSR_PBM_CTICK2, data << 16);
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xgene_enet_ring_wr32(ring, CSR_THRESHOLD0_SET1, 0x40);
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xgene_enet_ring_wr32(ring, CSR_THRESHOLD1_SET1, 0x80);
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xgene_enet_ring_wr32(ring, CSR_PBM_CTICK2, data);
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xgene_enet_ring_wr32(ring, CSR_PBM_CTICK3, data);
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xgene_enet_ring_wr32(ring, CSR_THRESHOLD0_SET1, 0x08);
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xgene_enet_ring_wr32(ring, CSR_THRESHOLD1_SET1, 0x10);
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}
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struct xgene_ring_ops xgene_ring2_ops = {
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