iommu/exynos: Fix trivial typos
Fixed trivial typos and grammar to improve readability. Changed w/a to workaround. Signed-off-by: Sachin Kamat <sachin.kamat@samsung.com> Acked-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Joerg Roedel <jroedel@suse.de>
This commit is contained in:
Sachin Kamat
Joerg Roedel
Родитель
7d1311b93e
Коммит
f171abab8f
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@ -32,7 +32,7 @@
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typedef u32 sysmmu_iova_t;
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typedef u32 sysmmu_pte_t;
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/* We does not consider super section mapping (16MB) */
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/* We do not consider super section mapping (16MB) */
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#define SECT_ORDER 20
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#define LPAGE_ORDER 16
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#define SPAGE_ORDER 12
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@ -307,7 +307,7 @@ static void show_fault_information(const char *name,
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static irqreturn_t exynos_sysmmu_irq(int irq, void *dev_id)
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{
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/* SYSMMU is in blocked when interrupt occurred. */
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/* SYSMMU is in blocked state when interrupt occurred. */
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struct sysmmu_drvdata *data = dev_id;
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enum exynos_sysmmu_inttype itype;
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sysmmu_iova_t addr = -1;
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@ -567,8 +567,8 @@ static void sysmmu_tlb_invalidate_entry(struct device *dev, sysmmu_iova_t iova,
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/*
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* L2TLB invalidation required
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* 4KB page: 1 invalidation
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* 64KB page: 16 invalidation
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* 1MB page: 64 invalidation
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* 64KB page: 16 invalidations
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* 1MB page: 64 invalidations
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* because it is set-associative TLB
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* with 8-way and 64 sets.
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* 1MB page can be cached in one of all sets.
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@ -714,7 +714,7 @@ static int exynos_iommu_domain_init(struct iommu_domain *domain)
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if (!priv->lv2entcnt)
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goto err_counter;
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/* w/a of System MMU v3.3 to prevent caching 1MiB mapping */
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/* Workaround for System MMU v3.3 to prevent caching 1MiB mapping */
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for (i = 0; i < NUM_LV1ENTRIES; i += 8) {
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priv->pgtable[i + 0] = ZERO_LV2LINK;
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priv->pgtable[i + 1] = ZERO_LV2LINK;
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@ -861,14 +861,14 @@ static sysmmu_pte_t *alloc_lv2entry(struct exynos_iommu_domain *priv,
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pgtable_flush(sent, sent + 1);
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/*
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* If pretched SLPD is a fault SLPD in zero_l2_table, FLPD cache
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* may caches the address of zero_l2_table. This function
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* replaces the zero_l2_table with new L2 page table to write
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* valid mappings.
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* If pre-fetched SLPD is a faulty SLPD in zero_l2_table,
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* FLPD cache may cache the address of zero_l2_table. This
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* function replaces the zero_l2_table with new L2 page table
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* to write valid mappings.
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* Accessing the valid area may cause page fault since FLPD
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* cache may still caches zero_l2_table for the valid area
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* instead of new L2 page table that have the mapping
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* information of the valid area
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* cache may still cache zero_l2_table for the valid area
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* instead of new L2 page table that has the mapping
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* information of the valid area.
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* Thus any replacement of zero_l2_table with other valid L2
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* page table must involve FLPD cache invalidation for System
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* MMU v3.3.
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@ -963,27 +963,27 @@ static int lv2set_page(sysmmu_pte_t *pent, phys_addr_t paddr, size_t size,
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/*
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* *CAUTION* to the I/O virtual memory managers that support exynos-iommu:
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*
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* System MMU v3.x have an advanced logic to improve address translation
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* System MMU v3.x has advanced logic to improve address translation
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* performance with caching more page table entries by a page table walk.
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* However, the logic has a bug that caching fault page table entries and System
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* MMU reports page fault if the cached fault entry is hit even though the fault
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* entry is updated to a valid entry after the entry is cached.
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* To prevent caching fault page table entries which may be updated to valid
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* entries later, the virtual memory manager should care about the w/a about the
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* problem. The followings describe w/a.
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* However, the logic has a bug that while caching faulty page table entries,
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* System MMU reports page fault if the cached fault entry is hit even though
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* the fault entry is updated to a valid entry after the entry is cached.
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* To prevent caching faulty page table entries which may be updated to valid
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* entries later, the virtual memory manager should care about the workaround
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* for the problem. The following describes the workaround.
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*
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* Any two consecutive I/O virtual address regions must have a hole of 128KiB
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* in maximum to prevent misbehavior of System MMU 3.x. (w/a of h/w bug)
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* at maximum to prevent misbehavior of System MMU 3.x (workaround for h/w bug).
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*
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* Precisely, any start address of I/O virtual region must be aligned by
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* Precisely, any start address of I/O virtual region must be aligned with
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* the following sizes for System MMU v3.1 and v3.2.
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* System MMU v3.1: 128KiB
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* System MMU v3.2: 256KiB
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*
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* Because System MMU v3.3 caches page table entries more aggressively, it needs
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* more w/a.
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* - Any two consecutive I/O virtual regions must be have a hole of larger size
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* than or equal size to 128KiB.
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* more workarounds.
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* - Any two consecutive I/O virtual regions must have a hole of size larger
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* than or equal to 128KiB.
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* - Start address of an I/O virtual region must be aligned by 128KiB.
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*/
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static int exynos_iommu_map(struct iommu_domain *domain, unsigned long l_iova,
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@ -1061,7 +1061,8 @@ static size_t exynos_iommu_unmap(struct iommu_domain *domain,
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goto err;
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}
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*ent = ZERO_LV2LINK; /* w/a for h/w bug in Sysmem MMU v3.3 */
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/* workaround for h/w bug in System MMU v3.3 */
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*ent = ZERO_LV2LINK;
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pgtable_flush(ent, ent + 1);
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size = SECT_SIZE;
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goto done;
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