RDMA/mlx5: Convert modify QP to use MLX5_SET macros
Instead of hand crafted mlx5_qp_context and mlx5_qp_path use common MLX5_SET() macros. Link: https://lore.kernel.org/r/20200526115440.205922-7-leon@kernel.org Reviewed-by: Maor Gottlieb <maorg@mellanox.com> Reviewed-by: Mark Zhang <markz@mellanox.com> Signed-off-by: Leon Romanovsky <leonro@mellanox.com> Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
This commit is contained in:
Leon Romanovsky
Jason Gunthorpe
Родитель
70bd7fb876
Коммит
f18e26af6a
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@ -3028,14 +3028,13 @@ int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata)
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return 0;
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}
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static int to_mlx5_access_flags(struct mlx5_ib_qp *qp,
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const struct ib_qp_attr *attr,
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int attr_mask, __be32 *hw_access_flags_be)
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static int set_qpc_atomic_flags(struct mlx5_ib_qp *qp,
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const struct ib_qp_attr *attr, int attr_mask,
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void *qpc)
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{
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u8 dest_rd_atomic;
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u32 access_flags, hw_access_flags = 0;
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struct mlx5_ib_dev *dev = to_mdev(qp->ibqp.device);
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u8 dest_rd_atomic;
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u32 access_flags;
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if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC)
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dest_rd_atomic = attr->max_dest_rd_atomic;
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@ -3050,8 +3049,8 @@ static int to_mlx5_access_flags(struct mlx5_ib_qp *qp,
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if (!dest_rd_atomic)
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access_flags &= IB_ACCESS_REMOTE_WRITE;
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if (access_flags & IB_ACCESS_REMOTE_READ)
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hw_access_flags |= MLX5_QP_BIT_RRE;
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MLX5_SET(qpc, qpc, rre, !!(access_flags & IB_ACCESS_REMOTE_READ));
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if (access_flags & IB_ACCESS_REMOTE_ATOMIC) {
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int atomic_mode;
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@ -3059,15 +3058,11 @@ static int to_mlx5_access_flags(struct mlx5_ib_qp *qp,
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if (atomic_mode < 0)
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return -EOPNOTSUPP;
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hw_access_flags |= MLX5_QP_BIT_RAE;
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hw_access_flags |= atomic_mode << MLX5_ATOMIC_MODE_OFFSET;
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MLX5_SET(qpc, qpc, rae, 1);
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MLX5_SET(qpc, qpc, atomic_mode, atomic_mode);
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}
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if (access_flags & IB_ACCESS_REMOTE_WRITE)
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hw_access_flags |= MLX5_QP_BIT_RWE;
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*hw_access_flags_be = cpu_to_be32(hw_access_flags);
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MLX5_SET(qpc, qpc, rwe, !!(access_flags & IB_ACCESS_REMOTE_WRITE));
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return 0;
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}
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@ -3147,26 +3142,22 @@ static int modify_raw_packet_tx_affinity(struct mlx5_core_dev *dev,
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return err;
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}
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static void mlx5_set_path_udp_sport(struct mlx5_qp_path *path,
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const struct rdma_ah_attr *ah,
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static void mlx5_set_path_udp_sport(void *path, const struct rdma_ah_attr *ah,
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u32 lqpn, u32 rqpn)
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{
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u32 fl = ah->grh.flow_label;
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u16 sport;
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if (!fl)
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fl = rdma_calc_flow_label(lqpn, rqpn);
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sport = rdma_flow_label_to_udp_sport(fl);
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path->udp_sport = cpu_to_be16(sport);
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MLX5_SET(ads, path, udp_sport, rdma_flow_label_to_udp_sport(fl));
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}
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static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
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const struct rdma_ah_attr *ah,
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struct mlx5_qp_path *path, u8 port, int attr_mask,
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u32 path_flags, const struct ib_qp_attr *attr,
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bool alt)
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const struct rdma_ah_attr *ah, void *path, u8 port,
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int attr_mask, u32 path_flags,
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const struct ib_qp_attr *attr, bool alt)
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{
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const struct ib_global_route *grh = rdma_ah_read_grh(ah);
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int err;
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@ -3175,8 +3166,8 @@ static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
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u8 sl = rdma_ah_get_sl(ah);
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if (attr_mask & IB_QP_PKEY_INDEX)
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path->pkey_index = cpu_to_be16(alt ? attr->alt_pkey_index :
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attr->pkey_index);
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MLX5_SET(ads, path, pkey_index,
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alt ? attr->alt_pkey_index : attr->pkey_index);
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if (ah_flags & IB_AH_GRH) {
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if (grh->sgid_index >=
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@ -3192,7 +3183,8 @@ static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
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if (!(ah_flags & IB_AH_GRH))
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return -EINVAL;
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memcpy(path->rmac, ah->roce.dmac, sizeof(ah->roce.dmac));
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ether_addr_copy(MLX5_ADDR_OF(ads, path, rmac_47_32),
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ah->roce.dmac);
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if ((qp->ibqp.qp_type == IB_QPT_RC ||
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qp->ibqp.qp_type == IB_QPT_UC ||
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qp->ibqp.qp_type == IB_QPT_XRC_INI ||
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@ -3202,38 +3194,38 @@ static int mlx5_set_path(struct mlx5_ib_dev *dev, struct mlx5_ib_qp *qp,
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mlx5_set_path_udp_sport(path, ah,
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qp->ibqp.qp_num,
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attr->dest_qp_num);
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path->dci_cfi_prio_sl = (sl & 0x7) << 4;
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MLX5_SET(ads, path, eth_prio, sl & 0x7);
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gid_type = ah->grh.sgid_attr->gid_type;
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if (gid_type == IB_GID_TYPE_ROCE_UDP_ENCAP)
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path->ecn_dscp = (grh->traffic_class >> 2) & 0x3f;
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MLX5_SET(ads, path, dscp, grh->traffic_class >> 2);
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} else {
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path->fl_free_ar = (path_flags & MLX5_PATH_FLAG_FL) ? 0x80 : 0;
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path->fl_free_ar |=
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(path_flags & MLX5_PATH_FLAG_FREE_AR) ? 0x40 : 0;
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path->rlid = cpu_to_be16(rdma_ah_get_dlid(ah));
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path->grh_mlid = rdma_ah_get_path_bits(ah) & 0x7f;
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if (ah_flags & IB_AH_GRH)
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path->grh_mlid |= 1 << 7;
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path->dci_cfi_prio_sl = sl & 0xf;
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MLX5_SET(ads, path, fl, !!(path_flags & MLX5_PATH_FLAG_FL));
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MLX5_SET(ads, path, free_ar,
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!!(path_flags & MLX5_PATH_FLAG_FREE_AR));
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MLX5_SET(ads, path, rlid, rdma_ah_get_dlid(ah));
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MLX5_SET(ads, path, mlid, rdma_ah_get_path_bits(ah));
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MLX5_SET(ads, path, grh, !!(ah_flags & IB_AH_GRH));
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MLX5_SET(ads, path, sl, sl);
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}
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if (ah_flags & IB_AH_GRH) {
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path->mgid_index = grh->sgid_index;
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path->hop_limit = grh->hop_limit;
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path->tclass_flowlabel =
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cpu_to_be32((grh->traffic_class << 20) |
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(grh->flow_label));
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memcpy(path->rgid, grh->dgid.raw, 16);
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MLX5_SET(ads, path, src_addr_index, grh->sgid_index);
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MLX5_SET(ads, path, hop_limit, grh->hop_limit);
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MLX5_SET(ads, path, tclass, grh->traffic_class);
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MLX5_SET(ads, path, flow_label, grh->flow_label);
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memcpy(MLX5_ADDR_OF(ads, path, rgid_rip), grh->dgid.raw,
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sizeof(grh->dgid.raw));
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}
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err = ib_rate_to_mlx5(dev, rdma_ah_get_static_rate(ah));
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if (err < 0)
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return err;
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path->static_rate = err;
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path->port = port;
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MLX5_SET(ads, path, stat_rate, err);
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MLX5_SET(ads, path, vhca_port_num, port);
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if (attr_mask & IB_QP_TIMEOUT)
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path->ackto_lt = (alt ? attr->alt_timeout : attr->timeout) << 3;
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MLX5_SET(ads, path, ack_timeout,
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alt ? attr->alt_timeout : attr->timeout);
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if ((qp->ibqp.qp_type == IB_QPT_RAW_PACKET) && qp->sq.wqe_cnt)
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return modify_raw_packet_eth_prio(dev->mdev,
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@ -3759,9 +3751,9 @@ static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
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struct mlx5_ib_qp *qp = to_mqp(ibqp);
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struct mlx5_ib_qp_base *base = &qp->trans_qp.base;
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struct mlx5_ib_cq *send_cq, *recv_cq;
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struct mlx5_qp_context *context;
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struct mlx5_ib_pd *pd;
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enum mlx5_qp_state mlx5_cur, mlx5_new;
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void *qpc, *pri_path, *alt_path;
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enum mlx5_qp_optpar optpar = 0;
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u32 set_id = 0;
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int mlx5_st;
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@ -3773,25 +3765,25 @@ static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
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if (mlx5_st < 0)
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return -EINVAL;
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context = kzalloc(sizeof(*context), GFP_KERNEL);
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if (!context)
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qpc = kzalloc(MLX5_ST_SZ_BYTES(qpc), GFP_KERNEL);
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if (!qpc)
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return -ENOMEM;
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pd = to_mpd(qp->ibqp.pd);
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context->flags = cpu_to_be32(mlx5_st << 16);
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MLX5_SET(qpc, qpc, st, mlx5_st);
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if (!(attr_mask & IB_QP_PATH_MIG_STATE)) {
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context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
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MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
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} else {
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switch (attr->path_mig_state) {
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case IB_MIG_MIGRATED:
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context->flags |= cpu_to_be32(MLX5_QP_PM_MIGRATED << 11);
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MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_MIGRATED);
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break;
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case IB_MIG_REARM:
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context->flags |= cpu_to_be32(MLX5_QP_PM_REARM << 11);
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MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_REARM);
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break;
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case IB_MIG_ARMED:
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context->flags |= cpu_to_be32(MLX5_QP_PM_ARMED << 11);
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MLX5_SET(qpc, qpc, pm_state, MLX5_QP_PM_ARMED);
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break;
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}
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}
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@ -3799,19 +3791,20 @@ static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
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tx_affinity = get_tx_affinity(ibqp, attr, attr_mask,
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cur_state == IB_QPS_RESET &&
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new_state == IB_QPS_INIT, udata);
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if (tx_affinity) {
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context->flags |= cpu_to_be32(tx_affinity << 24);
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if (new_state == IB_QPS_RTR &&
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MLX5_CAP_GEN(dev->mdev, init2_lag_tx_port_affinity))
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optpar |= MLX5_QP_OPTPAR_LAG_TX_AFF;
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}
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MLX5_SET(qpc, qpc, lag_tx_port_affinity, tx_affinity);
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if (tx_affinity && new_state == IB_QPS_RTR &&
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MLX5_CAP_GEN(dev->mdev, init2_lag_tx_port_affinity))
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optpar |= MLX5_QP_OPTPAR_LAG_TX_AFF;
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if (is_sqp(ibqp->qp_type)) {
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context->mtu_msgmax = (IB_MTU_256 << 5) | 8;
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MLX5_SET(qpc, qpc, mtu, IB_MTU_256);
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MLX5_SET(qpc, qpc, log_msg_max, 8);
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} else if ((ibqp->qp_type == IB_QPT_UD &&
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!(qp->flags & IB_QP_CREATE_SOURCE_QPN)) ||
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ibqp->qp_type == MLX5_IB_QPT_REG_UMR) {
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context->mtu_msgmax = (IB_MTU_4096 << 5) | 12;
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MLX5_SET(qpc, qpc, mtu, IB_MTU_4096);
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MLX5_SET(qpc, qpc, log_msg_max, 12);
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} else if (attr_mask & IB_QP_PATH_MTU) {
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if (attr->path_mtu < IB_MTU_256 ||
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attr->path_mtu > IB_MTU_4096) {
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@ -3819,40 +3812,45 @@ static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
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err = -EINVAL;
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goto out;
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}
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context->mtu_msgmax = (attr->path_mtu << 5) |
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(u8)MLX5_CAP_GEN(dev->mdev, log_max_msg);
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MLX5_SET(qpc, qpc, mtu, attr->path_mtu);
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MLX5_SET(qpc, qpc, log_msg_max,
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MLX5_CAP_GEN(dev->mdev, log_max_msg));
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}
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if (attr_mask & IB_QP_DEST_QPN)
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context->log_pg_sz_remote_qpn = cpu_to_be32(attr->dest_qp_num);
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MLX5_SET(qpc, qpc, remote_qpn, attr->dest_qp_num);
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pri_path = MLX5_ADDR_OF(qpc, qpc, primary_address_path);
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alt_path = MLX5_ADDR_OF(qpc, qpc, secondary_address_path);
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if (attr_mask & IB_QP_PKEY_INDEX)
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context->pri_path.pkey_index = cpu_to_be16(attr->pkey_index);
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MLX5_SET(ads, pri_path, pkey_index, attr->pkey_index);
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/* todo implement counter_index functionality */
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if (is_sqp(ibqp->qp_type))
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context->pri_path.port = qp->port;
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MLX5_SET(ads, pri_path, vhca_port_num, qp->port);
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if (attr_mask & IB_QP_PORT)
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context->pri_path.port = attr->port_num;
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MLX5_SET(ads, pri_path, vhca_port_num, attr->port_num);
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if (attr_mask & IB_QP_AV) {
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err = mlx5_set_path(dev, qp, &attr->ah_attr, &context->pri_path,
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attr_mask & IB_QP_PORT ? attr->port_num : qp->port,
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err = mlx5_set_path(dev, qp, &attr->ah_attr, pri_path,
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attr_mask & IB_QP_PORT ? attr->port_num :
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qp->port,
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attr_mask, 0, attr, false);
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if (err)
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goto out;
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}
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if (attr_mask & IB_QP_TIMEOUT)
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context->pri_path.ackto_lt |= attr->timeout << 3;
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MLX5_SET(ads, pri_path, ack_timeout, attr->timeout);
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if (attr_mask & IB_QP_ALT_PATH) {
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err = mlx5_set_path(dev, qp, &attr->alt_ah_attr,
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&context->alt_path,
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err = mlx5_set_path(dev, qp, &attr->alt_ah_attr, alt_path,
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attr->alt_port_num,
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attr_mask | IB_QP_PKEY_INDEX | IB_QP_TIMEOUT,
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attr_mask | IB_QP_PKEY_INDEX |
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IB_QP_TIMEOUT,
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0, attr, true);
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if (err)
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goto out;
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@ -3861,53 +3859,47 @@ static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
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get_cqs(qp->ibqp.qp_type, qp->ibqp.send_cq, qp->ibqp.recv_cq,
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&send_cq, &recv_cq);
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context->flags_pd = cpu_to_be32(pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
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context->cqn_send = send_cq ? cpu_to_be32(send_cq->mcq.cqn) : 0;
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context->cqn_recv = recv_cq ? cpu_to_be32(recv_cq->mcq.cqn) : 0;
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context->params1 = cpu_to_be32(MLX5_IB_ACK_REQ_FREQ << 28);
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MLX5_SET(qpc, qpc, pd, pd ? pd->pdn : to_mpd(dev->devr.p0)->pdn);
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if (send_cq)
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MLX5_SET(qpc, qpc, cqn_snd, send_cq->mcq.cqn);
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if (recv_cq)
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MLX5_SET(qpc, qpc, cqn_rcv, recv_cq->mcq.cqn);
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MLX5_SET(qpc, qpc, log_ack_req_freq, MLX5_IB_ACK_REQ_FREQ);
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if (attr_mask & IB_QP_RNR_RETRY)
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context->params1 |= cpu_to_be32(attr->rnr_retry << 13);
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MLX5_SET(qpc, qpc, rnr_retry, attr->rnr_retry);
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if (attr_mask & IB_QP_RETRY_CNT)
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context->params1 |= cpu_to_be32(attr->retry_cnt << 16);
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MLX5_SET(qpc, qpc, retry_count, attr->retry_cnt);
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if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
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if (attr->max_rd_atomic)
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context->params1 |=
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cpu_to_be32(fls(attr->max_rd_atomic - 1) << 21);
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}
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if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC && attr->max_rd_atomic)
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MLX5_SET(qpc, qpc, log_sra_max, ilog2(attr->max_rd_atomic));
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if (attr_mask & IB_QP_SQ_PSN)
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context->next_send_psn = cpu_to_be32(attr->sq_psn);
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MLX5_SET(qpc, qpc, next_send_psn, attr->sq_psn);
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if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
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if (attr->max_dest_rd_atomic)
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context->params2 |=
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cpu_to_be32(fls(attr->max_dest_rd_atomic - 1) << 21);
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}
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if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC && attr->max_dest_rd_atomic)
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MLX5_SET(qpc, qpc, log_rra_max,
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ilog2(attr->max_dest_rd_atomic));
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if (attr_mask & (IB_QP_ACCESS_FLAGS | IB_QP_MAX_DEST_RD_ATOMIC)) {
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__be32 access_flags;
|
||||
|
||||
err = to_mlx5_access_flags(qp, attr, attr_mask, &access_flags);
|
||||
err = set_qpc_atomic_flags(qp, attr, attr_mask, qpc);
|
||||
if (err)
|
||||
goto out;
|
||||
|
||||
context->params2 |= access_flags;
|
||||
}
|
||||
|
||||
if (attr_mask & IB_QP_MIN_RNR_TIMER)
|
||||
context->rnr_nextrecvpsn |= cpu_to_be32(attr->min_rnr_timer << 24);
|
||||
MLX5_SET(qpc, qpc, min_rnr_nak, attr->min_rnr_timer);
|
||||
|
||||
if (attr_mask & IB_QP_RQ_PSN)
|
||||
context->rnr_nextrecvpsn |= cpu_to_be32(attr->rq_psn);
|
||||
MLX5_SET(qpc, qpc, next_rcv_psn, attr->rq_psn);
|
||||
|
||||
if (attr_mask & IB_QP_QKEY)
|
||||
context->qkey = cpu_to_be32(attr->qkey);
|
||||
MLX5_SET(qpc, qpc, q_key, attr->qkey);
|
||||
|
||||
if (qp->rq.wqe_cnt && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
|
||||
context->db_rec_addr = cpu_to_be64(qp->db.dma);
|
||||
MLX5_SET64(qpc, qpc, dbr_addr, qp->db.dma);
|
||||
|
||||
if (cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT) {
|
||||
u8 port_num = (attr_mask & IB_QP_PORT ? attr->port_num :
|
||||
|
|
@ -3921,15 +3913,14 @@ static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
|
|||
set_id = ibqp->counter->id;
|
||||
else
|
||||
set_id = mlx5_ib_get_counters_id(dev, port_num);
|
||||
context->qp_counter_set_usr_page |=
|
||||
cpu_to_be32(set_id << 24);
|
||||
MLX5_SET(qpc, qpc, counter_set_id, set_id);
|
||||
}
|
||||
|
||||
if (!ibqp->uobject && cur_state == IB_QPS_RESET && new_state == IB_QPS_INIT)
|
||||
context->sq_crq_size |= cpu_to_be16(1 << 4);
|
||||
MLX5_SET(qpc, qpc, rlky, 1);
|
||||
|
||||
if (qp->flags & MLX5_IB_QP_CREATE_SQPN_QP1)
|
||||
context->deth_sqpn = cpu_to_be32(1);
|
||||
MLX5_SET(qpc, qpc, deth_sqpn, 1);
|
||||
|
||||
mlx5_cur = to_mlx5_state(cur_state);
|
||||
mlx5_new = to_mlx5_state(new_state);
|
||||
|
|
@ -3987,7 +3978,7 @@ static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
|
|||
|
||||
err = modify_raw_packet_qp(dev, qp, &raw_qp_param, tx_affinity);
|
||||
} else {
|
||||
err = mlx5_core_qp_modify(dev, op, optpar, context, &base->mqp);
|
||||
err = mlx5_core_qp_modify(dev, op, optpar, qpc, &base->mqp);
|
||||
}
|
||||
|
||||
if (err)
|
||||
|
|
@ -4034,7 +4025,7 @@ static int __mlx5_ib_modify_qp(struct ib_qp *ibqp,
|
|||
}
|
||||
|
||||
out:
|
||||
kfree(context);
|
||||
kfree(qpc);
|
||||
return err;
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -495,72 +495,6 @@ struct mlx5_core_dct {
|
|||
struct completion drained;
|
||||
};
|
||||
|
||||
struct mlx5_qp_path {
|
||||
u8 fl_free_ar;
|
||||
u8 rsvd3;
|
||||
__be16 pkey_index;
|
||||
u8 rsvd0;
|
||||
u8 grh_mlid;
|
||||
__be16 rlid;
|
||||
u8 ackto_lt;
|
||||
u8 mgid_index;
|
||||
u8 static_rate;
|
||||
u8 hop_limit;
|
||||
__be32 tclass_flowlabel;
|
||||
union {
|
||||
u8 rgid[16];
|
||||
u8 rip[16];
|
||||
};
|
||||
u8 f_dscp_ecn_prio;
|
||||
u8 ecn_dscp;
|
||||
__be16 udp_sport;
|
||||
u8 dci_cfi_prio_sl;
|
||||
u8 port;
|
||||
u8 rmac[6];
|
||||
};
|
||||
|
||||
/* FIXME: use mlx5_ifc.h qpc */
|
||||
struct mlx5_qp_context {
|
||||
__be32 flags;
|
||||
__be32 flags_pd;
|
||||
u8 mtu_msgmax;
|
||||
u8 rq_size_stride;
|
||||
__be16 sq_crq_size;
|
||||
__be32 qp_counter_set_usr_page;
|
||||
__be32 wire_qpn;
|
||||
__be32 log_pg_sz_remote_qpn;
|
||||
struct mlx5_qp_path pri_path;
|
||||
struct mlx5_qp_path alt_path;
|
||||
__be32 params1;
|
||||
u8 reserved2[4];
|
||||
__be32 next_send_psn;
|
||||
__be32 cqn_send;
|
||||
__be32 deth_sqpn;
|
||||
u8 reserved3[4];
|
||||
__be32 last_acked_psn;
|
||||
__be32 ssn;
|
||||
__be32 params2;
|
||||
__be32 rnr_nextrecvpsn;
|
||||
__be32 xrcd;
|
||||
__be32 cqn_recv;
|
||||
__be64 db_rec_addr;
|
||||
__be32 qkey;
|
||||
__be32 rq_type_srqn;
|
||||
__be32 rmsn;
|
||||
__be16 hw_sq_wqe_counter;
|
||||
__be16 sw_sq_wqe_counter;
|
||||
__be16 hw_rcyclic_byte_counter;
|
||||
__be16 hw_rq_counter;
|
||||
__be16 sw_rcyclic_byte_counter;
|
||||
__be16 sw_rq_counter;
|
||||
u8 rsvd0[5];
|
||||
u8 cgs;
|
||||
u8 cs_req;
|
||||
u8 cs_res;
|
||||
__be64 dc_access_key;
|
||||
u8 rsvd1[24];
|
||||
};
|
||||
|
||||
int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
|
||||
void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
|
||||
|
||||
|
|
|
|||
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