amd64_edac: Simplify decoding path
Use the struct mce directly instead of copying from it into a custom struct err_regs. No functionality change. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
This commit is contained in:
Borislav Petkov
Родитель
7d20d14da1
Коммит
f192c7b16c
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@ -788,11 +788,6 @@ static int sys_addr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr)
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static int get_channel_from_ecc_syndrome(struct mem_ctl_info *, u16);
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static u16 extract_syndrome(struct err_regs *err)
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{
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return ((err->nbsh >> 15) & 0xff) | ((err->nbsl >> 16) & 0xff00);
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}
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/*
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* Determine if the DIMMs have ECC enabled. ECC is enabled ONLY if all the DIMMs
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* are ECC capable.
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@ -975,12 +970,10 @@ static int k8_early_channel_count(struct amd64_pvt *pvt)
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return (flag) ? 2 : 1;
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}
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/* Extract the ERROR ADDRESS for the K8 CPUs */
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static u64 k8_get_error_address(struct mem_ctl_info *mci,
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struct err_regs *info)
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static u64 k8_get_error_address(struct mem_ctl_info *mci, struct mce *m)
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{
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return (((u64) (info->nbeah & 0xff)) << 32) +
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(info->nbeal & ~0x03);
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/* ErrAddr[39:3] */
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return m->addr & GENMASK(3, 39);
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}
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static void read_dram_base_limit_regs(struct amd64_pvt *pvt, unsigned range)
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@ -1000,18 +993,16 @@ static void read_dram_base_limit_regs(struct amd64_pvt *pvt, unsigned range)
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amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_HI + off, &pvt->ranges[range].lim.hi);
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}
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static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci,
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struct err_regs *err_info, u64 sys_addr)
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static void k8_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr,
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u16 syndrome)
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{
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struct mem_ctl_info *src_mci;
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struct amd64_pvt *pvt = mci->pvt_info;
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int channel, csrow;
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u32 page, offset;
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u16 syndrome;
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syndrome = extract_syndrome(err_info);
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/* CHIPKILL enabled */
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if (err_info->nbcfg & NBCFG_CHIPKILL) {
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if (pvt->nbcfg & NBCFG_CHIPKILL) {
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channel = get_channel_from_ecc_syndrome(mci, syndrome);
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if (channel < 0) {
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/*
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@ -1136,11 +1127,9 @@ static int f10_dbam_to_chip_select(struct amd64_pvt *pvt, int cs_mode)
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return dbam_map[cs_mode];
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}
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static u64 f10_get_error_address(struct mem_ctl_info *mci,
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struct err_regs *info)
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static u64 f10_get_error_address(struct mem_ctl_info *mci, struct mce *m)
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{
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return (((u64) (info->nbeah & 0xffff)) << 32) +
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(info->nbeal & ~0x01);
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return m->addr & GENMASK(1, 47);
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}
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static void f10_read_dram_ctl_register(struct amd64_pvt *pvt)
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@ -1434,14 +1423,12 @@ static int f10_translate_sysaddr_to_cs(struct amd64_pvt *pvt, u64 sys_addr,
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* The @sys_addr is usually an error address received from the hardware
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* (MCX_ADDR).
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*/
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static void f10_map_sysaddr_to_csrow(struct mem_ctl_info *mci,
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struct err_regs *err_info,
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u64 sys_addr)
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static void f10_map_sysaddr_to_csrow(struct mem_ctl_info *mci, u64 sys_addr,
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u16 syndrome)
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{
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struct amd64_pvt *pvt = mci->pvt_info;
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u32 page, offset;
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int nid, csrow, chan = 0;
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u16 syndrome;
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csrow = f10_translate_sysaddr_to_cs(pvt, sys_addr, &nid, &chan);
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@ -1452,8 +1439,6 @@ static void f10_map_sysaddr_to_csrow(struct mem_ctl_info *mci,
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error_address_to_page_and_offset(sys_addr, &page, &offset);
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syndrome = extract_syndrome(err_info);
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/*
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* We need the syndromes for channel detection only when we're
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* ganged. Otherwise @chan should already contain the channel at
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@ -1740,29 +1725,29 @@ static int get_channel_from_ecc_syndrome(struct mem_ctl_info *mci, u16 syndrome)
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* Handle any Correctable Errors (CEs) that have occurred. Check for valid ERROR
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* ADDRESS and process.
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*/
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static void amd64_handle_ce(struct mem_ctl_info *mci,
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struct err_regs *info)
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static void amd64_handle_ce(struct mem_ctl_info *mci, struct mce *m)
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{
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struct amd64_pvt *pvt = mci->pvt_info;
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u64 sys_addr;
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u16 syndrome;
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/* Ensure that the Error Address is VALID */
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if (!(info->nbsh & NBSH_VALID_ERROR_ADDR)) {
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if (!(m->status & MCI_STATUS_ADDRV)) {
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amd64_mc_err(mci, "HW has no ERROR_ADDRESS available\n");
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edac_mc_handle_ce_no_info(mci, EDAC_MOD_STR);
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return;
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}
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sys_addr = pvt->ops->get_error_address(mci, info);
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sys_addr = pvt->ops->get_error_address(mci, m);
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syndrome = extract_syndrome(m->status);
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amd64_mc_err(mci, "CE ERROR_ADDRESS= 0x%llx\n", sys_addr);
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pvt->ops->map_sysaddr_to_csrow(mci, info, sys_addr);
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pvt->ops->map_sysaddr_to_csrow(mci, sys_addr, syndrome);
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}
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/* Handle any Un-correctable Errors (UEs) */
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static void amd64_handle_ue(struct mem_ctl_info *mci,
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struct err_regs *info)
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static void amd64_handle_ue(struct mem_ctl_info *mci, struct mce *m)
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{
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struct amd64_pvt *pvt = mci->pvt_info;
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struct mem_ctl_info *log_mci, *src_mci = NULL;
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@ -1772,13 +1757,13 @@ static void amd64_handle_ue(struct mem_ctl_info *mci,
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log_mci = mci;
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if (!(info->nbsh & NBSH_VALID_ERROR_ADDR)) {
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if (!(m->status & MCI_STATUS_ADDRV)) {
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amd64_mc_err(mci, "HW has no ERROR_ADDRESS available\n");
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edac_mc_handle_ue_no_info(log_mci, EDAC_MOD_STR);
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return;
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}
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sys_addr = pvt->ops->get_error_address(mci, info);
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sys_addr = pvt->ops->get_error_address(mci, m);
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/*
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* Find out which node the error address belongs to. This may be
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@ -1806,11 +1791,11 @@ static void amd64_handle_ue(struct mem_ctl_info *mci,
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}
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static inline void __amd64_decode_bus_error(struct mem_ctl_info *mci,
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struct err_regs *info)
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struct mce *m)
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{
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u16 ec = EC(info->nbsl);
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u8 xec = XEC(info->nbsl, 0x1f);
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int ecc_type = (info->nbsh >> 13) & 0x3;
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u16 ec = EC(m->status);
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u8 xec = XEC(m->status, 0x1f);
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u8 ecc_type = (m->status >> 45) & 0x3;
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/* Bail early out if this was an 'observed' error */
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if (PP(ec) == NBSL_PP_OBS)
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@ -1821,23 +1806,16 @@ static inline void __amd64_decode_bus_error(struct mem_ctl_info *mci,
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return;
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if (ecc_type == 2)
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amd64_handle_ce(mci, info);
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amd64_handle_ce(mci, m);
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else if (ecc_type == 1)
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amd64_handle_ue(mci, info);
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amd64_handle_ue(mci, m);
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}
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void amd64_decode_bus_error(int node_id, struct mce *m, u32 nbcfg)
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{
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struct mem_ctl_info *mci = mcis[node_id];
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struct err_regs regs;
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regs.nbsl = (u32) m->status;
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regs.nbsh = (u32)(m->status >> 32);
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regs.nbeal = (u32) m->addr;
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regs.nbeah = (u32)(m->addr >> 32);
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regs.nbcfg = nbcfg;
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__amd64_decode_bus_error(mci, ®s);
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__amd64_decode_bus_error(mci, m);
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}
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/*
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@ -397,6 +397,11 @@ static inline u64 get_dram_limit(struct amd64_pvt *pvt, unsigned i)
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return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim;
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}
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static inline u16 extract_syndrome(u64 status)
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{
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return ((status >> 47) & 0xff) | ((status >> 16) & 0xff00);
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}
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/*
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* per-node ECC settings descriptor
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*/
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@ -440,11 +445,10 @@ extern struct mcidev_sysfs_attribute amd64_dbg_attrs[NUM_DBG_ATTRS],
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struct low_ops {
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int (*early_channel_count) (struct amd64_pvt *pvt);
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u64 (*get_error_address) (struct mem_ctl_info *mci,
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struct err_regs *info);
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u64 (*get_error_address) (struct mem_ctl_info *mci, struct mce *m);
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void (*read_dram_ctl_register) (struct amd64_pvt *pvt);
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void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci,
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struct err_regs *info, u64 SystemAddr);
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void (*map_sysaddr_to_csrow) (struct mem_ctl_info *mci, u64 sys_addr,
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u16 syndrome);
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int (*dbam_to_cs) (struct amd64_pvt *pvt, int cs_mode);
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int (*read_dct_pci_cfg) (struct amd64_pvt *pvt, int offset,
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u32 *val, const char *func);
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@ -34,7 +34,6 @@
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/*
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* F3x4C bits (MCi_STATUS' high half)
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*/
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#define NBSH_VALID_ERROR_ADDR BIT(26)
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#define NBSH_ERR_CPU_VAL BIT(24)
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enum tt_ids {
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@ -77,17 +76,6 @@ extern const char *pp_msgs[];
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extern const char *to_msgs[];
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extern const char *ii_msgs[];
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/*
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* relevant NB regs
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*/
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struct err_regs {
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u32 nbcfg;
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u32 nbsh;
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u32 nbsl;
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u32 nbeah;
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u32 nbeal;
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};
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/*
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* per-family decoder ops
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*/
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