MIPS: Simplify EVA cache handling
protected_cache_op is only used for flushing user addresses, so we only need to define protected_cache_op different in EVA mode and be done with it. Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
This commit is contained in:
Thomas Bogendoerfer
Родитель
b1468f3071
Коммит
f1b0bf577f
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@ -23,7 +23,6 @@
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#include <asm/mipsmtregs.h>
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#include <asm/mmzone.h>
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#include <asm/unroll.h>
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#include <linux/uaccess.h> /* for uaccess_kernel() */
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extern void (*r4k_blast_dcache)(void);
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extern void (*r4k_blast_icache)(void);
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@ -102,30 +101,9 @@ static inline void flush_scache_line(unsigned long addr)
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cache_op(Hit_Writeback_Inv_SD, addr);
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}
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#define protected_cache_op(op,addr) \
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({ \
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int __err = 0; \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noreorder \n" \
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" .set "MIPS_ISA_ARCH_LEVEL" \n" \
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"1: cache %1, (%2) \n" \
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"2: .insn \n" \
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" .set pop \n" \
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" .section .fixup,\"ax\" \n" \
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"3: li %0, %3 \n" \
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" j 2b \n" \
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" .previous \n" \
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" .section __ex_table,\"a\" \n" \
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" "STR(PTR)" 1b, 3b \n" \
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" .previous" \
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: "+r" (__err) \
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: "i" (op), "r" (addr), "i" (-EFAULT)); \
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__err; \
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})
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#ifdef CONFIG_EVA
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#define protected_cachee_op(op,addr) \
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#define protected_cache_op(op, addr) \
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({ \
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int __err = 0; \
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__asm__ __volatile__( \
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@ -147,6 +125,30 @@ static inline void flush_scache_line(unsigned long addr)
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: "i" (op), "r" (addr), "i" (-EFAULT)); \
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__err; \
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})
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#else
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#define protected_cache_op(op, addr) \
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({ \
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int __err = 0; \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noreorder \n" \
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" .set "MIPS_ISA_ARCH_LEVEL" \n" \
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"1: cache %1, (%2) \n" \
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"2: .insn \n" \
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" .set pop \n" \
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" .section .fixup,\"ax\" \n" \
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"3: li %0, %3 \n" \
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" j 2b \n" \
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" .previous \n" \
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" .section __ex_table,\"a\" \n" \
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" "STR(PTR)" 1b, 3b \n" \
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" .previous" \
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: "+r" (__err) \
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: "i" (op), "r" (addr), "i" (-EFAULT)); \
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__err; \
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})
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#endif
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/*
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* The next two are for badland addresses like signal trampolines.
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@ -158,11 +160,7 @@ static inline int protected_flush_icache_line(unsigned long addr)
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return protected_cache_op(Hit_Invalidate_I_Loongson2, addr);
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default:
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#ifdef CONFIG_EVA
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return protected_cachee_op(Hit_Invalidate_I, addr);
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#else
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return protected_cache_op(Hit_Invalidate_I, addr);
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#endif
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}
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}
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@ -174,20 +172,12 @@ static inline int protected_flush_icache_line(unsigned long addr)
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*/
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static inline int protected_writeback_dcache_line(unsigned long addr)
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{
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#ifdef CONFIG_EVA
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return protected_cachee_op(Hit_Writeback_Inv_D, addr);
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#else
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return protected_cache_op(Hit_Writeback_Inv_D, addr);
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#endif
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}
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static inline int protected_writeback_scache_line(unsigned long addr)
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{
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#ifdef CONFIG_EVA
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return protected_cachee_op(Hit_Writeback_Inv_SD, addr);
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#else
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return protected_cache_op(Hit_Writeback_Inv_SD, addr);
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#endif
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}
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/*
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@ -307,43 +297,8 @@ static inline void prot##extra##blast_##pfx##cache##_range(unsigned long start,
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} \
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}
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#ifndef CONFIG_EVA
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__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_, )
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__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_, )
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#else
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#define __BUILD_PROT_BLAST_CACHE_RANGE(pfx, desc, hitop) \
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static inline void protected_blast_##pfx##cache##_range(unsigned long start,\
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unsigned long end) \
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{ \
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unsigned long lsize = cpu_##desc##_line_size(); \
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unsigned long addr = start & ~(lsize - 1); \
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unsigned long aend = (end - 1) & ~(lsize - 1); \
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\
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if (!uaccess_kernel()) { \
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while (1) { \
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protected_cachee_op(hitop, addr); \
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if (addr == aend) \
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break; \
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addr += lsize; \
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} \
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} else { \
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while (1) { \
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protected_cache_op(hitop, addr); \
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if (addr == aend) \
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break; \
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addr += lsize; \
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} \
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\
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} \
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}
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__BUILD_PROT_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D)
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__BUILD_PROT_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I)
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#endif
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__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_, )
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__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I_Loongson2, \
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protected_, loongson2_)
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