drm/radeon/kms: remove some pll algo flags
These shouldn't be needed with the post div changes in the last patch. Signed-off-by: Alex Deucher <alexdeucher@gmail.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
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@ -501,21 +501,9 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
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(rdev->family == CHIP_RS740))
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pll->flags |= (/*RADEON_PLL_USE_FRAC_FB_DIV |*/
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RADEON_PLL_PREFER_CLOSEST_LOWER);
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if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */
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pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
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else
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pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
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} else {
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} else
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pll->flags |= RADEON_PLL_LEGACY;
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if (mode->clock > 200000) /* range limits??? */
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pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
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else
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pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
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}
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list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
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if (encoder->crtc == crtc) {
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radeon_encoder = to_radeon_encoder(encoder);
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@ -579,7 +579,8 @@ static void radeon_compute_pll_legacy(struct radeon_pll *pll,
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if ((best_vco == 0 && error < best_error) ||
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(best_vco != 0 &&
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((best_error > 100 && error < best_error - 100) ||
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(abs(error - best_error) < 100 && vco_diff < best_vco_diff)))) {
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(abs(error - best_error) < 100 &&
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vco_diff < best_vco_diff)))) {
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best_post_div = post_div;
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best_ref_div = ref_div;
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best_feedback_div = feedback_div;
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@ -587,29 +588,6 @@ static void radeon_compute_pll_legacy(struct radeon_pll *pll,
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best_freq = current_freq;
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best_error = error;
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best_vco_diff = vco_diff;
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} else if (current_freq == freq) {
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if (best_freq == -1) {
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best_post_div = post_div;
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best_ref_div = ref_div;
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best_feedback_div = feedback_div;
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best_frac_feedback_div = frac_feedback_div;
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best_freq = current_freq;
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best_error = error;
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best_vco_diff = vco_diff;
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} else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) ||
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((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) ||
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((pll->flags & RADEON_PLL_PREFER_LOW_FB_DIV) && (feedback_div < best_feedback_div)) ||
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((pll->flags & RADEON_PLL_PREFER_HIGH_FB_DIV) && (feedback_div > best_feedback_div)) ||
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((pll->flags & RADEON_PLL_PREFER_LOW_POST_DIV) && (post_div < best_post_div)) ||
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((pll->flags & RADEON_PLL_PREFER_HIGH_POST_DIV) && (post_div > best_post_div))) {
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best_post_div = post_div;
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best_ref_div = ref_div;
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best_feedback_div = feedback_div;
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best_frac_feedback_div = frac_feedback_div;
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best_freq = current_freq;
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best_error = error;
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best_vco_diff = vco_diff;
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}
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}
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if (current_freq < freq)
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min_frac_feed_div = frac_feedback_div + 1;
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@ -722,11 +722,6 @@ static void radeon_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode)
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else
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pll->algo = PLL_ALGO_LEGACY;
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if (mode->clock > 200000) /* range limits??? */
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pll->flags |= RADEON_PLL_PREFER_HIGH_FB_DIV;
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else
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pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
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list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
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if (encoder->crtc == crtc) {
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struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
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@ -139,16 +139,10 @@ struct radeon_tmds_pll {
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#define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
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#define RADEON_PLL_USE_REF_DIV (1 << 2)
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#define RADEON_PLL_LEGACY (1 << 3)
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#define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
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#define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
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#define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
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#define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
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#define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
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#define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
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#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
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#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
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#define RADEON_PLL_USE_POST_DIV (1 << 12)
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#define RADEON_PLL_IS_LCD (1 << 13)
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#define RADEON_PLL_USE_FRAC_FB_DIV (1 << 4)
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#define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 5)
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#define RADEON_PLL_USE_POST_DIV (1 << 6)
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#define RADEON_PLL_IS_LCD (1 << 7)
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/* pll algo */
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enum radeon_pll_algo {
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