xtensa: add load/store exception handler
Memory attached to instruction bus of the xtensa CPU is only accessible for a limited subset of opcodes. Other opcodes generate an exception with the load/store error cause code. This property complicates use of such systems. Provide a handler that recognizes and transparently fixes such exceptions. The following opcodes are recognized when used outside of FLIX bundles: l32i, l32i.n, l16ui, l16si, l8ui. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov
Родитель
651d4aff68
Коммит
f29cf77609
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@ -203,6 +203,18 @@ config XTENSA_UNALIGNED_USER
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Say Y here to enable unaligned memory access in user space.
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config XTENSA_LOAD_STORE
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bool "Load/store exception handler for memory only readable with l32"
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help
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The Xtensa architecture only allows reading memory attached to its
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instruction bus with l32r and l32i instructions, all other
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instructions raise an exception with the LoadStoreErrorCause code.
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This makes it hard to use some configurations, e.g. store string
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literals in FLASH memory attached to the instruction bus.
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Say Y here to enable exception handler that allows transparent
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byte and 2-byte access to memory attached to instruction bus.
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config HAVE_SMP
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bool "System Supports SMP (MX)"
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depends on XTENSA_VARIANT_CUSTOM
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@ -47,6 +47,7 @@ __init trap_set_handler(int cause, xtensa_exception_handler *handler);
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asmlinkage void fast_illegal_instruction_user(void);
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asmlinkage void fast_syscall_user(void);
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asmlinkage void fast_alloca(void);
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asmlinkage void fast_load_store(void);
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asmlinkage void fast_unaligned(void);
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asmlinkage void fast_second_level_miss(void);
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asmlinkage void fast_store_prohibited(void);
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@ -64,6 +65,10 @@ void do_unhandled(struct pt_regs *regs);
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static inline void __init early_trap_init(void)
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{
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static struct exc_table init_exc_table __initdata = {
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#ifdef CONFIG_XTENSA_LOAD_STORE
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.fast_kernel_handler[EXCCAUSE_LOAD_STORE_ERROR] =
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fast_load_store,
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#endif
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#ifdef CONFIG_MMU
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.fast_kernel_handler[EXCCAUSE_DTLB_MISS] =
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fast_second_level_miss,
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@ -22,7 +22,17 @@
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#include <asm/asmmacro.h>
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#include <asm/processor.h>
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#if XCHAL_UNALIGNED_LOAD_EXCEPTION || XCHAL_UNALIGNED_STORE_EXCEPTION
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#if XCHAL_UNALIGNED_LOAD_EXCEPTION || defined CONFIG_XTENSA_LOAD_STORE
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#define LOAD_EXCEPTION_HANDLER
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#endif
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#if XCHAL_UNALIGNED_STORE_EXCEPTION || defined LOAD_EXCEPTION_HANDLER
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#define ANY_EXCEPTION_HANDLER
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#endif
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#if XCHAL_HAVE_WINDOWED
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#define UNALIGNED_USER_EXCEPTION
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#endif
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/* First-level exception handler for unaligned exceptions.
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*
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@ -58,10 +68,6 @@
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* BE shift left / mask 0 0 X X
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*/
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#if XCHAL_HAVE_WINDOWED
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#define UNALIGNED_USER_EXCEPTION
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#endif
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#if XCHAL_HAVE_BE
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#define HWORD_START 16
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@ -103,7 +109,7 @@
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*
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* 23 0
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* -----------------------------
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* res 0000 0010
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* L8UI xxxx xxxx 0000 ssss tttt 0010
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* L16UI xxxx xxxx 0001 ssss tttt 0010
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* L32I xxxx xxxx 0010 ssss tttt 0010
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* XXX 0011 ssss tttt 0010
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@ -128,9 +134,11 @@
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#define OP0_L32I_N 0x8 /* load immediate narrow */
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#define OP0_S32I_N 0x9 /* store immediate narrow */
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#define OP0_LSAI 0x2 /* load/store */
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#define OP1_SI_MASK 0x4 /* OP1 bit set for stores */
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#define OP1_SI_BIT 2 /* OP1 bit number for stores */
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#define OP1_L8UI 0x0
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#define OP1_L32I 0x2
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#define OP1_L16UI 0x1
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#define OP1_L16SI 0x9
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@ -155,8 +163,73 @@
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*/
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.literal_position
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#ifdef CONFIG_XTENSA_LOAD_STORE
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ENTRY(fast_load_store)
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call0 .Lsave_and_load_instruction
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/* Analyze the instruction (load or store?). */
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extui a0, a4, INSN_OP0, 4 # get insn.op0 nibble
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#if XCHAL_HAVE_DENSITY
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_beqi a0, OP0_L32I_N, 1f # L32I.N, jump
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#endif
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bnei a0, OP0_LSAI, .Linvalid_instruction
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/* 'store indicator bit' set, jump */
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bbsi.l a4, OP1_SI_BIT + INSN_OP1, .Linvalid_instruction
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1:
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movi a3, ~3
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and a3, a3, a8 # align memory address
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__ssa8 a8
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#ifdef CONFIG_MMU
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/* l32e can't be used here even when it's available. */
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/* TODO access_ok(a3) could be used here */
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j .Linvalid_instruction
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#endif
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l32i a5, a3, 0
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l32i a6, a3, 4
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__src_b a3, a5, a6 # a3 has the data word
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#if XCHAL_HAVE_DENSITY
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addi a7, a7, 2 # increment PC (assume 16-bit insn)
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_beqi a0, OP0_L32I_N, .Lload_w# l32i.n: jump
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addi a7, a7, 1
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#else
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addi a7, a7, 3
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#endif
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extui a5, a4, INSN_OP1, 4
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_beqi a5, OP1_L32I, .Lload_w
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bnei a5, OP1_L8UI, .Lload16
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extui a3, a3, 0, 8
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j .Lload_w
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ENDPROC(fast_load_store)
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#endif
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/*
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* Entry condition:
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*
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* a0: trashed, original value saved on stack (PT_AREG0)
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* a1: a1
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* a2: new stack pointer, original in DEPC
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* a3: a3
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* depc: a2, original value saved on stack (PT_DEPC)
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* excsave_1: dispatch table
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*
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* PT_DEPC >= VALID_DOUBLE_EXCEPTION_ADDRESS: double exception, DEPC
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* < VALID_DOUBLE_EXCEPTION_ADDRESS: regular exception
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*/
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#ifdef ANY_EXCEPTION_HANDLER
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ENTRY(fast_unaligned)
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#if XCHAL_UNALIGNED_LOAD_EXCEPTION || XCHAL_UNALIGNED_STORE_EXCEPTION
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call0 .Lsave_and_load_instruction
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/* Analyze the instruction (load or store?). */
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@ -171,12 +244,17 @@ ENTRY(fast_unaligned)
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/* 'store indicator bit' not set, jump */
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_bbci.l a4, OP1_SI_BIT + INSN_OP1, .Lload
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#endif
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#if XCHAL_UNALIGNED_STORE_EXCEPTION
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/* Store: Jump to table entry to get the value in the source register.*/
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.Lstore:movi a5, .Lstore_table # table
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extui a6, a4, INSN_T, 4 # get source register
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addx8 a5, a6, a5
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jx a5 # jump into table
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#endif
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#if XCHAL_UNALIGNED_LOAD_EXCEPTION
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/* Load: Load memory address. */
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@ -207,7 +285,9 @@ ENTRY(fast_unaligned)
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extui a5, a4, INSN_OP1, 4
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_beqi a5, OP1_L32I, .Lload_w # l32i: jump
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#endif
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#ifdef LOAD_EXCEPTION_HANDLER
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.Lload16:
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extui a3, a3, 0, 16 # extract lower 16 bits
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_beqi a5, OP1_L16UI, .Lload_w
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addi a5, a5, -OP1_L16SI
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@ -247,7 +327,8 @@ ENTRY(fast_unaligned)
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mov a13, a3 ; _j .Lexit; .align 8
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mov a14, a3 ; _j .Lexit; .align 8
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mov a15, a3 ; _j .Lexit; .align 8
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#endif
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#if XCHAL_UNALIGNED_STORE_EXCEPTION
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.Lstore_table:
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l32i a3, a2, PT_AREG0; _j .Lstore_w; .align 8
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mov a3, a1; _j .Lstore_w; .align 8 # fishy??
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@ -265,7 +346,9 @@ ENTRY(fast_unaligned)
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mov a3, a13 ; _j .Lstore_w; .align 8
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mov a3, a14 ; _j .Lstore_w; .align 8
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mov a3, a15 ; _j .Lstore_w; .align 8
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#endif
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#ifdef ANY_EXCEPTION_HANDLER
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/* We cannot handle this exception. */
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.extern _kernel_exception
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@ -294,6 +377,8 @@ ENTRY(fast_unaligned)
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2: movi a0, _user_exception
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jx a0
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#endif
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#if XCHAL_UNALIGNED_STORE_EXCEPTION
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# a7: instruction pointer, a4: instruction, a3: value
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.Lstore_w:
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@ -358,7 +443,8 @@ ENTRY(fast_unaligned)
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#else
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s32i a6, a4, 4
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#endif
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#endif
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#ifdef ANY_EXCEPTION_HANDLER
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.Lexit:
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#if XCHAL_HAVE_LOOPS
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rsr a4, lend # check if we reached LEND
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@ -453,7 +539,7 @@ ENTRY(fast_unaligned)
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__src_b a4, a4, a5 # a4 has the instruction
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ret
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#endif
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ENDPROC(fast_unaligned)
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ENTRY(fast_unaligned_fixup)
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@ -490,5 +576,4 @@ ENTRY(fast_unaligned_fixup)
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jx a0
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ENDPROC(fast_unaligned_fixup)
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#endif /* XCHAL_UNALIGNED_LOAD_EXCEPTION || XCHAL_UNALIGNED_STORE_EXCEPTION */
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#endif
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@ -245,7 +245,8 @@ void __init init_arch(bp_tag_t *bp_start)
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{
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/* Initialize basic exception handling if configuration may need it */
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if (IS_ENABLED(CONFIG_KASAN))
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if (IS_ENABLED(CONFIG_KASAN) ||
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IS_ENABLED(CONFIG_XTENSA_LOAD_STORE))
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early_trap_init();
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/* Initialize MMU. */
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@ -54,6 +54,9 @@ static void do_interrupt(struct pt_regs *regs);
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#if XTENSA_FAKE_NMI
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static void do_nmi(struct pt_regs *regs);
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#endif
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#ifdef CONFIG_XTENSA_LOAD_STORE
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static void do_load_store(struct pt_regs *regs);
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#endif
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static void do_unaligned_user(struct pt_regs *regs);
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static void do_multihit(struct pt_regs *regs);
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#if XTENSA_HAVE_COPROCESSORS
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@ -89,7 +92,10 @@ static dispatch_init_table_t __initdata dispatch_init_table[] = {
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{ EXCCAUSE_SYSTEM_CALL, USER, fast_syscall_user },
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{ EXCCAUSE_SYSTEM_CALL, 0, system_call },
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/* EXCCAUSE_INSTRUCTION_FETCH unhandled */
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/* EXCCAUSE_LOAD_STORE_ERROR unhandled*/
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#ifdef CONFIG_XTENSA_LOAD_STORE
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{ EXCCAUSE_LOAD_STORE_ERROR, USER|KRNL, fast_load_store },
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{ EXCCAUSE_LOAD_STORE_ERROR, 0, do_load_store },
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#endif
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{ EXCCAUSE_LEVEL1_INTERRUPT, 0, do_interrupt },
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#ifdef SUPPORT_WINDOWED
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{ EXCCAUSE_ALLOCA, USER|KRNL, fast_alloca },
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@ -347,6 +353,19 @@ static void do_div0(struct pt_regs *regs)
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force_sig_fault(SIGFPE, FPE_INTDIV, (void __user *)regs->pc);
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}
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#ifdef CONFIG_XTENSA_LOAD_STORE
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static void do_load_store(struct pt_regs *regs)
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{
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__die_if_kernel("Unhandled load/store exception in kernel",
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regs, SIGKILL);
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pr_info_ratelimited("Load/store error to %08lx in '%s' (pid = %d, pc = %#010lx)\n",
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regs->excvaddr, current->comm,
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task_pid_nr(current), regs->pc);
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force_sig_fault(SIGBUS, BUS_ADRERR, (void *)regs->excvaddr);
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}
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#endif
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/*
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* Handle unaligned memory accesses from user space. Kill task.
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*
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