spi_txx9 controller driver
This is a driver for SPI controller built into TXx9 MIPS SoCs. This driver is derived from arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
This commit is contained in:
Atsushi Nemoto
Linus Torvalds
Родитель
ccdc7bf925
Коммит
f2cac67dd3
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@ -174,6 +174,12 @@ config SPI_S3C24XX_GPIO
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the inbuilt hardware cannot provide the transfer mode, or
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where the board is using non hardware connected pins.
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config SPI_TXX9
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tristate "Toshiba TXx9 SPI controller"
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depends on SPI_MASTER && GENERIC_GPIO && CPU_TX49XX
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help
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SPI driver for Toshiba TXx9 MIPS SoCs
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config SPI_XILINX
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tristate "Xilinx SPI controller"
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depends on SPI_MASTER && XILINX_VIRTEX && EXPERIMENTAL
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@ -25,6 +25,7 @@ obj-$(CONFIG_SPI_MPC52xx_PSC) += mpc52xx_psc_spi.o
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obj-$(CONFIG_SPI_MPC83xx) += spi_mpc83xx.o
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obj-$(CONFIG_SPI_S3C24XX_GPIO) += spi_s3c24xx_gpio.o
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obj-$(CONFIG_SPI_S3C24XX) += spi_s3c24xx.o
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obj-$(CONFIG_SPI_TXX9) += spi_txx9.o
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obj-$(CONFIG_SPI_XILINX) += xilinx_spi.o
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# ... add above this line ...
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@ -0,0 +1,474 @@
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/*
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* spi_txx9.c - TXx9 SPI controller driver.
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*
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* Based on linux/arch/mips/tx4938/toshiba_rbtx4938/spi_txx9.c
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* Copyright (C) 2000-2001 Toshiba Corporation
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*
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* 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
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* terms of the GNU General Public License version 2. This program is
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* licensed "as is" without any warranty of any kind, whether express
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* or implied.
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*
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* Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
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*
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* Convert to generic SPI framework - Atsushi Nemoto (anemo@mba.ocn.ne.jp)
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*/
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/errno.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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#include <linux/workqueue.h>
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#include <linux/spi/spi.h>
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#include <linux/err.h>
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#include <linux/clk.h>
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#include <asm/gpio.h>
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#define SPI_FIFO_SIZE 4
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#define TXx9_SPMCR 0x00
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#define TXx9_SPCR0 0x04
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#define TXx9_SPCR1 0x08
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#define TXx9_SPFS 0x0c
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#define TXx9_SPSR 0x14
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#define TXx9_SPDR 0x18
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/* SPMCR : SPI Master Control */
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#define TXx9_SPMCR_OPMODE 0xc0
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#define TXx9_SPMCR_CONFIG 0x40
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#define TXx9_SPMCR_ACTIVE 0x80
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#define TXx9_SPMCR_SPSTP 0x02
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#define TXx9_SPMCR_BCLR 0x01
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/* SPCR0 : SPI Control 0 */
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#define TXx9_SPCR0_TXIFL_MASK 0xc000
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#define TXx9_SPCR0_RXIFL_MASK 0x3000
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#define TXx9_SPCR0_SIDIE 0x0800
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#define TXx9_SPCR0_SOEIE 0x0400
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#define TXx9_SPCR0_RBSIE 0x0200
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#define TXx9_SPCR0_TBSIE 0x0100
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#define TXx9_SPCR0_IFSPSE 0x0010
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#define TXx9_SPCR0_SBOS 0x0004
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#define TXx9_SPCR0_SPHA 0x0002
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#define TXx9_SPCR0_SPOL 0x0001
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/* SPSR : SPI Status */
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#define TXx9_SPSR_TBSI 0x8000
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#define TXx9_SPSR_RBSI 0x4000
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#define TXx9_SPSR_TBS_MASK 0x3800
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#define TXx9_SPSR_RBS_MASK 0x0700
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#define TXx9_SPSR_SPOE 0x0080
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#define TXx9_SPSR_IFSD 0x0008
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#define TXx9_SPSR_SIDLE 0x0004
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#define TXx9_SPSR_STRDY 0x0002
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#define TXx9_SPSR_SRRDY 0x0001
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struct txx9spi {
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struct workqueue_struct *workqueue;
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struct work_struct work;
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spinlock_t lock; /* protect 'queue' */
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struct list_head queue;
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wait_queue_head_t waitq;
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void __iomem *membase;
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int irq;
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int baseclk;
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struct clk *clk;
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u32 max_speed_hz, min_speed_hz;
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int last_chipselect;
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int last_chipselect_val;
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};
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static u32 txx9spi_rd(struct txx9spi *c, int reg)
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{
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return __raw_readl(c->membase + reg);
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}
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static void txx9spi_wr(struct txx9spi *c, u32 val, int reg)
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{
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__raw_writel(val, c->membase + reg);
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}
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static void txx9spi_cs_func(struct spi_device *spi, struct txx9spi *c,
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int on, unsigned int cs_delay)
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{
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int val = (spi->mode & SPI_CS_HIGH) ? on : !on;
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if (on) {
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/* deselect the chip with cs_change hint in last transfer */
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if (c->last_chipselect >= 0)
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gpio_set_value(c->last_chipselect,
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!c->last_chipselect_val);
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c->last_chipselect = spi->chip_select;
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c->last_chipselect_val = val;
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} else {
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c->last_chipselect = -1;
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ndelay(cs_delay); /* CS Hold Time */
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}
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gpio_set_value(spi->chip_select, val);
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ndelay(cs_delay); /* CS Setup Time / CS Recovery Time */
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}
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/* the spi->mode bits understood by this driver: */
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#define MODEBITS (SPI_CS_HIGH|SPI_CPOL|SPI_CPHA)
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static int txx9spi_setup(struct spi_device *spi)
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{
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struct txx9spi *c = spi_master_get_devdata(spi->master);
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u8 bits_per_word;
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if (spi->mode & ~MODEBITS)
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return -EINVAL;
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if (!spi->max_speed_hz
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|| spi->max_speed_hz > c->max_speed_hz
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|| spi->max_speed_hz < c->min_speed_hz)
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return -EINVAL;
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bits_per_word = spi->bits_per_word ? : 8;
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if (bits_per_word != 8 && bits_per_word != 16)
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return -EINVAL;
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if (gpio_direction_output(spi->chip_select,
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!(spi->mode & SPI_CS_HIGH))) {
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dev_err(&spi->dev, "Cannot setup GPIO for chipselect.\n");
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return -EINVAL;
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}
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/* deselect chip */
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spin_lock(&c->lock);
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txx9spi_cs_func(spi, c, 0, (NSEC_PER_SEC / 2) / spi->max_speed_hz);
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spin_unlock(&c->lock);
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return 0;
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}
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static irqreturn_t txx9spi_interrupt(int irq, void *dev_id)
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{
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struct txx9spi *c = dev_id;
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/* disable rx intr */
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txx9spi_wr(c, txx9spi_rd(c, TXx9_SPCR0) & ~TXx9_SPCR0_RBSIE,
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TXx9_SPCR0);
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wake_up(&c->waitq);
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return IRQ_HANDLED;
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}
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static void txx9spi_work_one(struct txx9spi *c, struct spi_message *m)
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{
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struct spi_device *spi = m->spi;
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struct spi_transfer *t;
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unsigned int cs_delay;
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unsigned int cs_change = 1;
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int status = 0;
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u32 mcr;
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u32 prev_speed_hz = 0;
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u8 prev_bits_per_word = 0;
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/* CS setup/hold/recovery time in nsec */
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cs_delay = 100 + (NSEC_PER_SEC / 2) / spi->max_speed_hz;
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mcr = txx9spi_rd(c, TXx9_SPMCR);
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if (unlikely((mcr & TXx9_SPMCR_OPMODE) == TXx9_SPMCR_ACTIVE)) {
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dev_err(&spi->dev, "Bad mode.\n");
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status = -EIO;
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goto exit;
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}
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mcr &= ~(TXx9_SPMCR_OPMODE | TXx9_SPMCR_SPSTP | TXx9_SPMCR_BCLR);
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/* enter config mode */
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txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR);
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txx9spi_wr(c, TXx9_SPCR0_SBOS
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| ((spi->mode & SPI_CPOL) ? TXx9_SPCR0_SPOL : 0)
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| ((spi->mode & SPI_CPHA) ? TXx9_SPCR0_SPHA : 0)
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| 0x08,
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TXx9_SPCR0);
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list_for_each_entry (t, &m->transfers, transfer_list) {
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const void *txbuf = t->tx_buf;
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void *rxbuf = t->rx_buf;
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u32 data;
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unsigned int len = t->len;
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unsigned int wsize;
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u32 speed_hz = t->speed_hz ? : spi->max_speed_hz;
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u8 bits_per_word = t->bits_per_word ? : spi->bits_per_word;
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bits_per_word = bits_per_word ? : 8;
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wsize = bits_per_word >> 3; /* in bytes */
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if (prev_speed_hz != speed_hz
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|| prev_bits_per_word != bits_per_word) {
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u32 n = (c->baseclk + speed_hz - 1) / speed_hz;
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if (n < 1)
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n = 1;
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else if (n > 0xff)
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n = 0xff;
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/* enter config mode */
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txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR,
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TXx9_SPMCR);
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txx9spi_wr(c, (n << 8) | bits_per_word, TXx9_SPCR1);
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/* enter active mode */
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txx9spi_wr(c, mcr | TXx9_SPMCR_ACTIVE, TXx9_SPMCR);
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prev_speed_hz = speed_hz;
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prev_bits_per_word = bits_per_word;
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}
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if (cs_change)
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txx9spi_cs_func(spi, c, 1, cs_delay);
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cs_change = t->cs_change;
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while (len) {
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unsigned int count = SPI_FIFO_SIZE;
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int i;
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u32 cr0;
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if (len < count * wsize)
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count = len / wsize;
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/* now tx must be idle... */
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while (!(txx9spi_rd(c, TXx9_SPSR) & TXx9_SPSR_SIDLE))
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cpu_relax();
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cr0 = txx9spi_rd(c, TXx9_SPCR0);
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cr0 &= ~TXx9_SPCR0_RXIFL_MASK;
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cr0 |= (count - 1) << 12;
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/* enable rx intr */
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cr0 |= TXx9_SPCR0_RBSIE;
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txx9spi_wr(c, cr0, TXx9_SPCR0);
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/* send */
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for (i = 0; i < count; i++) {
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if (txbuf) {
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data = (wsize == 1)
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? *(const u8 *)txbuf
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: *(const u16 *)txbuf;
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txx9spi_wr(c, data, TXx9_SPDR);
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txbuf += wsize;
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} else
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txx9spi_wr(c, 0, TXx9_SPDR);
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}
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/* wait all rx data */
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wait_event(c->waitq,
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txx9spi_rd(c, TXx9_SPSR) & TXx9_SPSR_RBSI);
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/* receive */
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for (i = 0; i < count; i++) {
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data = txx9spi_rd(c, TXx9_SPDR);
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if (rxbuf) {
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if (wsize == 1)
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*(u8 *)rxbuf = data;
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else
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*(u16 *)rxbuf = data;
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rxbuf += wsize;
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}
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}
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len -= count * wsize;
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}
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m->actual_length += t->len;
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if (t->delay_usecs)
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udelay(t->delay_usecs);
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if (!cs_change)
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continue;
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if (t->transfer_list.next == &m->transfers)
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break;
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/* sometimes a short mid-message deselect of the chip
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* may be needed to terminate a mode or command
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*/
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txx9spi_cs_func(spi, c, 0, cs_delay);
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}
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exit:
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m->status = status;
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m->complete(m->context);
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/* normally deactivate chipselect ... unless no error and
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* cs_change has hinted that the next message will probably
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* be for this chip too.
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*/
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if (!(status == 0 && cs_change))
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txx9spi_cs_func(spi, c, 0, cs_delay);
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/* enter config mode */
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txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR);
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}
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static void txx9spi_work(struct work_struct *work)
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{
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struct txx9spi *c = container_of(work, struct txx9spi, work);
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unsigned long flags;
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spin_lock_irqsave(&c->lock, flags);
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while (!list_empty(&c->queue)) {
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struct spi_message *m;
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m = container_of(c->queue.next, struct spi_message, queue);
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list_del_init(&m->queue);
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spin_unlock_irqrestore(&c->lock, flags);
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txx9spi_work_one(c, m);
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spin_lock_irqsave(&c->lock, flags);
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}
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spin_unlock_irqrestore(&c->lock, flags);
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}
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static int txx9spi_transfer(struct spi_device *spi, struct spi_message *m)
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{
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struct spi_master *master = spi->master;
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struct txx9spi *c = spi_master_get_devdata(master);
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struct spi_transfer *t;
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unsigned long flags;
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m->actual_length = 0;
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/* check each transfer's parameters */
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list_for_each_entry (t, &m->transfers, transfer_list) {
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u32 speed_hz = t->speed_hz ? : spi->max_speed_hz;
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u8 bits_per_word = t->bits_per_word ? : spi->bits_per_word;
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bits_per_word = bits_per_word ? : 8;
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if (!t->tx_buf && !t->rx_buf && t->len)
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return -EINVAL;
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if (bits_per_word != 8 && bits_per_word != 16)
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return -EINVAL;
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if (t->len & ((bits_per_word >> 3) - 1))
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return -EINVAL;
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if (speed_hz < c->min_speed_hz || speed_hz > c->max_speed_hz)
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return -EINVAL;
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}
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spin_lock_irqsave(&c->lock, flags);
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list_add_tail(&m->queue, &c->queue);
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queue_work(c->workqueue, &c->work);
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spin_unlock_irqrestore(&c->lock, flags);
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return 0;
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}
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static int __init txx9spi_probe(struct platform_device *dev)
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{
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struct spi_master *master;
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struct txx9spi *c;
|
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struct resource *res;
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int ret = -ENODEV;
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u32 mcr;
|
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master = spi_alloc_master(&dev->dev, sizeof(*c));
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if (!master)
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return ret;
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c = spi_master_get_devdata(master);
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c->irq = -1;
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platform_set_drvdata(dev, master);
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INIT_WORK(&c->work, txx9spi_work);
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spin_lock_init(&c->lock);
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INIT_LIST_HEAD(&c->queue);
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init_waitqueue_head(&c->waitq);
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c->clk = clk_get(&dev->dev, "spi-baseclk");
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if (IS_ERR(c->clk)) {
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ret = PTR_ERR(c->clk);
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c->clk = NULL;
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goto exit;
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}
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ret = clk_enable(c->clk);
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if (ret) {
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clk_put(c->clk);
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c->clk = NULL;
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goto exit;
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}
|
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c->baseclk = clk_get_rate(c->clk);
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c->min_speed_hz = (c->baseclk + 0xff - 1) / 0xff;
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c->max_speed_hz = c->baseclk;
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res = platform_get_resource(dev, IORESOURCE_MEM, 0);
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if (!res)
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goto exit;
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c->membase = ioremap(res->start, res->end - res->start + 1);
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if (!c->membase)
|
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goto exit;
|
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|
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/* enter config mode */
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mcr = txx9spi_rd(c, TXx9_SPMCR);
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mcr &= ~(TXx9_SPMCR_OPMODE | TXx9_SPMCR_SPSTP | TXx9_SPMCR_BCLR);
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txx9spi_wr(c, mcr | TXx9_SPMCR_CONFIG | TXx9_SPMCR_BCLR, TXx9_SPMCR);
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c->irq = platform_get_irq(dev, 0);
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if (c->irq < 0)
|
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goto exit;
|
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ret = request_irq(c->irq, txx9spi_interrupt, 0, dev->name, c);
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if (ret) {
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c->irq = -1;
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goto exit;
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}
|
||||
|
||||
c->workqueue = create_singlethread_workqueue(master->cdev.dev->bus_id);
|
||||
if (!c->workqueue)
|
||||
goto exit;
|
||||
c->last_chipselect = -1;
|
||||
|
||||
dev_info(&dev->dev, "at %#llx, irq %d, %dMHz\n",
|
||||
(unsigned long long)res->start, c->irq,
|
||||
(c->baseclk + 500000) / 1000000);
|
||||
|
||||
master->bus_num = dev->id;
|
||||
master->setup = txx9spi_setup;
|
||||
master->transfer = txx9spi_transfer;
|
||||
master->num_chipselect = (u16)UINT_MAX; /* any GPIO numbers */
|
||||
|
||||
ret = spi_register_master(master);
|
||||
if (ret)
|
||||
goto exit;
|
||||
return 0;
|
||||
exit:
|
||||
if (c->workqueue)
|
||||
destroy_workqueue(c->workqueue);
|
||||
if (c->irq >= 0)
|
||||
free_irq(c->irq, c);
|
||||
if (c->membase)
|
||||
iounmap(c->membase);
|
||||
if (c->clk) {
|
||||
clk_disable(c->clk);
|
||||
clk_put(c->clk);
|
||||
}
|
||||
platform_set_drvdata(dev, NULL);
|
||||
spi_master_put(master);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int __exit txx9spi_remove(struct platform_device *dev)
|
||||
{
|
||||
struct spi_master *master = spi_master_get(platform_get_drvdata(dev));
|
||||
struct txx9spi *c = spi_master_get_devdata(master);
|
||||
|
||||
spi_unregister_master(master);
|
||||
platform_set_drvdata(dev, NULL);
|
||||
destroy_workqueue(c->workqueue);
|
||||
free_irq(c->irq, c);
|
||||
iounmap(c->membase);
|
||||
clk_disable(c->clk);
|
||||
clk_put(c->clk);
|
||||
spi_master_put(master);
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct platform_driver txx9spi_driver = {
|
||||
.remove = __exit_p(txx9spi_remove),
|
||||
.driver = {
|
||||
.name = "txx9spi",
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init txx9spi_init(void)
|
||||
{
|
||||
return platform_driver_probe(&txx9spi_driver, txx9spi_probe);
|
||||
}
|
||||
subsys_initcall(txx9spi_init);
|
||||
|
||||
static void __exit txx9spi_exit(void)
|
||||
{
|
||||
platform_driver_unregister(&txx9spi_driver);
|
||||
}
|
||||
module_exit(txx9spi_exit);
|
||||
|
||||
MODULE_DESCRIPTION("TXx9 SPI Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
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