Merge tag 'renesas-soc2-for-v3.12' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
From Simon Horman: Second Round of Renesas ARM based SoC updates for v3.12 * Increased clock coverage for r8a7740 and r8a7790 SoCs * tag 'renesas-soc2-for-v3.12' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: r8a7740: Add TPU clock entry for DT platforms ARM: shmobile: r8a7790: clocks for Ether support ARM: shmobile: r8a7740: Fix TPU clock name ARM: shmobile: Insert align directives before 4 bytes data ARM: shmobile: Force ARM mode to compile reset vector for secondary CPUs ARM: shmobile: fix compile error when CONFIG_THUMB2_KERNEL=y ARM: shmobile: Update romImage to relocate appended DTB Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
Коммит
f2d6e550a2
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@ -55,12 +55,47 @@ __tmp_stack:
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__continue:
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#endif /* CONFIG_ZBOOT_ROM_MMC || CONFIG_ZBOOT_ROM_SH_MOBILE_SDHI */
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/* Set board ID necessary for boot */
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ldr r7, 1f @ Set machine type register
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mov r8, #0 @ pass null pointer as atag
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adr r0, dtb_info
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ldmia r0, {r1, r3, r4, r5, r7}
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sub r0, r0, r1 @ calculate the delta offset
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add r5, r5, r0 @ _edata
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ldr lr, [r5, #0] @ check if valid DTB is present
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cmp lr, r3
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bne 0f
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add r9, r7, #31 @ rounded up to a multiple
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bic r9, r9, #31 @ ... of 32 bytes
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add r6, r9, r5 @ copy from _edata
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add r9, r9, r4 @ to MEMORY_START
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1: ldmdb r6!, {r0 - r3, r10 - r12, lr}
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cmp r6, r5
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stmdb r9!, {r0 - r3, r10 - r12, lr}
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bhi 1b
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/* Success: Zero board ID, pointer to start of memory for atag/dtb */
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mov r7, #0
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mov r8, r4
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b 2f
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1 : .long MACH_TYPE
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.align 2
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dtb_info:
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.word dtb_info
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#ifndef __ARMEB__
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.word 0xedfe0dd0 @ sig is 0xd00dfeed big endian
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#else
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.word 0xd00dfeed
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#endif
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.word MEMORY_START
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.word _edata
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.word 0x4000 @ maximum DTB size
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0:
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/* Failure: Zero board ID, NULL atag/dtb */
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mov r7, #0
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mov r8, #0 @ pass null pointer as atag
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2 :
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#endif /* CONFIG_ZBOOT_ROM */
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@ -596,7 +596,8 @@ static struct clk_lookup lookups[] = {
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CLKDEV_DEV_ID("e6bd0000.mmcif", &mstp_clks[MSTP312]),
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CLKDEV_DEV_ID("r8a7740-gether", &mstp_clks[MSTP309]),
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CLKDEV_DEV_ID("e9a00000.sh-eth", &mstp_clks[MSTP309]),
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CLKDEV_DEV_ID("renesas_tpu_pwm", &mstp_clks[MSTP304]),
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CLKDEV_DEV_ID("renesas-tpu-pwm", &mstp_clks[MSTP304]),
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CLKDEV_DEV_ID("e6600000.pwm", &mstp_clks[MSTP304]),
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CLKDEV_DEV_ID("sh_mobile_sdhi.2", &mstp_clks[MSTP415]),
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CLKDEV_DEV_ID("e6870000.sdhi", &mstp_clks[MSTP415]),
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@ -51,6 +51,7 @@
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#define SMSTPCR3 0xe615013c
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#define SMSTPCR5 0xe6150144
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#define SMSTPCR7 0xe615014c
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#define SMSTPCR8 0xe6150990
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#define SDCKCR 0xE6150074
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#define SD2CKCR 0xE6150078
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@ -180,6 +181,7 @@ static struct clk div6_clks[DIV6_NR] = {
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/* MSTP */
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enum {
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MSTP813,
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MSTP721, MSTP720,
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MSTP717, MSTP716,
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MSTP522,
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@ -190,6 +192,7 @@ enum {
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};
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static struct clk mstp_clks[MSTP_NR] = {
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[MSTP813] = SH_CLK_MSTP32(&p_clk, SMSTPCR8, 13, 0), /* Ether */
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[MSTP721] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 21, 0), /* SCIF0 */
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[MSTP720] = SH_CLK_MSTP32(&p_clk, SMSTPCR7, 20, 0), /* SCIF1 */
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[MSTP717] = SH_CLK_MSTP32(&zs_clk, SMSTPCR7, 17, 0), /* HSCIF0 */
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@ -258,6 +261,7 @@ static struct clk_lookup lookups[] = {
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CLKDEV_DEV_ID("sh-sci.7", &mstp_clks[MSTP720]),
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CLKDEV_DEV_ID("sh-sci.8", &mstp_clks[MSTP717]),
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CLKDEV_DEV_ID("sh-sci.9", &mstp_clks[MSTP716]),
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CLKDEV_DEV_ID("r8a7790-ether", &mstp_clks[MSTP813]),
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CLKDEV_DEV_ID("rcar_thermal", &mstp_clks[MSTP522]),
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CLKDEV_DEV_ID("ee200000.mmcif", &mstp_clks[MSTP315]),
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CLKDEV_DEV_ID("sh_mmcif.0", &mstp_clks[MSTP315]),
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@ -37,13 +37,15 @@ ENTRY(shmobile_boot_scu)
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lsl r1, r1, #3 @ we will shift by cpu_id * 8 bits
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ldr r2, [r0, #8] @ SCU Power Status Register
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mov r3, #3
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bic r2, r2, r3, lsl r1 @ Clear bits of our CPU (Run Mode)
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lsl r3, r3, r1
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bic r2, r2, r3 @ Clear bits of our CPU (Run Mode)
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str r2, [r0, #8] @ write back
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b shmobile_invalidate_start
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ENDPROC(shmobile_boot_scu)
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.text
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.align 2
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.globl shmobile_scu_base
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shmobile_scu_base:
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.space 4
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@ -24,12 +24,16 @@ ENDPROC(shmobile_invalidate_start)
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* This will be mapped at address 0 by SBAR register.
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* We need _long_ jump to the physical address.
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*/
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.arm
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.align 12
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ENTRY(shmobile_boot_vector)
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ldr r0, 2f
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ldr pc, 1f
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ldr r1, 1f
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bx r1
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ENDPROC(shmobile_boot_vector)
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.align 2
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.globl shmobile_boot_fn
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shmobile_boot_fn:
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1: .space 4
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@ -1,7 +1,6 @@
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#ifndef ZBOOT_H
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#define ZBOOT_H
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#include <asm/mach-types.h>
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#include <mach/zboot_macros.h>
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/**************************************************
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@ -11,7 +10,6 @@
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**************************************************/
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#ifdef CONFIG_MACH_MACKEREL
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#define MACH_TYPE MACH_TYPE_MACKEREL
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#define MEMORY_START 0x40000000
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#include "mach/head-mackerel.txt"
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#else
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@ -41,6 +41,7 @@
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sh7372_resume_core_standby_sysc:
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ldr pc, 1f
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.align 2
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.globl sh7372_cpu_resume
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sh7372_cpu_resume:
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1: .space 4
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@ -96,6 +97,7 @@ sh7372_do_idle_sysc:
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1:
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b 1b
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.align 2
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kernel_flush:
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.word v7_flush_dcache_all
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#endif
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