x86/PCI: Add "pci=big_root_window" option for AMD 64-bit windows
Only try to enable a 64-bit window on AMD CPUs when "pci=big_root_window" is specified. This taints the kernel because the new 64-bit window uses address space we don't know anything about, and it may contain unreported devices or memory that would conflict with the window. The pci_amd_enable_64bit_bar() quirk that enables the window is specific to AMD CPUs. The generic solution would be to have the firmware enable the window and describe it in the host bridge's _CRS method, or at least describe it in the _PRS method so the OS would have the option of enabling it. Signed-off-by: Christian König <christian.koenig@amd.com> [bhelgaas: changelog, extend doc, mention taint in dmesg] Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
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@ -3094,6 +3094,12 @@
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pcie_scan_all Scan all possible PCIe devices. Otherwise we
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pcie_scan_all Scan all possible PCIe devices. Otherwise we
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only look for one device below a PCIe downstream
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only look for one device below a PCIe downstream
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port.
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port.
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big_root_window Try to add a big 64bit memory window to the PCIe
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root complex on AMD CPUs. Some GFX hardware
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can resize a BAR to allow access to all VRAM.
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Adding the window is slightly risky (it may
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conflict with unreported devices), so this
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taints the kernel.
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pcie_aspm= [PCIE] Forcibly enable or disable PCIe Active State Power
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pcie_aspm= [PCIE] Forcibly enable or disable PCIe Active State Power
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Management.
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Management.
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@ -38,6 +38,7 @@ do { \
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#define PCI_NOASSIGN_ROMS 0x80000
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#define PCI_NOASSIGN_ROMS 0x80000
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#define PCI_ROOT_NO_CRS 0x100000
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#define PCI_ROOT_NO_CRS 0x100000
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#define PCI_NOASSIGN_BARS 0x200000
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#define PCI_NOASSIGN_BARS 0x200000
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#define PCI_BIG_ROOT_WINDOW 0x400000
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extern unsigned int pci_probe;
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extern unsigned int pci_probe;
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extern unsigned long pirq_table_addr;
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extern unsigned long pirq_table_addr;
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@ -594,6 +594,11 @@ char *__init pcibios_setup(char *str)
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} else if (!strcmp(str, "nocrs")) {
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} else if (!strcmp(str, "nocrs")) {
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pci_probe |= PCI_ROOT_NO_CRS;
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pci_probe |= PCI_ROOT_NO_CRS;
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return NULL;
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return NULL;
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#ifdef CONFIG_PHYS_ADDR_T_64BIT
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} else if (!strcmp(str, "big_root_window")) {
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pci_probe |= PCI_BIG_ROOT_WINDOW;
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return NULL;
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#endif
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} else if (!strcmp(str, "earlydump")) {
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} else if (!strcmp(str, "earlydump")) {
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pci_early_dump_regs = 1;
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pci_early_dump_regs = 1;
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return NULL;
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return NULL;
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@ -667,6 +667,9 @@ static void pci_amd_enable_64bit_bar(struct pci_dev *dev)
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struct resource *res, *conflict;
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struct resource *res, *conflict;
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struct pci_dev *other;
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struct pci_dev *other;
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if (!(pci_probe & PCI_BIG_ROOT_WINDOW))
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return;
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/* Check that we are the only device of that type */
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/* Check that we are the only device of that type */
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other = pci_get_device(dev->vendor, dev->device, NULL);
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other = pci_get_device(dev->vendor, dev->device, NULL);
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if (other != dev ||
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if (other != dev ||
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@ -714,7 +717,9 @@ static void pci_amd_enable_64bit_bar(struct pci_dev *dev)
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res->start = conflict->end + 1;
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res->start = conflict->end + 1;
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}
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}
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dev_info(&dev->dev, "adding root bus resource %pR\n", res);
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dev_info(&dev->dev, "adding root bus resource %pR (tainting kernel)\n",
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res);
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add_taint(TAINT_FIRMWARE_WORKAROUND, LOCKDEP_STILL_OK);
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base = ((res->start >> 8) & AMD_141b_MMIO_BASE_MMIOBASE_MASK) |
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base = ((res->start >> 8) & AMD_141b_MMIO_BASE_MMIOBASE_MASK) |
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AMD_141b_MMIO_BASE_RE_MASK | AMD_141b_MMIO_BASE_WE_MASK;
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AMD_141b_MMIO_BASE_RE_MASK | AMD_141b_MMIO_BASE_WE_MASK;
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