[MIPS] Alchemy: Fix build by conversion to irq_cpu.c.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle
Родитель
fb8dd01422
Коммит
f3e8d1da38
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@ -137,6 +137,7 @@ config SOC_AU1200
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config SOC_AU1X00
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bool
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select 64BIT_PHYS_ADDR
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select IRQ_CPU
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select SYS_HAS_CPU_MIPS32_R1
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select SYS_SUPPORTS_32BIT_KERNEL
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select SYS_SUPPORTS_APM_EMULATION
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@ -1,11 +1,10 @@
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/*
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* BRIEF MODULE DESCRIPTION
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* Au1000 interrupt routines.
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*
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* Copyright 2001 MontaVista Software Inc.
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* Author: MontaVista Software, Inc.
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* ppopov@mvista.com or source@mvista.com
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*
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* Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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@ -32,6 +31,7 @@
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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#include <asm/mach-au1x00/au1000.h>
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#ifdef CONFIG_MIPS_PB1000
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@ -44,7 +44,7 @@
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#define EXT_INTC1_REQ1 5 /* IP 5 */
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#define MIPS_TIMER_IP 7 /* IP 7 */
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void (*board_init_irq)(void);
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void (*board_init_irq)(void) __initdata = NULL;
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static DEFINE_SPINLOCK(irq_lock);
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@ -134,12 +134,14 @@ void restore_au1xxx_intctl(void)
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inline void local_enable_irq(unsigned int irq_nr)
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{
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if (irq_nr > AU1000_LAST_INTC0_INT) {
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au_writel(1 << (irq_nr - 32), IC1_MASKSET);
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au_writel(1 << (irq_nr - 32), IC1_WAKESET);
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unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
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if (bit >= 32) {
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au_writel(1 << (bit - 32), IC1_MASKSET);
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au_writel(1 << (bit - 32), IC1_WAKESET);
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} else {
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au_writel(1 << irq_nr, IC0_MASKSET);
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au_writel(1 << irq_nr, IC0_WAKESET);
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au_writel(1 << bit, IC0_MASKSET);
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au_writel(1 << bit, IC0_WAKESET);
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}
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au_sync();
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}
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@ -147,12 +149,14 @@ inline void local_enable_irq(unsigned int irq_nr)
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inline void local_disable_irq(unsigned int irq_nr)
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{
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if (irq_nr > AU1000_LAST_INTC0_INT) {
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au_writel(1 << (irq_nr - 32), IC1_MASKCLR);
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au_writel(1 << (irq_nr - 32), IC1_WAKECLR);
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unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
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if (bit >= 32) {
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au_writel(1 << (bit - 32), IC1_MASKCLR);
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au_writel(1 << (bit - 32), IC1_WAKECLR);
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} else {
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au_writel(1 << irq_nr, IC0_MASKCLR);
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au_writel(1 << irq_nr, IC0_WAKECLR);
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au_writel(1 << bit, IC0_MASKCLR);
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au_writel(1 << bit, IC0_WAKECLR);
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}
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au_sync();
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}
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@ -160,12 +164,14 @@ inline void local_disable_irq(unsigned int irq_nr)
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static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr)
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{
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if (irq_nr > AU1000_LAST_INTC0_INT) {
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au_writel(1 << (irq_nr - 32), IC1_RISINGCLR);
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au_writel(1 << (irq_nr - 32), IC1_MASKCLR);
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unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
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if (bit >= 32) {
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au_writel(1 << (bit - 32), IC1_RISINGCLR);
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au_writel(1 << (bit - 32), IC1_MASKCLR);
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} else {
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au_writel(1 << irq_nr, IC0_RISINGCLR);
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au_writel(1 << irq_nr, IC0_MASKCLR);
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au_writel(1 << bit, IC0_RISINGCLR);
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au_writel(1 << bit, IC0_MASKCLR);
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}
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au_sync();
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}
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@ -173,12 +179,14 @@ static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr)
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static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr)
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{
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if (irq_nr > AU1000_LAST_INTC0_INT) {
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au_writel(1 << (irq_nr - 32), IC1_FALLINGCLR);
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au_writel(1 << (irq_nr - 32), IC1_MASKCLR);
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unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
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if (bit >= 32) {
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au_writel(1 << (bit - 32), IC1_FALLINGCLR);
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au_writel(1 << (bit - 32), IC1_MASKCLR);
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} else {
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au_writel(1 << irq_nr, IC0_FALLINGCLR);
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au_writel(1 << irq_nr, IC0_MASKCLR);
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au_writel(1 << bit, IC0_FALLINGCLR);
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au_writel(1 << bit, IC0_MASKCLR);
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}
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au_sync();
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}
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@ -186,17 +194,20 @@ static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr)
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static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr)
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{
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/* This may assume that we don't get interrupts from
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unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
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/*
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* This may assume that we don't get interrupts from
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* both edges at once, or if we do, that we don't care.
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*/
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if (irq_nr > AU1000_LAST_INTC0_INT) {
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au_writel(1 << (irq_nr - 32), IC1_FALLINGCLR);
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au_writel(1 << (irq_nr - 32), IC1_RISINGCLR);
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au_writel(1 << (irq_nr - 32), IC1_MASKCLR);
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if (bit >= 32) {
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au_writel(1 << (bit - 32), IC1_FALLINGCLR);
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au_writel(1 << (bit - 32), IC1_RISINGCLR);
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au_writel(1 << (bit - 32), IC1_MASKCLR);
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} else {
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au_writel(1 << irq_nr, IC0_FALLINGCLR);
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au_writel(1 << irq_nr, IC0_RISINGCLR);
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au_writel(1 << irq_nr, IC0_MASKCLR);
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au_writel(1 << bit, IC0_FALLINGCLR);
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au_writel(1 << bit, IC0_RISINGCLR);
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au_writel(1 << bit, IC0_MASKCLR);
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}
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au_sync();
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}
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@ -213,10 +224,8 @@ static inline void mask_and_ack_level_irq(unsigned int irq_nr)
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au_sync();
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}
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#endif
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return;
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}
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static void end_irq(unsigned int irq_nr)
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{
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if (!(irq_desc[irq_nr].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
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@ -341,114 +350,118 @@ void startup_match20_interrupt(irq_handler_t handler)
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}
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#endif
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static void setup_local_irq(unsigned int irq_nr, int type, int int_req)
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static void __init setup_local_irq(unsigned int irq_nr, int type, int int_req)
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{
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if (irq_nr > AU1000_MAX_INTR) return;
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unsigned int bit = irq_nr - AU1000_INTC0_INT_BASE;
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if (irq_nr > AU1000_MAX_INTR)
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return;
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/* Config2[n], Config1[n], Config0[n] */
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if (irq_nr > AU1000_LAST_INTC0_INT) {
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if (bit >= 32) {
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switch (type) {
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case INTC_INT_RISE_EDGE: /* 0:0:1 */
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au_writel(1 << (irq_nr - 32), IC1_CFG2CLR);
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au_writel(1 << (irq_nr - 32), IC1_CFG1CLR);
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au_writel(1 << (irq_nr - 32), IC1_CFG0SET);
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au_writel(1 << (bit - 32), IC1_CFG2CLR);
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au_writel(1 << (bit - 32), IC1_CFG1CLR);
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au_writel(1 << (bit - 32), IC1_CFG0SET);
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set_irq_chip(irq_nr, &rise_edge_irq_type);
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break;
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case INTC_INT_FALL_EDGE: /* 0:1:0 */
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au_writel(1 << (irq_nr - 32), IC1_CFG2CLR);
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au_writel(1 << (irq_nr - 32), IC1_CFG1SET);
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au_writel(1 << (irq_nr - 32), IC1_CFG0CLR);
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au_writel(1 << (bit - 32), IC1_CFG2CLR);
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au_writel(1 << (bit - 32), IC1_CFG1SET);
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au_writel(1 << (bit - 32), IC1_CFG0CLR);
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set_irq_chip(irq_nr, &fall_edge_irq_type);
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break;
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case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
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au_writel(1 << (irq_nr - 32), IC1_CFG2CLR);
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au_writel(1 << (irq_nr - 32), IC1_CFG1SET);
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au_writel(1 << (irq_nr - 32), IC1_CFG0SET);
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au_writel(1 << (bit - 32), IC1_CFG2CLR);
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au_writel(1 << (bit - 32), IC1_CFG1SET);
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au_writel(1 << (bit - 32), IC1_CFG0SET);
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set_irq_chip(irq_nr, &either_edge_irq_type);
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break;
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case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
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au_writel(1 << (irq_nr - 32), IC1_CFG2SET);
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au_writel(1 << (irq_nr - 32), IC1_CFG1CLR);
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au_writel(1 << (irq_nr - 32), IC1_CFG0SET);
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au_writel(1 << (bit - 32), IC1_CFG2SET);
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au_writel(1 << (bit - 32), IC1_CFG1CLR);
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au_writel(1 << (bit - 32), IC1_CFG0SET);
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set_irq_chip(irq_nr, &level_irq_type);
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break;
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case INTC_INT_LOW_LEVEL: /* 1:1:0 */
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au_writel(1 << (irq_nr - 32), IC1_CFG2SET);
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au_writel(1 << (irq_nr - 32), IC1_CFG1SET);
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au_writel(1 << (irq_nr - 32), IC1_CFG0CLR);
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au_writel(1 << (bit - 32), IC1_CFG2SET);
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au_writel(1 << (bit - 32), IC1_CFG1SET);
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au_writel(1 << (bit - 32), IC1_CFG0CLR);
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set_irq_chip(irq_nr, &level_irq_type);
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break;
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case INTC_INT_DISABLED: /* 0:0:0 */
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au_writel(1 << (irq_nr - 32), IC1_CFG0CLR);
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au_writel(1 << (irq_nr - 32), IC1_CFG1CLR);
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au_writel(1 << (irq_nr - 32), IC1_CFG2CLR);
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au_writel(1 << (bit - 32), IC1_CFG0CLR);
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au_writel(1 << (bit - 32), IC1_CFG1CLR);
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au_writel(1 << (bit - 32), IC1_CFG2CLR);
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break;
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default: /* disable the interrupt */
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printk(KERN_WARNING "unexpected int type %d (irq %d)\n",
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type, irq_nr);
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au_writel(1 << (irq_nr - 32), IC1_CFG0CLR);
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au_writel(1 << (irq_nr - 32), IC1_CFG1CLR);
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au_writel(1 << (irq_nr - 32), IC1_CFG2CLR);
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au_writel(1 << (bit - 32), IC1_CFG0CLR);
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au_writel(1 << (bit - 32), IC1_CFG1CLR);
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au_writel(1 << (bit - 32), IC1_CFG2CLR);
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return;
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}
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if (int_req) /* assign to interrupt request 1 */
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au_writel(1 << (irq_nr - 32), IC1_ASSIGNCLR);
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au_writel(1 << (bit - 32), IC1_ASSIGNCLR);
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else /* assign to interrupt request 0 */
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au_writel(1 << (irq_nr - 32), IC1_ASSIGNSET);
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au_writel(1 << (irq_nr - 32), IC1_SRCSET);
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au_writel(1 << (irq_nr - 32), IC1_MASKCLR);
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au_writel(1 << (irq_nr - 32), IC1_WAKECLR);
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au_writel(1 << (bit - 32), IC1_ASSIGNSET);
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au_writel(1 << (bit - 32), IC1_SRCSET);
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au_writel(1 << (bit - 32), IC1_MASKCLR);
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au_writel(1 << (bit - 32), IC1_WAKECLR);
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} else {
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switch (type) {
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case INTC_INT_RISE_EDGE: /* 0:0:1 */
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au_writel(1 << irq_nr, IC0_CFG2CLR);
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au_writel(1 << irq_nr, IC0_CFG1CLR);
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au_writel(1 << irq_nr, IC0_CFG0SET);
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au_writel(1 << bit, IC0_CFG2CLR);
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au_writel(1 << bit, IC0_CFG1CLR);
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au_writel(1 << bit, IC0_CFG0SET);
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set_irq_chip(irq_nr, &rise_edge_irq_type);
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break;
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case INTC_INT_FALL_EDGE: /* 0:1:0 */
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au_writel(1 << irq_nr, IC0_CFG2CLR);
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au_writel(1 << irq_nr, IC0_CFG1SET);
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au_writel(1 << irq_nr, IC0_CFG0CLR);
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au_writel(1 << bit, IC0_CFG2CLR);
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au_writel(1 << bit, IC0_CFG1SET);
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au_writel(1 << bit, IC0_CFG0CLR);
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set_irq_chip(irq_nr, &fall_edge_irq_type);
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break;
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case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
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au_writel(1 << irq_nr, IC0_CFG2CLR);
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au_writel(1 << irq_nr, IC0_CFG1SET);
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au_writel(1 << irq_nr, IC0_CFG0SET);
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au_writel(1 << bit, IC0_CFG2CLR);
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au_writel(1 << bit, IC0_CFG1SET);
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au_writel(1 << bit, IC0_CFG0SET);
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set_irq_chip(irq_nr, &either_edge_irq_type);
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break;
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case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
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au_writel(1 << irq_nr, IC0_CFG2SET);
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au_writel(1 << irq_nr, IC0_CFG1CLR);
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au_writel(1 << irq_nr, IC0_CFG0SET);
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au_writel(1 << bit, IC0_CFG2SET);
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au_writel(1 << bit, IC0_CFG1CLR);
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au_writel(1 << bit, IC0_CFG0SET);
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set_irq_chip(irq_nr, &level_irq_type);
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break;
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case INTC_INT_LOW_LEVEL: /* 1:1:0 */
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au_writel(1 << irq_nr, IC0_CFG2SET);
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au_writel(1 << irq_nr, IC0_CFG1SET);
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au_writel(1 << irq_nr, IC0_CFG0CLR);
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au_writel(1 << bit, IC0_CFG2SET);
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au_writel(1 << bit, IC0_CFG1SET);
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au_writel(1 << bit, IC0_CFG0CLR);
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set_irq_chip(irq_nr, &level_irq_type);
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break;
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case INTC_INT_DISABLED: /* 0:0:0 */
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au_writel(1 << irq_nr, IC0_CFG0CLR);
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au_writel(1 << irq_nr, IC0_CFG1CLR);
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au_writel(1 << irq_nr, IC0_CFG2CLR);
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au_writel(1 << bit, IC0_CFG0CLR);
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au_writel(1 << bit, IC0_CFG1CLR);
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au_writel(1 << bit, IC0_CFG2CLR);
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break;
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default: /* disable the interrupt */
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printk(KERN_WARNING "unexpected int type %d (irq %d)\n",
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type, irq_nr);
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au_writel(1 << irq_nr, IC0_CFG0CLR);
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au_writel(1 << irq_nr, IC0_CFG1CLR);
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au_writel(1 << irq_nr, IC0_CFG2CLR);
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au_writel(1 << bit, IC0_CFG0CLR);
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au_writel(1 << bit, IC0_CFG1CLR);
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au_writel(1 << bit, IC0_CFG2CLR);
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return;
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}
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if (int_req) /* assign to interrupt request 1 */
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au_writel(1 << irq_nr, IC0_ASSIGNCLR);
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au_writel(1 << bit, IC0_ASSIGNCLR);
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else /* assign to interrupt request 0 */
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au_writel(1 << irq_nr, IC0_ASSIGNSET);
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au_writel(1 << irq_nr, IC0_SRCSET);
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au_writel(1 << irq_nr, IC0_MASKCLR);
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au_writel(1 << irq_nr, IC0_WAKECLR);
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au_writel(1 << bit, IC0_ASSIGNSET);
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au_writel(1 << bit, IC0_SRCSET);
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au_writel(1 << bit, IC0_MASKCLR);
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au_writel(1 << bit, IC0_WAKECLR);
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}
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au_sync();
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}
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@ -461,8 +474,8 @@ static void setup_local_irq(unsigned int irq_nr, int type, int int_req)
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static void intc0_req0_irqdispatch(void)
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{
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int irq = 0;
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static unsigned long intc0_req0;
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unsigned int bit;
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intc0_req0 |= au_readl(IC0_REQ0INT);
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@ -481,25 +494,25 @@ static void intc0_req0_irqdispatch(void)
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return;
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}
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#endif
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irq = ffs(intc0_req0);
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intc0_req0 &= ~(1 << irq);
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do_IRQ(irq);
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bit = ffs(intc0_req0);
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intc0_req0 &= ~(1 << bit);
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do_IRQ(MIPS_CPU_IRQ_BASE + bit);
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}
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static void intc0_req1_irqdispatch(void)
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{
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int irq = 0;
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static unsigned long intc0_req1;
|
||||
unsigned int bit;
|
||||
|
||||
intc0_req1 |= au_readl(IC0_REQ1INT);
|
||||
|
||||
if (!intc0_req1)
|
||||
return;
|
||||
|
||||
irq = ffs(intc0_req1);
|
||||
intc0_req1 &= ~(1 << irq);
|
||||
do_IRQ(irq);
|
||||
bit = ffs(intc0_req1);
|
||||
intc0_req1 &= ~(1 << bit);
|
||||
do_IRQ(bit);
|
||||
}
|
||||
|
||||
|
||||
|
|
@ -509,43 +522,41 @@ static void intc0_req1_irqdispatch(void)
|
|||
*/
|
||||
static void intc1_req0_irqdispatch(void)
|
||||
{
|
||||
int irq = 0;
|
||||
static unsigned long intc1_req0;
|
||||
unsigned int bit;
|
||||
|
||||
intc1_req0 |= au_readl(IC1_REQ0INT);
|
||||
|
||||
if (!intc1_req0)
|
||||
return;
|
||||
|
||||
irq = ffs(intc1_req0);
|
||||
intc1_req0 &= ~(1 << irq);
|
||||
irq += 32;
|
||||
do_IRQ(irq);
|
||||
bit = ffs(intc1_req0);
|
||||
intc1_req0 &= ~(1 << bit);
|
||||
do_IRQ(MIPS_CPU_IRQ_BASE + 32 + bit);
|
||||
}
|
||||
|
||||
|
||||
static void intc1_req1_irqdispatch(void)
|
||||
{
|
||||
int irq = 0;
|
||||
static unsigned long intc1_req1;
|
||||
unsigned int bit;
|
||||
|
||||
intc1_req1 |= au_readl(IC1_REQ1INT);
|
||||
|
||||
if (!intc1_req1)
|
||||
return;
|
||||
|
||||
irq = ffs(intc1_req1);
|
||||
intc1_req1 &= ~(1 << irq);
|
||||
irq += 32;
|
||||
do_IRQ(irq);
|
||||
bit = ffs(intc1_req1);
|
||||
intc1_req1 &= ~(1 << bit);
|
||||
do_IRQ(MIPS_CPU_IRQ_BASE + 32 + bit);
|
||||
}
|
||||
|
||||
asmlinkage void plat_irq_dispatch(void)
|
||||
{
|
||||
unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
|
||||
unsigned int pending = read_c0_status() & read_c0_cause();
|
||||
|
||||
if (pending & CAUSEF_IP7)
|
||||
do_IRQ(63);
|
||||
do_IRQ(MIPS_CPU_IRQ_BASE + 7);
|
||||
else if (pending & CAUSEF_IP2)
|
||||
intc0_req0_irqdispatch();
|
||||
else if (pending & CAUSEF_IP3)
|
||||
|
|
@ -561,16 +572,14 @@ asmlinkage void plat_irq_dispatch(void)
|
|||
void __init arch_init_irq(void)
|
||||
{
|
||||
int i;
|
||||
unsigned long cp0_status;
|
||||
struct au1xxx_irqmap *imp;
|
||||
extern struct au1xxx_irqmap au1xxx_irq_map[];
|
||||
extern struct au1xxx_irqmap au1xxx_ic0_map[];
|
||||
extern int au1xxx_nr_irqs;
|
||||
extern int au1xxx_ic0_nr_irqs;
|
||||
|
||||
cp0_status = read_c0_status();
|
||||
|
||||
/* Initialize interrupt controllers to a safe state.
|
||||
/*
|
||||
* Initialize interrupt controllers to a safe state.
|
||||
*/
|
||||
au_writel(0xffffffff, IC0_CFG0CLR);
|
||||
au_writel(0xffffffff, IC0_CFG1CLR);
|
||||
|
|
@ -594,7 +603,10 @@ void __init arch_init_irq(void)
|
|||
au_writel(0xffffffff, IC1_RISINGCLR);
|
||||
au_writel(0x00000000, IC1_TESTBIT);
|
||||
|
||||
/* Initialize IC0, which is fixed per processor.
|
||||
mips_cpu_irq_init();
|
||||
|
||||
/*
|
||||
* Initialize IC0, which is fixed per processor.
|
||||
*/
|
||||
imp = au1xxx_ic0_map;
|
||||
for (i = 0; i < au1xxx_ic0_nr_irqs; i++) {
|
||||
|
|
@ -602,7 +614,8 @@ void __init arch_init_irq(void)
|
|||
imp++;
|
||||
}
|
||||
|
||||
/* Now set up the irq mapping for the board.
|
||||
/*
|
||||
* Now set up the irq mapping for the board.
|
||||
*/
|
||||
imp = au1xxx_irq_map;
|
||||
for (i = 0; i < au1xxx_nr_irqs; i++) {
|
||||
|
|
@ -615,5 +628,5 @@ void __init arch_init_irq(void)
|
|||
/* Board specific IRQ initialization.
|
||||
*/
|
||||
if (board_init_irq)
|
||||
(*board_init_irq)();
|
||||
board_init_irq();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -926,9 +926,11 @@ extern struct au1xxx_irqmap au1xxx_irq_map[];
|
|||
|
||||
#endif /* CONFIG_SOC_AU1200 */
|
||||
|
||||
#define AU1000_LAST_INTC0_INT 31
|
||||
#define AU1000_LAST_INTC1_INT 63
|
||||
#define AU1000_MAX_INTR 63
|
||||
#define AU1000_INTC0_INT_BASE (MIPS_CPU_IRQ_BASE + 0)
|
||||
#define AU1000_INTC0_INT_LAST (MIPS_CPU_IRQ_BASE + 31)
|
||||
#define AU1000_INTC1_INT_BASE (MIPS_CPU_IRQ_BASE + 32)
|
||||
#define AU1000_INTC1_INT_LAST (MIPS_CPU_IRQ_BASE + 63)
|
||||
#define AU1000_MAX_INTR (MIPS_CPU_IRQ_BASE + 63)
|
||||
#define INTX 0xFF /* not valid */
|
||||
|
||||
/* Programmable Counters 0 and 1 */
|
||||
|
|
|
|||
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