iio: humidity: hts221: move drdy enable logic in hts221_trig_set_state()
Move data-ready configuration in hts221_buffer.c since it is only related to trigger logic Signed-off-by: Lorenzo Bianconi <lorenzo.bianconi@st.com> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
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Родитель
21d841b2a4
Коммит
f3f0ae16f0
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@ -60,7 +60,6 @@ struct hts221_hw {
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extern const struct dev_pm_ops hts221_pm_ops;
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extern const struct dev_pm_ops hts221_pm_ops;
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int hts221_config_drdy(struct hts221_hw *hw, bool enable);
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int hts221_write_with_mask(struct hts221_hw *hw, u8 addr, u8 mask, u8 val);
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int hts221_write_with_mask(struct hts221_hw *hw, u8 addr, u8 mask, u8 val);
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int hts221_probe(struct iio_dev *iio_dev);
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int hts221_probe(struct iio_dev *iio_dev);
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int hts221_set_enable(struct hts221_hw *hw, bool enable);
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int hts221_set_enable(struct hts221_hw *hw, bool enable);
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@ -28,6 +28,8 @@
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#define HTS221_REG_DRDY_HL_MASK BIT(7)
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#define HTS221_REG_DRDY_HL_MASK BIT(7)
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#define HTS221_REG_DRDY_PP_OD_ADDR 0x22
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#define HTS221_REG_DRDY_PP_OD_ADDR 0x22
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#define HTS221_REG_DRDY_PP_OD_MASK BIT(6)
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#define HTS221_REG_DRDY_PP_OD_MASK BIT(6)
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#define HTS221_REG_DRDY_EN_ADDR 0x22
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#define HTS221_REG_DRDY_EN_MASK BIT(2)
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#define HTS221_REG_STATUS_ADDR 0x27
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#define HTS221_REG_STATUS_ADDR 0x27
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#define HTS221_RH_DRDY_MASK BIT(1)
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#define HTS221_RH_DRDY_MASK BIT(1)
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#define HTS221_TEMP_DRDY_MASK BIT(0)
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#define HTS221_TEMP_DRDY_MASK BIT(0)
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@ -36,8 +38,12 @@ static int hts221_trig_set_state(struct iio_trigger *trig, bool state)
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{
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{
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struct iio_dev *iio_dev = iio_trigger_get_drvdata(trig);
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struct iio_dev *iio_dev = iio_trigger_get_drvdata(trig);
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struct hts221_hw *hw = iio_priv(iio_dev);
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struct hts221_hw *hw = iio_priv(iio_dev);
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int err;
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return hts221_config_drdy(hw, state);
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err = hts221_write_with_mask(hw, HTS221_REG_DRDY_EN_ADDR,
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HTS221_REG_DRDY_EN_MASK, state);
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return err < 0 ? err : 0;
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}
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}
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static const struct iio_trigger_ops hts221_trigger_ops = {
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static const struct iio_trigger_ops hts221_trigger_ops = {
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@ -23,7 +23,6 @@
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#define HTS221_REG_CNTRL1_ADDR 0x20
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#define HTS221_REG_CNTRL1_ADDR 0x20
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#define HTS221_REG_CNTRL2_ADDR 0x21
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#define HTS221_REG_CNTRL2_ADDR 0x21
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#define HTS221_REG_CNTRL3_ADDR 0x22
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#define HTS221_REG_AVG_ADDR 0x10
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#define HTS221_REG_AVG_ADDR 0x10
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#define HTS221_REG_H_OUT_L 0x28
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#define HTS221_REG_H_OUT_L 0x28
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@ -36,9 +35,6 @@
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#define HTS221_BDU_MASK BIT(2)
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#define HTS221_BDU_MASK BIT(2)
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#define HTS221_ENABLE_MASK BIT(7)
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#define HTS221_ENABLE_MASK BIT(7)
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#define HTS221_DRDY_MASK BIT(2)
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/* calibration registers */
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/* calibration registers */
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#define HTS221_REG_0RH_CAL_X_H 0x36
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#define HTS221_REG_0RH_CAL_X_H 0x36
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#define HTS221_REG_1RH_CAL_X_H 0x3a
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#define HTS221_REG_1RH_CAL_X_H 0x3a
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@ -181,16 +177,6 @@ static int hts221_check_whoami(struct hts221_hw *hw)
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return 0;
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return 0;
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}
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}
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int hts221_config_drdy(struct hts221_hw *hw, bool enable)
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{
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int err;
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err = hts221_write_with_mask(hw, HTS221_REG_CNTRL3_ADDR,
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HTS221_DRDY_MASK, enable);
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return err < 0 ? err : 0;
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}
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static int hts221_update_odr(struct hts221_hw *hw, u8 odr)
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static int hts221_update_odr(struct hts221_hw *hw, u8 odr)
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{
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{
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int i, err;
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int i, err;
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