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WSL2-Linux-Kernel
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qspinlock: use signed temporaries for cmpxchg 

When building with W=2, the build log is flooded with

include/asm-generic/qrwlock.h:65:56: warning: pointer targets in passing argument 2 of 'atomic_try_cmpxchg_acquire' differ in signedness [-Wpointer-sign]
include/asm-generic/qrwlock.h:92:53: warning: pointer targets in passing argument 2 of 'atomic_try_cmpxchg_acquire' differ in signedness [-Wpointer-sign]
include/asm-generic/qspinlock.h:68:55: warning: pointer targets in passing argument 2 of 'atomic_try_cmpxchg_acquire' differ in signedness [-Wpointer-sign]
include/asm-generic/qspinlock.h:82:52: warning: pointer targets in passing argument 2 of 'atomic_try_cmpxchg_acquire' differ in signedness [-Wpointer-sign]

The atomics are built on top of signed integers, but the caller
doesn't actually care. Just use signed types as well.

Fixes: 27df89689e ("locking/spinlocks: Remove an instruction from spin and write locks")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2020-10-19 09:09:21 +02:00
Родитель 6f6573a404
Коммит f44ca0871b
2 изменённых файлов: 6 добавлений и 6 удалений
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8
include/asm-generic/qrwlock.h
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@ -37,7 +37,7 @@ extern void queued_write_lock_slowpath(struct qrwlock *lock);
*/ */
static inline int queued_read_trylock(struct qrwlock *lock) static inline int queued_read_trylock(struct qrwlock *lock)
{ {
u32 cnts; int cnts;
cnts = atomic_read(&lock->cnts); cnts = atomic_read(&lock->cnts);
if (likely(!(cnts & _QW_WMASK))) { if (likely(!(cnts & _QW_WMASK))) {
@ -56,7 +56,7 @@ static inline int queued_read_trylock(struct qrwlock *lock)
*/ */
static inline int queued_write_trylock(struct qrwlock *lock) static inline int queued_write_trylock(struct qrwlock *lock)
{ {
u32 cnts; int cnts;
cnts = atomic_read(&lock->cnts); cnts = atomic_read(&lock->cnts);
if (unlikely(cnts)) if (unlikely(cnts))
@ -71,7 +71,7 @@ static inline int queued_write_trylock(struct qrwlock *lock)
*/ */
static inline void queued_read_lock(struct qrwlock *lock) static inline void queued_read_lock(struct qrwlock *lock)
{ {
u32 cnts; int cnts;
cnts = atomic_add_return_acquire(_QR_BIAS, &lock->cnts); cnts = atomic_add_return_acquire(_QR_BIAS, &lock->cnts);
if (likely(!(cnts & _QW_WMASK))) if (likely(!(cnts & _QW_WMASK)))
@ -87,7 +87,7 @@ static inline void queued_read_lock(struct qrwlock *lock)
*/ */
static inline void queued_write_lock(struct qrwlock *lock) static inline void queued_write_lock(struct qrwlock *lock)
{ {
u32 cnts = 0; int cnts = 0;
/* Optimize for the unfair lock case where the fair flag is 0. */ /* Optimize for the unfair lock case where the fair flag is 0. */
if (likely(atomic_try_cmpxchg_acquire(&lock->cnts, &cnts, _QW_LOCKED))) if (likely(atomic_try_cmpxchg_acquire(&lock->cnts, &cnts, _QW_LOCKED)))
return; return;

4
include/asm-generic/qspinlock.h
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@ -60,7 +60,7 @@ static __always_inline int queued_spin_is_contended(struct qspinlock *lock)
*/ */
static __always_inline int queued_spin_trylock(struct qspinlock *lock) static __always_inline int queued_spin_trylock(struct qspinlock *lock)
{ {
u32 val = atomic_read(&lock->val); int val = atomic_read(&lock->val);
if (unlikely(val)) if (unlikely(val))
return 0; return 0;
@ -77,7 +77,7 @@ extern void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val);
*/ */
static __always_inline void queued_spin_lock(struct qspinlock *lock) static __always_inline void queued_spin_lock(struct qspinlock *lock)
{ {
u32 val = 0; int val = 0;
if (likely(atomic_try_cmpxchg_acquire(&lock->val, &val, _Q_LOCKED_VAL))) if (likely(atomic_try_cmpxchg_acquire(&lock->val, &val, _Q_LOCKED_VAL)))
return; return;