spi: DUAL and QUAD support
fix the previous patch some mistake below: 1. DT in slave node, use "spi-tx-nbits = <1/2/4>" in place of using "spi-tx-dual, spi-tx-quad" directly, same to rx. So correct the previous way to get the property in @of_register_spi_devices(). 2. Change the value of transfer bit macro(SPI_NBITS_SINGLE, SPI_NBITS_DUAL SPI_NBITS_QUAD) to 0x01, 0x02 and 0x04 to match the actual wires. 3. Add the following check (1)keep the tx_nbits and rx_nbits in spi_transfer is not beyond the single, dual and quad. (2)keep tx_nbits and rx_nbits are contained by @spi_device->mode example: if @spi_device->mode = DUAL, then tx/rx_nbits can not be set to QUAD(SPI_NBITS_QUAD) (3)if "@spi_device->mode & SPI_3WIRE", then tx/rx_nbits should be in single(SPI_NBITS_SINGLE) Signed-off-by: wangyuhang <wangyuhang2014@gmail.com> Signed-off-by: Mark Brown <broonie@linaro.org>
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Коммит
f477b7fb13
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@ -869,6 +869,51 @@ static void of_register_spi_devices(struct spi_master *master)
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if (of_find_property(nc, "spi-3wire", NULL))
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spi->mode |= SPI_3WIRE;
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/* Device DUAL/QUAD mode */
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prop = of_get_property(nc, "spi-tx-nbits", &len);
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if (!prop || len < sizeof(*prop)) {
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dev_err(&master->dev, "%s has no 'spi-tx-nbits' property\n",
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nc->full_name);
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spi_dev_put(spi);
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continue;
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}
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switch (be32_to_cpup(prop)) {
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case SPI_NBITS_SINGLE:
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break;
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case SPI_NBITS_DUAL:
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spi->mode |= SPI_TX_DUAL;
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break;
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case SPI_NBITS_QUAD:
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spi->mode |= SPI_TX_QUAD;
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break;
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default:
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dev_err(&master->dev, "spi-tx-nbits value is not supported\n");
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spi_dev_put(spi);
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continue;
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}
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prop = of_get_property(nc, "spi-rx-nbits", &len);
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if (!prop || len < sizeof(*prop)) {
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dev_err(&master->dev, "%s has no 'spi-rx-nbits' property\n",
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nc->full_name);
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spi_dev_put(spi);
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continue;
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}
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switch (be32_to_cpup(prop)) {
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case SPI_NBITS_SINGLE:
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break;
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case SPI_NBITS_DUAL:
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spi->mode |= SPI_RX_DUAL;
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break;
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case SPI_NBITS_QUAD:
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spi->mode |= SPI_RX_QUAD;
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break;
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default:
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dev_err(&master->dev, "spi-rx-nbits value is not supported\n");
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spi_dev_put(spi);
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continue;
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}
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/* Device speed */
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prop = of_get_property(nc, "spi-max-frequency", &len);
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if (!prop || len < sizeof(*prop)) {
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@ -1316,6 +1361,19 @@ int spi_setup(struct spi_device *spi)
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unsigned bad_bits;
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int status = 0;
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/* check mode to prevent that DUAL and QUAD set at the same time
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*/
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if (((spi->mode & SPI_TX_DUAL) && (spi->mode & SPI_TX_QUAD)) ||
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((spi->mode & SPI_RX_DUAL) && (spi->mode & SPI_RX_QUAD))) {
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dev_err(&spi->dev,
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"setup: can not select dual and quad at the same time\n");
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return -EINVAL;
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}
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/* if it is SPI_3WIRE mode, DUAL and QUAD should be forbidden
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*/
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if ((spi->mode & SPI_3WIRE) && (spi->mode &
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(SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)))
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return -EINVAL;
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/* help drivers fail *cleanly* when they need options
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* that aren't supported with their current master
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*/
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@ -1378,6 +1436,8 @@ static int __spi_async(struct spi_device *spi, struct spi_message *message)
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/**
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* Set transfer bits_per_word and max speed as spi device default if
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* it is not set for this transfer.
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* Set transfer tx_nbits and rx_nbits as single transfer default
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* (SPI_NBITS_SINGLE) if it is not set for this transfer.
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*/
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list_for_each_entry(xfer, &message->transfers, transfer_list) {
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if (!xfer->bits_per_word)
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@ -1403,6 +1463,42 @@ static int __spi_async(struct spi_device *spi, struct spi_message *message)
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return -EINVAL;
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if (xfer->speed_hz && master->max_speed_hz &&
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xfer->speed_hz > master->max_speed_hz)
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if (xfer->tx_buf && !xfer->tx_nbits)
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xfer->tx_nbits = SPI_NBITS_SINGLE;
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if (xfer->rx_buf && !xfer->rx_nbits)
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xfer->rx_nbits = SPI_NBITS_SINGLE;
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/* check transfer tx/rx_nbits:
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* 1. keep the value is not out of single, dual and quad
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* 2. keep tx/rx_nbits is contained by mode in spi_device
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* 3. if SPI_3WIRE, tx/rx_nbits should be in single
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*/
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if (xfer->tx_nbits != SPI_NBITS_SINGLE &&
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xfer->tx_nbits != SPI_NBITS_DUAL &&
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xfer->tx_nbits != SPI_NBITS_QUAD)
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return -EINVAL;
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if ((xfer->tx_nbits == SPI_NBITS_DUAL) &&
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!(spi->mode & (SPI_TX_DUAL | SPI_TX_QUAD)))
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return -EINVAL;
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if ((xfer->tx_nbits == SPI_NBITS_QUAD) &&
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!(spi->mode & SPI_TX_QUAD))
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return -EINVAL;
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if ((spi->mode & SPI_3WIRE) &&
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(xfer->tx_nbits != SPI_NBITS_SINGLE))
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return -EINVAL;
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/* check transfer rx_nbits */
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if (xfer->rx_nbits != SPI_NBITS_SINGLE &&
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xfer->rx_nbits != SPI_NBITS_DUAL &&
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xfer->rx_nbits != SPI_NBITS_QUAD)
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return -EINVAL;
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if ((xfer->rx_nbits == SPI_NBITS_DUAL) &&
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!(spi->mode & (SPI_RX_DUAL | SPI_RX_QUAD)))
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return -EINVAL;
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if ((xfer->rx_nbits == SPI_NBITS_QUAD) &&
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!(spi->mode & SPI_RX_QUAD))
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return -EINVAL;
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if ((spi->mode & SPI_3WIRE) &&
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(xfer->rx_nbits != SPI_NBITS_SINGLE))
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return -EINVAL;
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}
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@ -74,7 +74,7 @@ struct spi_device {
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struct spi_master *master;
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u32 max_speed_hz;
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u8 chip_select;
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u8 mode;
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u16 mode;
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#define SPI_CPHA 0x01 /* clock phase */
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#define SPI_CPOL 0x02 /* clock polarity */
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#define SPI_MODE_0 (0|0) /* (original MicroWire) */
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@ -87,6 +87,10 @@ struct spi_device {
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#define SPI_LOOP 0x20 /* loopback mode */
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#define SPI_NO_CS 0x40 /* 1 dev/bus, no chipselect */
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#define SPI_READY 0x80 /* slave pulls low to pause */
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#define SPI_TX_DUAL 0x100 /* transmit with 2 wires */
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#define SPI_TX_QUAD 0x200 /* transmit with 4 wires */
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#define SPI_RX_DUAL 0x400 /* receive with 2 wires */
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#define SPI_RX_QUAD 0x800 /* receive with 4 wires */
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u8 bits_per_word;
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int irq;
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void *controller_state;
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@ -454,6 +458,10 @@ extern struct spi_master *spi_busnum_to_master(u16 busnum);
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* @rx_buf: data to be read (dma-safe memory), or NULL
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* @tx_dma: DMA address of tx_buf, if @spi_message.is_dma_mapped
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* @rx_dma: DMA address of rx_buf, if @spi_message.is_dma_mapped
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* @tx_nbits: number of bits used for writting. If 0 the default
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* (SPI_NBITS_SINGLE) is used.
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* @rx_nbits: number of bits used for reading. If 0 the default
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* (SPI_NBITS_SINGLE) is used.
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* @len: size of rx and tx buffers (in bytes)
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* @speed_hz: Select a speed other than the device default for this
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* transfer. If 0 the default (from @spi_device) is used.
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@ -508,6 +516,11 @@ extern struct spi_master *spi_busnum_to_master(u16 busnum);
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* by the results of previous messages and where the whole transaction
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* ends when the chipselect goes intactive.
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*
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* When SPI can transfer in 1x,2x or 4x. It can get this tranfer information
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* from device through @tx_nbits and @rx_nbits. In Bi-direction, these
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* two should both be set. User can set transfer mode with SPI_NBITS_SINGLE(1x)
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* SPI_NBITS_DUAL(2x) and SPI_NBITS_QUAD(4x) to support these three transfer.
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*
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* The code that submits an spi_message (and its spi_transfers)
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* to the lower layers is responsible for managing its memory.
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* Zero-initialize every field you don't set up explicitly, to
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@ -528,6 +541,11 @@ struct spi_transfer {
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dma_addr_t rx_dma;
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unsigned cs_change:1;
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u8 tx_nbits;
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u8 rx_nbits;
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#define SPI_NBITS_SINGLE 0x01 /* 1bit transfer */
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#define SPI_NBITS_DUAL 0x02 /* 2bits transfer */
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#define SPI_NBITS_QUAD 0x04 /* 4bits transfer */
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u8 bits_per_word;
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u16 delay_usecs;
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u32 speed_hz;
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@ -875,7 +893,7 @@ struct spi_board_info {
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/* mode becomes spi_device.mode, and is essential for chips
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* where the default of SPI_CS_HIGH = 0 is wrong.
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*/
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u8 mode;
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u16 mode;
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/* ... may need additional spi_device chip config data here.
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* avoid stuff protocol drivers can set; but include stuff
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