bnx2x: prevent false parity error in MSI-X memory of HC block
Signed-off-by: Dmitry Kravkov <dmitry@broadcom.com> Signed-off-by: Vladislav Zolotarov <vladz@broadcom.com> Signed-off-by: Eilon Greenstein <eilong@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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a0fd065cd5
Коммит
f4a66897e7
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@ -5457,7 +5457,8 @@ static int bnx2x_init_hw_func(struct bnx2x *bp)
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struct bnx2x_ilt *ilt = BP_ILT(bp);
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struct bnx2x_ilt *ilt = BP_ILT(bp);
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u16 cdu_ilt_start;
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u16 cdu_ilt_start;
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u32 addr, val;
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u32 addr, val;
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int i;
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u32 main_mem_base, main_mem_size, main_mem_prty_clr;
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int i, main_mem_width;
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DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
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DP(BNX2X_MSG_MCP, "starting func init func %d\n", func);
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@ -5706,6 +5707,31 @@ static int bnx2x_init_hw_func(struct bnx2x *bp)
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bnx2x_init_block(bp, MCP_BLOCK, FUNC0_STAGE + func);
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bnx2x_init_block(bp, MCP_BLOCK, FUNC0_STAGE + func);
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bnx2x_init_block(bp, DMAE_BLOCK, FUNC0_STAGE + func);
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bnx2x_init_block(bp, DMAE_BLOCK, FUNC0_STAGE + func);
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if (CHIP_IS_E1x(bp)) {
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main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/
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main_mem_base = HC_REG_MAIN_MEMORY +
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BP_PORT(bp) * (main_mem_size * 4);
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main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR;
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main_mem_width = 8;
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val = REG_RD(bp, main_mem_prty_clr);
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if (val)
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DP(BNX2X_MSG_MCP, "Hmmm... Parity errors in HC "
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"block during "
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"function init (0x%x)!\n", val);
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/* Clear "false" parity errors in MSI-X table */
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for (i = main_mem_base;
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i < main_mem_base + main_mem_size * 4;
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i += main_mem_width) {
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bnx2x_read_dmae(bp, i, main_mem_width / 4);
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bnx2x_write_dmae(bp, bnx2x_sp_mapping(bp, wb_data),
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i, main_mem_width / 4);
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}
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/* Clear HC parity attention */
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REG_RD(bp, main_mem_prty_clr);
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}
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bnx2x_phy_probe(&bp->link_params);
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bnx2x_phy_probe(&bp->link_params);
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return 0;
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return 0;
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@ -800,9 +800,13 @@
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#define HC_REG_HC_PRTY_MASK 0x1080a0
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#define HC_REG_HC_PRTY_MASK 0x1080a0
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/* [R 3] Parity register #0 read */
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/* [R 3] Parity register #0 read */
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#define HC_REG_HC_PRTY_STS 0x108094
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#define HC_REG_HC_PRTY_STS 0x108094
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#define HC_REG_INT_MASK 0x108108
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/* [RC 3] Parity register #0 read clear */
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#define HC_REG_HC_PRTY_STS_CLR 0x108098
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#define HC_REG_INT_MASK 0x108108
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#define HC_REG_LEADING_EDGE_0 0x108040
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#define HC_REG_LEADING_EDGE_0 0x108040
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#define HC_REG_LEADING_EDGE_1 0x108048
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#define HC_REG_LEADING_EDGE_1 0x108048
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#define HC_REG_MAIN_MEMORY 0x108800
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#define HC_REG_MAIN_MEMORY_SIZE 152
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#define HC_REG_P0_PROD_CONS 0x108200
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#define HC_REG_P0_PROD_CONS 0x108200
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#define HC_REG_P1_PROD_CONS 0x108400
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#define HC_REG_P1_PROD_CONS 0x108400
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#define HC_REG_PBA_COMMAND 0x108140
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#define HC_REG_PBA_COMMAND 0x108140
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