Merge branch 'bnx2x'
Yuval Mintz says: ==================== This patch contains various bug fixes, half of which are SR-IOV related (some fixing issues in the recently added VF RSS support), while the other fix a wide assortments of issues in the driver. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Коммит
f516e2c9ec
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@ -2481,8 +2481,7 @@ load_error_cnic2:
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load_error_cnic1:
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load_error_cnic1:
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bnx2x_napi_disable_cnic(bp);
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bnx2x_napi_disable_cnic(bp);
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/* Update the number of queues without the cnic queues */
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/* Update the number of queues without the cnic queues */
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rc = bnx2x_set_real_num_queues(bp, 0);
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if (bnx2x_set_real_num_queues(bp, 0))
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if (rc)
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BNX2X_ERR("Unable to set real_num_queues not including cnic\n");
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BNX2X_ERR("Unable to set real_num_queues not including cnic\n");
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load_error_cnic0:
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load_error_cnic0:
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BNX2X_ERR("CNIC-related load failed\n");
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BNX2X_ERR("CNIC-related load failed\n");
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@ -4703,6 +4703,14 @@ bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
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attn.sig[3] = REG_RD(bp,
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attn.sig[3] = REG_RD(bp,
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MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
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MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
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port*4);
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port*4);
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/* Since MCP attentions can't be disabled inside the block, we need to
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* read AEU registers to see whether they're currently disabled
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*/
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attn.sig[3] &= ((REG_RD(bp,
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!port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
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: MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
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MISC_AEU_ENABLE_MCP_PRTY_BITS) |
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~MISC_AEU_ENABLE_MCP_PRTY_BITS);
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if (!CHIP_IS_E1x(bp))
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if (!CHIP_IS_E1x(bp))
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attn.sig[4] = REG_RD(bp,
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attn.sig[4] = REG_RD(bp,
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@ -5447,26 +5455,24 @@ static void bnx2x_timer(unsigned long data)
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if (IS_PF(bp) &&
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if (IS_PF(bp) &&
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!BP_NOMCP(bp)) {
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!BP_NOMCP(bp)) {
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int mb_idx = BP_FW_MB_IDX(bp);
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int mb_idx = BP_FW_MB_IDX(bp);
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u32 drv_pulse;
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u16 drv_pulse;
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u32 mcp_pulse;
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u16 mcp_pulse;
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++bp->fw_drv_pulse_wr_seq;
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++bp->fw_drv_pulse_wr_seq;
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bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
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bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
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/* TBD - add SYSTEM_TIME */
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drv_pulse = bp->fw_drv_pulse_wr_seq;
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drv_pulse = bp->fw_drv_pulse_wr_seq;
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bnx2x_drv_pulse(bp);
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bnx2x_drv_pulse(bp);
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mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
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mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
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MCP_PULSE_SEQ_MASK);
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MCP_PULSE_SEQ_MASK);
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/* The delta between driver pulse and mcp response
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/* The delta between driver pulse and mcp response
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* should be 1 (before mcp response) or 0 (after mcp response)
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* should not get too big. If the MFW is more than 5 pulses
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* behind, we should worry about it enough to generate an error
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* log.
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*/
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*/
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if ((drv_pulse != mcp_pulse) &&
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if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
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(drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) {
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BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
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/* someone lost a heartbeat... */
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BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
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drv_pulse, mcp_pulse);
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drv_pulse, mcp_pulse);
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}
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}
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}
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if (bp->state == BNX2X_STATE_OPEN)
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if (bp->state == BNX2X_STATE_OPEN)
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@ -1819,7 +1819,7 @@ bnx2x_get_vf_igu_cam_info(struct bnx2x *bp)
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fid = GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID);
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fid = GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID);
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if (fid & IGU_FID_ENCODE_IS_PF)
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if (fid & IGU_FID_ENCODE_IS_PF)
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current_pf = fid & IGU_FID_PF_NUM_MASK;
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current_pf = fid & IGU_FID_PF_NUM_MASK;
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else if (current_pf == BP_ABS_FUNC(bp))
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else if (current_pf == BP_FUNC(bp))
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bnx2x_vf_set_igu_info(bp, sb_id,
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bnx2x_vf_set_igu_info(bp, sb_id,
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(fid & IGU_FID_VF_NUM_MASK));
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(fid & IGU_FID_VF_NUM_MASK));
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DP(BNX2X_MSG_IOV, "%s[%d], igu_sb_id=%d, msix=%d\n",
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DP(BNX2X_MSG_IOV, "%s[%d], igu_sb_id=%d, msix=%d\n",
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@ -3180,6 +3180,7 @@ int bnx2x_enable_sriov(struct bnx2x *bp)
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/* set local queue arrays */
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/* set local queue arrays */
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vf->vfqs = &bp->vfdb->vfqs[qcount];
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vf->vfqs = &bp->vfdb->vfqs[qcount];
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qcount += vf_sb_count(vf);
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qcount += vf_sb_count(vf);
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bnx2x_iov_static_resc(bp, vf);
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}
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}
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/* prepare msix vectors in VF configuration space */
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/* prepare msix vectors in VF configuration space */
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@ -3187,6 +3188,8 @@ int bnx2x_enable_sriov(struct bnx2x *bp)
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bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf_idx));
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bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf_idx));
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REG_WR(bp, PCICFG_OFFSET + GRC_CONFIG_REG_VF_MSIX_CONTROL,
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REG_WR(bp, PCICFG_OFFSET + GRC_CONFIG_REG_VF_MSIX_CONTROL,
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num_vf_queues);
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num_vf_queues);
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DP(BNX2X_MSG_IOV, "set msix vec num in VF %d cfg space to %d\n",
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vf_idx, num_vf_queues);
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}
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}
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bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
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bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));
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@ -1765,28 +1765,28 @@ static void bnx2x_vf_mbx_request(struct bnx2x *bp, struct bnx2x_virtf *vf,
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switch (mbx->first_tlv.tl.type) {
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switch (mbx->first_tlv.tl.type) {
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case CHANNEL_TLV_ACQUIRE:
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case CHANNEL_TLV_ACQUIRE:
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bnx2x_vf_mbx_acquire(bp, vf, mbx);
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bnx2x_vf_mbx_acquire(bp, vf, mbx);
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break;
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return;
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case CHANNEL_TLV_INIT:
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case CHANNEL_TLV_INIT:
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bnx2x_vf_mbx_init_vf(bp, vf, mbx);
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bnx2x_vf_mbx_init_vf(bp, vf, mbx);
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break;
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return;
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case CHANNEL_TLV_SETUP_Q:
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case CHANNEL_TLV_SETUP_Q:
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bnx2x_vf_mbx_setup_q(bp, vf, mbx);
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bnx2x_vf_mbx_setup_q(bp, vf, mbx);
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break;
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return;
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case CHANNEL_TLV_SET_Q_FILTERS:
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case CHANNEL_TLV_SET_Q_FILTERS:
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bnx2x_vf_mbx_set_q_filters(bp, vf, mbx);
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bnx2x_vf_mbx_set_q_filters(bp, vf, mbx);
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break;
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return;
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case CHANNEL_TLV_TEARDOWN_Q:
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case CHANNEL_TLV_TEARDOWN_Q:
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bnx2x_vf_mbx_teardown_q(bp, vf, mbx);
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bnx2x_vf_mbx_teardown_q(bp, vf, mbx);
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break;
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return;
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case CHANNEL_TLV_CLOSE:
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case CHANNEL_TLV_CLOSE:
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bnx2x_vf_mbx_close_vf(bp, vf, mbx);
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bnx2x_vf_mbx_close_vf(bp, vf, mbx);
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break;
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return;
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case CHANNEL_TLV_RELEASE:
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case CHANNEL_TLV_RELEASE:
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bnx2x_vf_mbx_release_vf(bp, vf, mbx);
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bnx2x_vf_mbx_release_vf(bp, vf, mbx);
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break;
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return;
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case CHANNEL_TLV_UPDATE_RSS:
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case CHANNEL_TLV_UPDATE_RSS:
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bnx2x_vf_mbx_update_rss(bp, vf, mbx);
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bnx2x_vf_mbx_update_rss(bp, vf, mbx);
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break;
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return;
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}
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}
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} else {
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} else {
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@ -1802,26 +1802,24 @@ static void bnx2x_vf_mbx_request(struct bnx2x *bp, struct bnx2x_virtf *vf,
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for (i = 0; i < 20; i++)
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for (i = 0; i < 20; i++)
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DP_CONT(BNX2X_MSG_IOV, "%x ",
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DP_CONT(BNX2X_MSG_IOV, "%x ",
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mbx->msg->req.tlv_buf_size.tlv_buffer[i]);
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mbx->msg->req.tlv_buf_size.tlv_buffer[i]);
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}
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/* test whether we can respond to the VF (do we have an address
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/* can we respond to VF (do we have an address for it?) */
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* for it?)
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if (vf->state == VF_ACQUIRED || vf->state == VF_ENABLED) {
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/* mbx_resp uses the op_rc of the VF */
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vf->op_rc = PFVF_STATUS_NOT_SUPPORTED;
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/* notify the VF that we do not support this request */
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bnx2x_vf_mbx_resp(bp, vf);
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} else {
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/* can't send a response since this VF is unknown to us
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* just ack the FW to release the mailbox and unlock
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* the channel.
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*/
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*/
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if (vf->state == VF_ACQUIRED || vf->state == VF_ENABLED) {
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storm_memset_vf_mbx_ack(bp, vf->abs_vfid);
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/* mbx_resp uses the op_rc of the VF */
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/* Firmware ack should be written before unlocking channel */
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vf->op_rc = PFVF_STATUS_NOT_SUPPORTED;
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mmiowb();
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bnx2x_unlock_vf_pf_channel(bp, vf, mbx->first_tlv.tl.type);
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/* notify the VF that we do not support this request */
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bnx2x_vf_mbx_resp(bp, vf);
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} else {
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/* can't send a response since this VF is unknown to us
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* just ack the FW to release the mailbox and unlock
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* the channel.
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*/
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storm_memset_vf_mbx_ack(bp, vf->abs_vfid);
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mmiowb();
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bnx2x_unlock_vf_pf_channel(bp, vf,
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mbx->first_tlv.tl.type);
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}
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}
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}
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}
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}
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