Yuval Mintz says:

====================
This patch contains various bug fixes, half of which are SR-IOV related
(some fixing issues in the recently added VF RSS support), while the other fix
a wide assortments of issues in the driver.
====================

Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
David S. Miller 2013-09-23 16:17:16 -04:00
Родитель 343f7dc430 cbbf77de64
Коммит f516e2c9ec
4 изменённых файлов: 44 добавлений и 38 удалений

Просмотреть файл

@ -2481,8 +2481,7 @@ load_error_cnic2:
load_error_cnic1: load_error_cnic1:
bnx2x_napi_disable_cnic(bp); bnx2x_napi_disable_cnic(bp);
/* Update the number of queues without the cnic queues */ /* Update the number of queues without the cnic queues */
rc = bnx2x_set_real_num_queues(bp, 0); if (bnx2x_set_real_num_queues(bp, 0))
if (rc)
BNX2X_ERR("Unable to set real_num_queues not including cnic\n"); BNX2X_ERR("Unable to set real_num_queues not including cnic\n");
load_error_cnic0: load_error_cnic0:
BNX2X_ERR("CNIC-related load failed\n"); BNX2X_ERR("CNIC-related load failed\n");

Просмотреть файл

@ -4703,6 +4703,14 @@ bool bnx2x_chk_parity_attn(struct bnx2x *bp, bool *global, bool print)
attn.sig[3] = REG_RD(bp, attn.sig[3] = REG_RD(bp,
MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 +
port*4); port*4);
/* Since MCP attentions can't be disabled inside the block, we need to
* read AEU registers to see whether they're currently disabled
*/
attn.sig[3] &= ((REG_RD(bp,
!port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0
: MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0) &
MISC_AEU_ENABLE_MCP_PRTY_BITS) |
~MISC_AEU_ENABLE_MCP_PRTY_BITS);
if (!CHIP_IS_E1x(bp)) if (!CHIP_IS_E1x(bp))
attn.sig[4] = REG_RD(bp, attn.sig[4] = REG_RD(bp,
@ -5447,26 +5455,24 @@ static void bnx2x_timer(unsigned long data)
if (IS_PF(bp) && if (IS_PF(bp) &&
!BP_NOMCP(bp)) { !BP_NOMCP(bp)) {
int mb_idx = BP_FW_MB_IDX(bp); int mb_idx = BP_FW_MB_IDX(bp);
u32 drv_pulse; u16 drv_pulse;
u32 mcp_pulse; u16 mcp_pulse;
++bp->fw_drv_pulse_wr_seq; ++bp->fw_drv_pulse_wr_seq;
bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; bp->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK;
/* TBD - add SYSTEM_TIME */
drv_pulse = bp->fw_drv_pulse_wr_seq; drv_pulse = bp->fw_drv_pulse_wr_seq;
bnx2x_drv_pulse(bp); bnx2x_drv_pulse(bp);
mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) & mcp_pulse = (SHMEM_RD(bp, func_mb[mb_idx].mcp_pulse_mb) &
MCP_PULSE_SEQ_MASK); MCP_PULSE_SEQ_MASK);
/* The delta between driver pulse and mcp response /* The delta between driver pulse and mcp response
* should be 1 (before mcp response) or 0 (after mcp response) * should not get too big. If the MFW is more than 5 pulses
* behind, we should worry about it enough to generate an error
* log.
*/ */
if ((drv_pulse != mcp_pulse) && if (((drv_pulse - mcp_pulse) & MCP_PULSE_SEQ_MASK) > 5)
(drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) { BNX2X_ERR("MFW seems hanged: drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
/* someone lost a heartbeat... */
BNX2X_ERR("drv_pulse (0x%x) != mcp_pulse (0x%x)\n",
drv_pulse, mcp_pulse); drv_pulse, mcp_pulse);
}
} }
if (bp->state == BNX2X_STATE_OPEN) if (bp->state == BNX2X_STATE_OPEN)

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@ -1819,7 +1819,7 @@ bnx2x_get_vf_igu_cam_info(struct bnx2x *bp)
fid = GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID); fid = GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID);
if (fid & IGU_FID_ENCODE_IS_PF) if (fid & IGU_FID_ENCODE_IS_PF)
current_pf = fid & IGU_FID_PF_NUM_MASK; current_pf = fid & IGU_FID_PF_NUM_MASK;
else if (current_pf == BP_ABS_FUNC(bp)) else if (current_pf == BP_FUNC(bp))
bnx2x_vf_set_igu_info(bp, sb_id, bnx2x_vf_set_igu_info(bp, sb_id,
(fid & IGU_FID_VF_NUM_MASK)); (fid & IGU_FID_VF_NUM_MASK));
DP(BNX2X_MSG_IOV, "%s[%d], igu_sb_id=%d, msix=%d\n", DP(BNX2X_MSG_IOV, "%s[%d], igu_sb_id=%d, msix=%d\n",
@ -3180,6 +3180,7 @@ int bnx2x_enable_sriov(struct bnx2x *bp)
/* set local queue arrays */ /* set local queue arrays */
vf->vfqs = &bp->vfdb->vfqs[qcount]; vf->vfqs = &bp->vfdb->vfqs[qcount];
qcount += vf_sb_count(vf); qcount += vf_sb_count(vf);
bnx2x_iov_static_resc(bp, vf);
} }
/* prepare msix vectors in VF configuration space */ /* prepare msix vectors in VF configuration space */
@ -3187,6 +3188,8 @@ int bnx2x_enable_sriov(struct bnx2x *bp)
bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf_idx)); bnx2x_pretend_func(bp, HW_VF_HANDLE(bp, vf_idx));
REG_WR(bp, PCICFG_OFFSET + GRC_CONFIG_REG_VF_MSIX_CONTROL, REG_WR(bp, PCICFG_OFFSET + GRC_CONFIG_REG_VF_MSIX_CONTROL,
num_vf_queues); num_vf_queues);
DP(BNX2X_MSG_IOV, "set msix vec num in VF %d cfg space to %d\n",
vf_idx, num_vf_queues);
} }
bnx2x_pretend_func(bp, BP_ABS_FUNC(bp)); bnx2x_pretend_func(bp, BP_ABS_FUNC(bp));

Просмотреть файл

@ -1765,28 +1765,28 @@ static void bnx2x_vf_mbx_request(struct bnx2x *bp, struct bnx2x_virtf *vf,
switch (mbx->first_tlv.tl.type) { switch (mbx->first_tlv.tl.type) {
case CHANNEL_TLV_ACQUIRE: case CHANNEL_TLV_ACQUIRE:
bnx2x_vf_mbx_acquire(bp, vf, mbx); bnx2x_vf_mbx_acquire(bp, vf, mbx);
break; return;
case CHANNEL_TLV_INIT: case CHANNEL_TLV_INIT:
bnx2x_vf_mbx_init_vf(bp, vf, mbx); bnx2x_vf_mbx_init_vf(bp, vf, mbx);
break; return;
case CHANNEL_TLV_SETUP_Q: case CHANNEL_TLV_SETUP_Q:
bnx2x_vf_mbx_setup_q(bp, vf, mbx); bnx2x_vf_mbx_setup_q(bp, vf, mbx);
break; return;
case CHANNEL_TLV_SET_Q_FILTERS: case CHANNEL_TLV_SET_Q_FILTERS:
bnx2x_vf_mbx_set_q_filters(bp, vf, mbx); bnx2x_vf_mbx_set_q_filters(bp, vf, mbx);
break; return;
case CHANNEL_TLV_TEARDOWN_Q: case CHANNEL_TLV_TEARDOWN_Q:
bnx2x_vf_mbx_teardown_q(bp, vf, mbx); bnx2x_vf_mbx_teardown_q(bp, vf, mbx);
break; return;
case CHANNEL_TLV_CLOSE: case CHANNEL_TLV_CLOSE:
bnx2x_vf_mbx_close_vf(bp, vf, mbx); bnx2x_vf_mbx_close_vf(bp, vf, mbx);
break; return;
case CHANNEL_TLV_RELEASE: case CHANNEL_TLV_RELEASE:
bnx2x_vf_mbx_release_vf(bp, vf, mbx); bnx2x_vf_mbx_release_vf(bp, vf, mbx);
break; return;
case CHANNEL_TLV_UPDATE_RSS: case CHANNEL_TLV_UPDATE_RSS:
bnx2x_vf_mbx_update_rss(bp, vf, mbx); bnx2x_vf_mbx_update_rss(bp, vf, mbx);
break; return;
} }
} else { } else {
@ -1802,26 +1802,24 @@ static void bnx2x_vf_mbx_request(struct bnx2x *bp, struct bnx2x_virtf *vf,
for (i = 0; i < 20; i++) for (i = 0; i < 20; i++)
DP_CONT(BNX2X_MSG_IOV, "%x ", DP_CONT(BNX2X_MSG_IOV, "%x ",
mbx->msg->req.tlv_buf_size.tlv_buffer[i]); mbx->msg->req.tlv_buf_size.tlv_buffer[i]);
}
/* test whether we can respond to the VF (do we have an address /* can we respond to VF (do we have an address for it?) */
* for it?) if (vf->state == VF_ACQUIRED || vf->state == VF_ENABLED) {
/* mbx_resp uses the op_rc of the VF */
vf->op_rc = PFVF_STATUS_NOT_SUPPORTED;
/* notify the VF that we do not support this request */
bnx2x_vf_mbx_resp(bp, vf);
} else {
/* can't send a response since this VF is unknown to us
* just ack the FW to release the mailbox and unlock
* the channel.
*/ */
if (vf->state == VF_ACQUIRED || vf->state == VF_ENABLED) { storm_memset_vf_mbx_ack(bp, vf->abs_vfid);
/* mbx_resp uses the op_rc of the VF */ /* Firmware ack should be written before unlocking channel */
vf->op_rc = PFVF_STATUS_NOT_SUPPORTED; mmiowb();
bnx2x_unlock_vf_pf_channel(bp, vf, mbx->first_tlv.tl.type);
/* notify the VF that we do not support this request */
bnx2x_vf_mbx_resp(bp, vf);
} else {
/* can't send a response since this VF is unknown to us
* just ack the FW to release the mailbox and unlock
* the channel.
*/
storm_memset_vf_mbx_ack(bp, vf->abs_vfid);
mmiowb();
bnx2x_unlock_vf_pf_channel(bp, vf,
mbx->first_tlv.tl.type);
}
} }
} }