drm/amd/display: Add symclk workaround during disable link output
[Why & How] This is originally a change (9c75891f
) in DCN32 because of the lack of interface to set TX while keeping symclk on. Adding this workaround to DCN314 will resolve the current issue. Fixes:9c75891fee
("drm/amd/display: rework recent update PHY state commit") Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Leo Chen <sancchen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Родитель
58d9b9a14b
Коммит
f57fa0f23d
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@ -423,3 +423,68 @@ void dcn314_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool
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PERF_TRACE();
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}
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static void apply_symclk_on_tx_off_wa(struct dc_link *link)
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{
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/* There are use cases where SYMCLK is referenced by OTG. For instance
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* for TMDS signal, OTG relies SYMCLK even if TX video output is off.
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* However current link interface will power off PHY when disabling link
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* output. This will turn off SYMCLK generated by PHY. The workaround is
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* to identify such case where SYMCLK is still in use by OTG when we
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* power off PHY. When this is detected, we will temporarily power PHY
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* back on and move PHY's SYMCLK state to SYMCLK_ON_TX_OFF by calling
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* program_pix_clk interface. When OTG is disabled, we will then power
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* off PHY by calling disable link output again.
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*
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* In future dcn generations, we plan to rework transmitter control
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* interface so that we could have an option to set SYMCLK ON TX OFF
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* state in one step without this workaround
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*/
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struct dc *dc = link->ctx->dc;
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struct pipe_ctx *pipe_ctx = NULL;
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uint8_t i;
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if (link->phy_state.symclk_ref_cnts.otg > 0) {
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for (i = 0; i < MAX_PIPES; i++) {
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pipe_ctx = &dc->current_state->res_ctx.pipe_ctx[i];
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if (pipe_ctx->stream && pipe_ctx->stream->link == link && pipe_ctx->top_pipe == NULL) {
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pipe_ctx->clock_source->funcs->program_pix_clk(
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pipe_ctx->clock_source,
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&pipe_ctx->stream_res.pix_clk_params,
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dc->link_srv->dp_get_encoding_format(
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&pipe_ctx->link_config.dp_link_settings),
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&pipe_ctx->pll_settings);
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link->phy_state.symclk_state = SYMCLK_ON_TX_OFF;
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break;
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}
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}
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}
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}
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void dcn314_disable_link_output(struct dc_link *link,
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const struct link_resource *link_res,
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enum signal_type signal)
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{
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struct dc *dc = link->ctx->dc;
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const struct link_hwss *link_hwss = get_link_hwss(link, link_res);
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struct dmcu *dmcu = dc->res_pool->dmcu;
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if (signal == SIGNAL_TYPE_EDP &&
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link->dc->hwss.edp_backlight_control)
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link->dc->hwss.edp_backlight_control(link, false);
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else if (dmcu != NULL && dmcu->funcs->lock_phy)
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dmcu->funcs->lock_phy(dmcu);
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link_hwss->disable_link_output(link, link_res, signal);
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link->phy_state.symclk_state = SYMCLK_OFF_TX_OFF;
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/*
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* Add the logic to extract BOTH power up and power down sequences
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* from enable/disable link output and only call edp panel control
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* in enable_link_dp and disable_link_dp once.
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*/
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if (dmcu != NULL && dmcu->funcs->lock_phy)
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dmcu->funcs->unlock_phy(dmcu);
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dc->link_srv->dp_trace_source_sequence(link, DPCD_SOURCE_SEQ_AFTER_DISABLE_LINK_PHY);
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apply_symclk_on_tx_off_wa(link);
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}
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@ -45,4 +45,6 @@ void dcn314_hubp_pg_control(struct dce_hwseq *hws, unsigned int hubp_inst, bool
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void dcn314_dpp_root_clock_control(struct dce_hwseq *hws, unsigned int dpp_inst, bool clock_on);
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void dcn314_disable_link_output(struct dc_link *link, const struct link_resource *link_res, enum signal_type signal);
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#endif /* __DC_HWSS_DCN314_H__ */
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@ -105,7 +105,7 @@ static const struct hw_sequencer_funcs dcn314_funcs = {
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.enable_lvds_link_output = dce110_enable_lvds_link_output,
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.enable_tmds_link_output = dce110_enable_tmds_link_output,
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.enable_dp_link_output = dce110_enable_dp_link_output,
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.disable_link_output = dce110_disable_link_output,
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.disable_link_output = dcn314_disable_link_output,
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.z10_restore = dcn31_z10_restore,
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.z10_save_init = dcn31_z10_save_init,
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.set_disp_pattern_generator = dcn30_set_disp_pattern_generator,
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