ARM OMAP2+ GPMC: always program GPMCFCLKDIVIDER
The WAITMONITORINGTIME is expressed as a number of GPMC_CLK clock cycles, even though the access is defined as asynchronous, and no GPMC_CLK clock is provided to the external device. Still, GPMCFCLKDIVIDER is used as a divider for the GPMC clock, so it must be programmed to define the correct WAITMONITORINGTIME delay. Signed-off-by: Robert ABEL <rabel@cit-ec.uni-bielefeld.de> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Roger Quadros <rogerq@ti.com>
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@ -508,7 +508,7 @@ static int set_gpmc_timing_reg(int cs, int reg, int st_bit, int end_bit,
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l = gpmc_cs_read_reg(cs, reg);
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#ifdef DEBUG
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printk(KERN_INFO
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pr_info(
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"GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n",
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cs, name, ticks, gpmc_get_fclk_period() * ticks / 1000,
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(l >> st_bit) & mask, time);
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@ -580,19 +580,14 @@ int gpmc_cs_set_timings(int cs, const struct gpmc_timings *t)
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if (gpmc_capability & GPMC_HAS_WR_ACCESS)
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GPMC_SET_ONE(GPMC_CS_CONFIG6, 24, 28, wr_access);
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/* caller is expected to have initialized CONFIG1 to cover
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* at least sync vs async
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*/
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l = gpmc_cs_read_reg(cs, GPMC_CS_CONFIG1);
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if (l & (GPMC_CONFIG1_READTYPE_SYNC | GPMC_CONFIG1_WRITETYPE_SYNC)) {
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#ifdef DEBUG
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printk(KERN_INFO "GPMC CS%d CLK period is %lu ns (div %d)\n",
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cs, (div * gpmc_get_fclk_period()) / 1000, div);
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pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n",
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cs, (div * gpmc_get_fclk_period()) / 1000, div);
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#endif
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l &= ~0x03;
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l |= (div - 1);
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gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
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}
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l &= ~0x03;
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l |= (div - 1);
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gpmc_cs_write_reg(cs, GPMC_CS_CONFIG1, l);
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gpmc_cs_bool_timings(cs, &t->bool_timings);
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gpmc_cs_show_timings(cs, "after gpmc_cs_set_timings");
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