ARM: cti: fix manipulation of debug lock registers
The LOCKSTATUS register for memory-mapped coresight devices indicates whether or not the device in question implements hardware locking. If not, locking is not present (i.e. LSR.SLI == 0) and LAR is write-ignore, so software doesn't actually need to check the status register at all. This patch removes the broken LSR checks. Cc: Ming Lei <ming.lei@canonical.com> Reported-by: Mike Williams <michael.williams@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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@ -146,15 +146,7 @@ static inline void cti_irq_ack(struct cti *cti)
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*/
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*/
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static inline void cti_unlock(struct cti *cti)
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static inline void cti_unlock(struct cti *cti)
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{
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{
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void __iomem *base = cti->base;
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__raw_writel(LOCKCODE, cti->base + LOCKACCESS);
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unsigned long val;
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val = __raw_readl(base + LOCKSTATUS);
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if (val & 1) {
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val = LOCKCODE;
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__raw_writel(val, base + LOCKACCESS);
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}
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}
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}
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/**
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/**
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@ -166,14 +158,6 @@ static inline void cti_unlock(struct cti *cti)
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*/
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*/
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static inline void cti_lock(struct cti *cti)
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static inline void cti_lock(struct cti *cti)
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{
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{
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void __iomem *base = cti->base;
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__raw_writel(~LOCKCODE, cti->base + LOCKACCESS);
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unsigned long val;
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val = __raw_readl(base + LOCKSTATUS);
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if (!(val & 1)) {
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val = ~LOCKCODE;
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__raw_writel(val, base + LOCKACCESS);
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}
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}
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}
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#endif
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#endif
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