CLK: TI: add support for gate clock
This patch adds support for TI specific gate clocks. These behave as basic gate-clock, but have different ops / hw-ops for controlling the actual gate, for example waiting until the clock is ready. Several sub-types are supported: - ti,gate-clock: basic gate clock with default ops/hwops - ti,clkdm-gate-clock: clockdomain level gate control - ti,dss-gate-clock: gate clock with DSS specific hardware handling - ti,am35xx-gate-clock: gate clock with AM35xx specific hardware handling - ti,hsdiv-gate-clock: gate clock with OMAP36xx hardware errata handling Signed-off-by: Tero Kristo <t-kristo@ti.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Mike Turquette <mturquette@linaro.org>
This commit is contained in:
Tero Kristo
Mike Turquette
Родитель
1f847c65fd
Коммит
f60b1ea5ea
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@ -0,0 +1,85 @@
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Binding for Texas Instruments gate clock.
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Binding status: Unstable - ABI compatibility may be broken in the future
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This binding uses the common clock binding[1]. This clock is
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quite much similar to the basic gate-clock [2], however,
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it supports a number of additional features. If no register
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is provided for this clock, the code assumes that a clockdomain
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will be controlled instead and the corresponding hw-ops for
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that is used.
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
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[2] Documentation/devicetree/bindings/clock/gate-clock.txt
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[3] Documentation/devicetree/bindings/clock/ti/clockdomain.txt
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Required properties:
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- compatible : shall be one of:
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"ti,gate-clock" - basic gate clock
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"ti,wait-gate-clock" - gate clock which waits until clock is active before
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returning from clk_enable()
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"ti,dss-gate-clock" - gate clock with DSS specific hardware handling
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"ti,am35xx-gate-clock" - gate clock with AM35xx specific hardware handling
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"ti,clkdm-gate-clock" - clockdomain gate clock, which derives its functional
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clock directly from a clockdomain, see [3] how
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to map clockdomains properly
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"ti,hsdiv-gate-clock" - gate clock with OMAP36xx specific hardware handling,
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required for a hardware errata
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- #clock-cells : from common clock binding; shall be set to 0
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- clocks : link to phandle of parent clock
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- reg : offset for register controlling adjustable gate, not needed for
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ti,clkdm-gate-clock type
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Optional properties:
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- ti,bit-shift : bit shift for programming the clock gate, invalid for
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ti,clkdm-gate-clock type
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- ti,set-bit-to-disable : inverts default gate programming. Setting the bit
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gates the clock and clearing the bit ungates the clock.
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Examples:
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mmchs2_fck: mmchs2_fck@48004a00 {
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#clock-cells = <0>;
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compatible = "ti,gate-clock";
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clocks = <&core_96m_fck>;
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reg = <0x48004a00 0x4>;
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ti,bit-shift = <25>;
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};
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uart4_fck_am35xx: uart4_fck_am35xx {
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#clock-cells = <0>;
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compatible = "ti,wait-gate-clock";
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clocks = <&core_48m_fck>;
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reg = <0x0a00>;
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ti,bit-shift = <23>;
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};
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dss1_alwon_fck_3430es2: dss1_alwon_fck_3430es2@48004e00 {
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#clock-cells = <0>;
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compatible = "ti,dss-gate-clock";
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clocks = <&dpll4_m4x2_ck>;
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reg = <0x48004e00 0x4>;
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ti,bit-shift = <0>;
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};
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emac_ick: emac_ick@4800259c {
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#clock-cells = <0>;
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compatible = "ti,am35xx-gate-clock";
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clocks = <&ipss_ick>;
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reg = <0x4800259c 0x4>;
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ti,bit-shift = <1>;
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};
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emu_src_ck: emu_src_ck {
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#clock-cells = <0>;
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compatible = "ti,clkdm-gate-clock";
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clocks = <&emu_src_mux_ck>;
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};
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dpll4_m2x2_ck: dpll4_m2x2_ck@48004d00 {
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#clock-cells = <0>;
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compatible = "ti,hsdiv-gate-clock";
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clocks = <&dpll4_m2x2_mul_ck>;
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ti,bit-shift = <0x1b>;
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reg = <0x48004d00 0x4>;
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ti,set-bit-to-disable;
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};
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@ -1,5 +1,5 @@
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ifneq ($(CONFIG_OF),)
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obj-y += clk.o autoidle.o
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clk-common = dpll.o composite.o divider.o \
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clk-common = dpll.o composite.o divider.o gate.o \
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fixed-factor.o
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endif
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@ -0,0 +1,249 @@
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/*
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* OMAP gate clock support
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*
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* Copyright (C) 2013 Texas Instruments, Inc.
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*
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* Tero Kristo <t-kristo@ti.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/clk-provider.h>
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#include <linux/slab.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/clk/ti.h>
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#define to_clk_divider(_hw) container_of(_hw, struct clk_divider, hw)
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#undef pr_fmt
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#define pr_fmt(fmt) "%s: " fmt, __func__
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static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk);
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static const struct clk_ops omap_gate_clkdm_clk_ops = {
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.init = &omap2_init_clk_clkdm,
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.enable = &omap2_clkops_enable_clkdm,
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.disable = &omap2_clkops_disable_clkdm,
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};
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static const struct clk_ops omap_gate_clk_ops = {
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.init = &omap2_init_clk_clkdm,
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.enable = &omap2_dflt_clk_enable,
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.disable = &omap2_dflt_clk_disable,
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.is_enabled = &omap2_dflt_clk_is_enabled,
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};
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static const struct clk_ops omap_gate_clk_hsdiv_restore_ops = {
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.init = &omap2_init_clk_clkdm,
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.enable = &omap36xx_gate_clk_enable_with_hsdiv_restore,
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.disable = &omap2_dflt_clk_disable,
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.is_enabled = &omap2_dflt_clk_is_enabled,
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};
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/**
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* omap36xx_gate_clk_enable_with_hsdiv_restore - enable clocks suffering
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* from HSDivider PWRDN problem Implements Errata ID: i556.
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* @clk: DPLL output struct clk
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*
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* 3630 only: dpll3_m3_ck, dpll4_m2_ck, dpll4_m3_ck, dpll4_m4_ck,
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* dpll4_m5_ck & dpll4_m6_ck dividers gets loaded with reset
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* valueafter their respective PWRDN bits are set. Any dummy write
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* (Any other value different from the Read value) to the
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* corresponding CM_CLKSEL register will refresh the dividers.
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*/
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static int omap36xx_gate_clk_enable_with_hsdiv_restore(struct clk_hw *clk)
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{
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struct clk_divider *parent;
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struct clk_hw *parent_hw;
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u32 dummy_v, orig_v;
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int ret;
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/* Clear PWRDN bit of HSDIVIDER */
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ret = omap2_dflt_clk_enable(clk);
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/* Parent is the x2 node, get parent of parent for the m2 div */
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parent_hw = __clk_get_hw(__clk_get_parent(__clk_get_parent(clk->clk)));
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parent = to_clk_divider(parent_hw);
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/* Restore the dividers */
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if (!ret) {
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orig_v = ti_clk_ll_ops->clk_readl(parent->reg);
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dummy_v = orig_v;
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/* Write any other value different from the Read value */
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dummy_v ^= (1 << parent->shift);
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ti_clk_ll_ops->clk_writel(dummy_v, parent->reg);
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/* Write the original divider */
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ti_clk_ll_ops->clk_writel(orig_v, parent->reg);
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}
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return ret;
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}
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static void __init _of_ti_gate_clk_setup(struct device_node *node,
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const struct clk_ops *ops,
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const struct clk_hw_omap_ops *hw_ops)
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{
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struct clk *clk;
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struct clk_init_data init = { NULL };
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struct clk_hw_omap *clk_hw;
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const char *clk_name = node->name;
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const char *parent_name;
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u32 val;
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clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL);
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if (!clk_hw)
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return;
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clk_hw->hw.init = &init;
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init.name = clk_name;
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init.ops = ops;
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if (ops != &omap_gate_clkdm_clk_ops) {
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clk_hw->enable_reg = ti_clk_get_reg_addr(node, 0);
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if (!clk_hw->enable_reg)
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goto cleanup;
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if (!of_property_read_u32(node, "ti,bit-shift", &val))
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clk_hw->enable_bit = val;
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}
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clk_hw->ops = hw_ops;
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clk_hw->flags = MEMMAP_ADDRESSING;
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if (of_clk_get_parent_count(node) != 1) {
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pr_err("%s must have 1 parent\n", clk_name);
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goto cleanup;
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}
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parent_name = of_clk_get_parent_name(node, 0);
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init.parent_names = &parent_name;
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init.num_parents = 1;
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if (of_property_read_bool(node, "ti,set-rate-parent"))
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init.flags |= CLK_SET_RATE_PARENT;
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if (of_property_read_bool(node, "ti,set-bit-to-disable"))
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clk_hw->flags |= INVERT_ENABLE;
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clk = clk_register(NULL, &clk_hw->hw);
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if (!IS_ERR(clk)) {
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of_clk_add_provider(node, of_clk_src_simple_get, clk);
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return;
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}
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cleanup:
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kfree(clk_hw);
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}
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static void __init
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_of_ti_composite_gate_clk_setup(struct device_node *node,
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const struct clk_hw_omap_ops *hw_ops)
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{
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struct clk_hw_omap *gate;
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u32 val = 0;
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gate = kzalloc(sizeof(*gate), GFP_KERNEL);
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if (!gate)
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return;
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gate->enable_reg = ti_clk_get_reg_addr(node, 0);
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if (!gate->enable_reg)
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goto cleanup;
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of_property_read_u32(node, "ti,bit-shift", &val);
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gate->enable_bit = val;
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gate->ops = hw_ops;
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gate->flags = MEMMAP_ADDRESSING;
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if (!ti_clk_add_component(node, &gate->hw, CLK_COMPONENT_TYPE_GATE))
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return;
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cleanup:
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kfree(gate);
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}
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static void __init
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of_ti_composite_no_wait_gate_clk_setup(struct device_node *node)
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{
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_of_ti_composite_gate_clk_setup(node, NULL);
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}
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CLK_OF_DECLARE(ti_composite_no_wait_gate_clk, "ti,composite-no-wait-gate-clock",
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of_ti_composite_no_wait_gate_clk_setup);
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#ifdef CONFIG_ARCH_OMAP3
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static void __init of_ti_composite_interface_clk_setup(struct device_node *node)
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{
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_of_ti_composite_gate_clk_setup(node, &clkhwops_iclk_wait);
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}
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CLK_OF_DECLARE(ti_composite_interface_clk, "ti,composite-interface-clock",
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of_ti_composite_interface_clk_setup);
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#endif
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static void __init of_ti_composite_gate_clk_setup(struct device_node *node)
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{
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_of_ti_composite_gate_clk_setup(node, &clkhwops_wait);
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}
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CLK_OF_DECLARE(ti_composite_gate_clk, "ti,composite-gate-clock",
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of_ti_composite_gate_clk_setup);
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static void __init of_ti_clkdm_gate_clk_setup(struct device_node *node)
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{
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_of_ti_gate_clk_setup(node, &omap_gate_clkdm_clk_ops, NULL);
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}
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CLK_OF_DECLARE(ti_clkdm_gate_clk, "ti,clkdm-gate-clock",
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of_ti_clkdm_gate_clk_setup);
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static void __init of_ti_hsdiv_gate_clk_setup(struct device_node *node)
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{
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_of_ti_gate_clk_setup(node, &omap_gate_clk_hsdiv_restore_ops,
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&clkhwops_wait);
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}
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CLK_OF_DECLARE(ti_hsdiv_gate_clk, "ti,hsdiv-gate-clock",
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of_ti_hsdiv_gate_clk_setup);
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static void __init of_ti_gate_clk_setup(struct device_node *node)
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{
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_of_ti_gate_clk_setup(node, &omap_gate_clk_ops, NULL);
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}
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CLK_OF_DECLARE(ti_gate_clk, "ti,gate-clock", of_ti_gate_clk_setup)
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static void __init of_ti_wait_gate_clk_setup(struct device_node *node)
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{
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_of_ti_gate_clk_setup(node, &omap_gate_clk_ops, &clkhwops_wait);
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}
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CLK_OF_DECLARE(ti_wait_gate_clk, "ti,wait-gate-clock",
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of_ti_wait_gate_clk_setup);
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#ifdef CONFIG_ARCH_OMAP3
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static void __init of_ti_am35xx_gate_clk_setup(struct device_node *node)
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{
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_of_ti_gate_clk_setup(node, &omap_gate_clk_ops,
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&clkhwops_am35xx_ipss_module_wait);
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}
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CLK_OF_DECLARE(ti_am35xx_gate_clk, "ti,am35xx-gate-clock",
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of_ti_am35xx_gate_clk_setup);
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static void __init of_ti_dss_gate_clk_setup(struct device_node *node)
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{
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_of_ti_gate_clk_setup(node, &omap_gate_clk_ops,
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&clkhwops_omap3430es2_dss_usbhost_wait);
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}
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CLK_OF_DECLARE(ti_dss_gate_clk, "ti,dss-gate-clock",
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of_ti_dss_gate_clk_setup);
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#endif
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@ -244,6 +244,8 @@ long omap2_dpll_round_rate(struct clk_hw *hw, unsigned long target_rate,
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void omap2_init_clk_clkdm(struct clk_hw *clk);
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unsigned long omap3_clkoutx2_recalc(struct clk_hw *hw,
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unsigned long parent_rate);
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int omap2_clkops_enable_clkdm(struct clk_hw *hw);
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void omap2_clkops_disable_clkdm(struct clk_hw *hw);
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int omap3_dpll4_set_rate(struct clk_hw *clk, unsigned long rate,
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unsigned long parent_rate);
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int omap2_dflt_clk_enable(struct clk_hw *hw);
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@ -268,5 +270,9 @@ static inline void of_ti_clk_deny_autoidle_all(void) { }
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extern const struct clk_hw_omap_ops clkhwops_omap3_dpll;
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extern const struct clk_hw_omap_ops clkhwops_omap4_dpllmx;
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extern const struct clk_hw_omap_ops clkhwops_wait;
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extern const struct clk_hw_omap_ops clkhwops_omap3430es2_dss_usbhost_wait;
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extern const struct clk_hw_omap_ops clkhwops_am35xx_ipss_module_wait;
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extern const struct clk_hw_omap_ops clkhwops_iclk_wait;
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#endif
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