This provides the following Integrator refactorings:
- Switch the FPGA IRQ controller to use the simple IRQ domain - Get rid of preallocated IRQ descriptors on the Integrator - Move the FPGA IRQ driver to drivers/irqchip -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJQlqH4AAoJEEEQszewGV1zsUcQALdxORXGin6rbluECrW68/dL zDDV6EO+3Fl8gMIjufd412dMNEjyU33V/Z25Z8GqHfm9o56MFP/J+8S05ES0devp 6GEpOSBfavvjq+rDRUlEnSW1udzJtBEcFlJiiyk2NpDwj6QLR4oU+4MRMtvuPsLO gyXizllkzWkADaxsIB3BxlHhYh8hnF0AKv0rVPBtByIIK8fbxbtryH1GYPpiqJTx 2V0KqedlPtlpFW0ltYdgaYy/+fp15E66QfVGZloQNiRMdnV/laqKwiJr27h4pets bKiZBCyNG8FJl31oJ0RP5DX0JOqL6pDCfzwYUy/T7a4YeD2JRQMw/so5XRZ70QaN Z/whMk6k5FPD2peyBcHUhzBcL2//X01UDUbaJ9SA8bn/E2lMqqGAu8GPwLfEfaU1 XpHe+ydig0AfUbm4bIgoBqNQRGt6l+sTn89WTzK3N48APRZP32rjn+etbHMiF8kJ DuDwH/CfHhH1Tw30t8GBom4w3Gb0tzXcaHhHcYk0Awbiv2lrr8kmDw3YRiK9N2MX +8IiXwhsHNgu8o+jwp0S93kuT+k0P1RAxEbpgHTEsUZ6TQDQsmxbV/88Vz2jaH/S 8kH48iyzRq5b36UNya19ymqFpiOz8SXHibEEn3IhWpdQI9wdfPvVG2vaAaKrqVix fhztJoXJ1x+GG1JsRKgO =OO6W -----END PGP SIGNATURE----- Merge tag 'integrator-irq' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/soc From Linus Walleij: This provides the following Integrator refactorings: - Switch the FPGA IRQ controller to use the simple IRQ domain - Get rid of preallocated IRQ descriptors on the Integrator - Move the FPGA IRQ driver to drivers/irqchip * tag 'integrator-irq' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator: ARM: plat-versatile: move FPGA irq driver to drivers/irqchip ARM: integrator: get rid of preallocated irq descriptors ARM: plat-versatile: use simple irqdomain for FPGA IRQ
This commit is contained in:
Olof Johansson
Коммит
f60be0d5c1
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@ -284,8 +284,8 @@ config ARCH_INTEGRATOR
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select MULTI_IRQ_HANDLER
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select NEED_MACH_MEMORY_H
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select PLAT_VERSATILE
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select PLAT_VERSATILE_FPGA_IRQ
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select SPARSE_IRQ
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select VERSATILE_FPGA_IRQ
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help
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Support for ARM's Integrator platform.
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@ -318,7 +318,7 @@ config ARCH_VERSATILE
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select PLAT_VERSATILE
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select PLAT_VERSATILE_CLCD
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select PLAT_VERSATILE_CLOCK
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select PLAT_VERSATILE_FPGA_IRQ
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select VERSATILE_FPGA_IRQ
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help
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This enables support for ARM Ltd Versatile board.
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@ -19,64 +19,63 @@
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/*
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* Interrupt numbers
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/*
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* Interrupt numbers, all of the above are just static reservations
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* used so they can be encoded into device resources. They will finally
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* be done away with when switching to device tree.
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*/
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#define IRQ_PIC_START 1
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#define IRQ_SOFTINT 1
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#define IRQ_UARTINT0 2
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#define IRQ_UARTINT1 3
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#define IRQ_KMIINT0 4
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#define IRQ_KMIINT1 5
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#define IRQ_TIMERINT0 6
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#define IRQ_TIMERINT1 7
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#define IRQ_TIMERINT2 8
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#define IRQ_RTCINT 9
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#define IRQ_AP_EXPINT0 10
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#define IRQ_AP_EXPINT1 11
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#define IRQ_AP_EXPINT2 12
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#define IRQ_AP_EXPINT3 13
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#define IRQ_AP_PCIINT0 14
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#define IRQ_AP_PCIINT1 15
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#define IRQ_AP_PCIINT2 16
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#define IRQ_AP_PCIINT3 17
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#define IRQ_AP_V3INT 18
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#define IRQ_AP_CPINT0 19
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#define IRQ_AP_CPINT1 20
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#define IRQ_AP_LBUSTIMEOUT 21
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#define IRQ_AP_APCINT 22
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#define IRQ_CP_CLCDCINT 23
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#define IRQ_CP_MMCIINT0 24
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#define IRQ_CP_MMCIINT1 25
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#define IRQ_CP_AACIINT 26
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#define IRQ_CP_CPPLDINT 27
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#define IRQ_CP_ETHINT 28
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#define IRQ_CP_TSPENINT 29
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#define IRQ_PIC_END 29
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#define IRQ_PIC_START 64
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#define IRQ_SOFTINT (IRQ_PIC_START+0)
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#define IRQ_UARTINT0 (IRQ_PIC_START+1)
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#define IRQ_UARTINT1 (IRQ_PIC_START+2)
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#define IRQ_KMIINT0 (IRQ_PIC_START+3)
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#define IRQ_KMIINT1 (IRQ_PIC_START+4)
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#define IRQ_TIMERINT0 (IRQ_PIC_START+5)
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#define IRQ_TIMERINT1 (IRQ_PIC_START+6)
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#define IRQ_TIMERINT2 (IRQ_PIC_START+7)
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#define IRQ_RTCINT (IRQ_PIC_START+8)
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#define IRQ_AP_EXPINT0 (IRQ_PIC_START+9)
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#define IRQ_AP_EXPINT1 (IRQ_PIC_START+10)
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#define IRQ_AP_EXPINT2 (IRQ_PIC_START+11)
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#define IRQ_AP_EXPINT3 (IRQ_PIC_START+12)
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#define IRQ_AP_PCIINT0 (IRQ_PIC_START+13)
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#define IRQ_AP_PCIINT1 (IRQ_PIC_START+14)
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#define IRQ_AP_PCIINT2 (IRQ_PIC_START+15)
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#define IRQ_AP_PCIINT3 (IRQ_PIC_START+16)
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#define IRQ_AP_V3INT (IRQ_PIC_START+17)
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#define IRQ_AP_CPINT0 (IRQ_PIC_START+18)
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#define IRQ_AP_CPINT1 (IRQ_PIC_START+19)
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#define IRQ_AP_LBUSTIMEOUT (IRQ_PIC_START+20)
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#define IRQ_AP_APCINT (IRQ_PIC_START+21)
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#define IRQ_CP_CLCDCINT (IRQ_PIC_START+22)
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#define IRQ_CP_MMCIINT0 (IRQ_PIC_START+23)
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#define IRQ_CP_MMCIINT1 (IRQ_PIC_START+24)
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#define IRQ_CP_AACIINT (IRQ_PIC_START+25)
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#define IRQ_CP_CPPLDINT (IRQ_PIC_START+26)
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#define IRQ_CP_ETHINT (IRQ_PIC_START+27)
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#define IRQ_CP_TSPENINT (IRQ_PIC_START+28)
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#define IRQ_PIC_END (IRQ_PIC_START+28)
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#define IRQ_CIC_START 32
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#define IRQ_CM_SOFTINT 32
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#define IRQ_CM_COMMRX 33
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#define IRQ_CM_COMMTX 34
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#define IRQ_CIC_END 34
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#define IRQ_CIC_START (IRQ_PIC_END+1)
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#define IRQ_CM_SOFTINT (IRQ_CIC_START+0)
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#define IRQ_CM_COMMRX (IRQ_CIC_START+1)
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#define IRQ_CM_COMMTX (IRQ_CIC_START+2)
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#define IRQ_CIC_END (IRQ_CIC_START+2)
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/*
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* IntegratorCP only
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*/
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#define IRQ_SIC_START 35
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#define IRQ_SIC_CP_SOFTINT 35
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#define IRQ_SIC_CP_RI0 36
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#define IRQ_SIC_CP_RI1 37
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#define IRQ_SIC_CP_CARDIN 38
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#define IRQ_SIC_CP_LMINT0 39
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#define IRQ_SIC_CP_LMINT1 40
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#define IRQ_SIC_CP_LMINT2 41
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#define IRQ_SIC_CP_LMINT3 42
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#define IRQ_SIC_CP_LMINT4 43
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#define IRQ_SIC_CP_LMINT5 44
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#define IRQ_SIC_CP_LMINT6 45
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#define IRQ_SIC_CP_LMINT7 46
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#define IRQ_SIC_END 46
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#define NR_IRQS_INTEGRATOR_AP 34
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#define NR_IRQS_INTEGRATOR_CP 47
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#define IRQ_SIC_START (IRQ_CIC_END+1)
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#define IRQ_SIC_CP_SOFTINT (IRQ_SIC_START+0)
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#define IRQ_SIC_CP_RI0 (IRQ_SIC_START+1)
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#define IRQ_SIC_CP_RI1 (IRQ_SIC_START+2)
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#define IRQ_SIC_CP_CARDIN (IRQ_SIC_START+3)
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#define IRQ_SIC_CP_LMINT0 (IRQ_SIC_START+4)
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#define IRQ_SIC_CP_LMINT1 (IRQ_SIC_START+5)
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#define IRQ_SIC_CP_LMINT2 (IRQ_SIC_START+6)
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#define IRQ_SIC_CP_LMINT3 (IRQ_SIC_START+7)
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#define IRQ_SIC_CP_LMINT4 (IRQ_SIC_START+8)
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#define IRQ_SIC_CP_LMINT5 (IRQ_SIC_START+9)
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#define IRQ_SIC_CP_LMINT6 (IRQ_SIC_START+10)
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#define IRQ_SIC_CP_LMINT7 (IRQ_SIC_START+11)
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#define IRQ_SIC_END (IRQ_SIC_START+11)
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@ -31,6 +31,7 @@
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irqchip/versatile-fpga.h>
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#include <linux/mtd/physmap.h>
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#include <linux/clk.h>
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#include <linux/platform_data/clk-integrator.h>
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@ -56,8 +57,6 @@
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#include <asm/mach/pci.h>
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#include <asm/mach/time.h>
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#include <plat/fpga-irq.h>
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#include "common.h"
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/*
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@ -499,7 +498,6 @@ static const char * ap_dt_board_compat[] = {
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DT_MACHINE_START(INTEGRATOR_AP_DT, "ARM Integrator/AP (Device Tree)")
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.reserve = integrator_reserve,
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.map_io = ap_map_io,
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.nr_irqs = NR_IRQS_INTEGRATOR_AP,
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.init_early = ap_init_early,
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.init_irq = ap_init_irq_of,
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.handle_irq = fpga_handle_irq,
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@ -609,7 +607,6 @@ MACHINE_START(INTEGRATOR, "ARM-Integrator")
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.atag_offset = 0x100,
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.reserve = integrator_reserve,
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.map_io = ap_map_io,
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.nr_irqs = NR_IRQS_INTEGRATOR_AP,
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.init_early = ap_init_early,
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.init_irq = ap_init_irq,
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.handle_irq = fpga_handle_irq,
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@ -20,6 +20,7 @@
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#include <linux/amba/clcd.h>
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#include <linux/amba/mmci.h>
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#include <linux/io.h>
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#include <linux/irqchip/versatile-fpga.h>
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#include <linux/gfp.h>
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#include <linux/mtd/physmap.h>
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#include <linux/platform_data/clk-integrator.h>
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@ -46,7 +47,6 @@
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#include <asm/hardware/timer-sp.h>
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#include <plat/clcd.h>
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#include <plat/fpga-irq.h>
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#include <plat/sched_clock.h>
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#include "common.h"
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@ -350,7 +350,6 @@ static const char * intcp_dt_board_compat[] = {
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DT_MACHINE_START(INTEGRATOR_CP_DT, "ARM Integrator/CP (Device Tree)")
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.reserve = integrator_reserve,
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.map_io = intcp_map_io,
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.nr_irqs = NR_IRQS_INTEGRATOR_CP,
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.init_early = intcp_init_early,
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.init_irq = intcp_init_irq_of,
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.handle_irq = fpga_handle_irq,
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@ -423,7 +422,7 @@ static void __init intcp_init_irq(void)
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u32 pic_mask, cic_mask, sic_mask;
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/* These masks are for the HW IRQ registers */
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pic_mask = ~((~0u) << (11 - IRQ_PIC_START));
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pic_mask = ~((~0u) << (11 - 0));
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pic_mask |= (~((~0u) << (29 - 22))) << 22;
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cic_mask = ~((~0u) << (1 + IRQ_CIC_END - IRQ_CIC_START));
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sic_mask = ~((~0u) << (1 + IRQ_SIC_END - IRQ_SIC_START));
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@ -504,7 +503,6 @@ MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
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.atag_offset = 0x100,
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.reserve = integrator_reserve,
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.map_io = intcp_map_io,
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.nr_irqs = NR_IRQS_INTEGRATOR_CP,
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.init_early = intcp_init_early,
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.init_irq = intcp_init_irq,
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.handle_irq = fpga_handle_irq,
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@ -32,6 +32,7 @@
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#include <linux/amba/mmci.h>
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#include <linux/amba/pl022.h>
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#include <linux/io.h>
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#include <linux/irqchip/versatile-fpga.h>
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#include <linux/gfp.h>
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#include <linux/clkdev.h>
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#include <linux/mtd/physmap.h>
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@ -51,7 +52,6 @@
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#include <asm/hardware/timer-sp.h>
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#include <plat/clcd.h>
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#include <plat/fpga-irq.h>
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#include <plat/sched_clock.h>
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#include "core.h"
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@ -6,15 +6,6 @@ config PLAT_VERSATILE_CLOCK
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config PLAT_VERSATILE_CLCD
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bool
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config PLAT_VERSATILE_FPGA_IRQ
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bool
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select IRQ_DOMAIN
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config PLAT_VERSATILE_FPGA_IRQ_NR
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int
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default 4
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depends on PLAT_VERSATILE_FPGA_IRQ
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config PLAT_VERSATILE_LEDS
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def_bool y if NEW_LEDS
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depends on ARCH_REALVIEW || ARCH_VERSATILE
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@ -2,7 +2,6 @@ ccflags-$(CONFIG_ARCH_MULTIPLATFORM) := -I$(srctree)/$(src)/include
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obj-$(CONFIG_PLAT_VERSATILE_CLOCK) += clock.o
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obj-$(CONFIG_PLAT_VERSATILE_CLCD) += clcd.o
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obj-$(CONFIG_PLAT_VERSATILE_FPGA_IRQ) += fpga-irq.o
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obj-$(CONFIG_PLAT_VERSATILE_LEDS) += leds.o
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obj-$(CONFIG_PLAT_VERSATILE_SCHED_CLOCK) += sched-clock.o
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obj-$(CONFIG_SMP) += headsmp.o platsmp.o
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@ -1 +1,8 @@
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# empty
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config VERSATILE_FPGA_IRQ
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bool
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select IRQ_DOMAIN
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config VERSATILE_FPGA_IRQ_NR
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int
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default 4
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depends on VERSATILE_FPGA_IRQ
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@ -1 +1,2 @@
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obj-$(CONFIG_ARCH_BCM2835) += irq-bcm2835.o
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obj-$(CONFIG_VERSATILE_FPGA_IRQ) += irq-versatile-fpga.o
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@ -1,8 +1,10 @@
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/*
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* Support for Versatile FPGA-based IRQ controllers
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*/
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#include <linux/bitops.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/irqchip/versatile-fpga.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/of.h>
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@ -10,7 +12,6 @@
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#include <asm/exception.h>
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#include <asm/mach/irq.h>
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#include <plat/fpga-irq.h>
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#define IRQ_STATUS 0x00
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#define IRQ_RAW_STATUS 0x04
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@ -41,7 +42,7 @@ struct fpga_irq_data {
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};
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/* we cannot allocate memory when the controllers are initially registered */
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static struct fpga_irq_data fpga_irq_devices[CONFIG_PLAT_VERSATILE_FPGA_IRQ_NR];
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static struct fpga_irq_data fpga_irq_devices[CONFIG_VERSATILE_FPGA_IRQ_NR];
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static int fpga_irq_id;
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static void fpga_irq_mask(struct irq_data *d)
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@ -117,13 +118,12 @@ static int fpga_irqdomain_map(struct irq_domain *d, unsigned int irq,
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struct fpga_irq_data *f = d->host_data;
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/* Skip invalid IRQs, only register handlers for the real ones */
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if (!(f->valid & (1 << hwirq)))
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if (!(f->valid & BIT(hwirq)))
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return -ENOTSUPP;
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irq_set_chip_data(irq, f);
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irq_set_chip_and_handler(irq, &f->chip,
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handle_level_irq);
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set_irq_flags(irq, IRQF_VALID | IRQF_PROBE);
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f->used_irqs++;
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return 0;
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}
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@ -132,13 +132,15 @@ static struct irq_domain_ops fpga_irqdomain_ops = {
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.xlate = irq_domain_xlate_onetwocell,
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};
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static __init struct fpga_irq_data *
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fpga_irq_prep_struct(void __iomem *base, const char *name, u32 valid) {
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void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start,
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int parent_irq, u32 valid, struct device_node *node)
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{
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struct fpga_irq_data *f;
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int i;
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if (fpga_irq_id >= ARRAY_SIZE(fpga_irq_devices)) {
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printk(KERN_ERR "%s: too few FPGA IRQ controllers, increase CONFIG_PLAT_VERSATILE_FPGA_IRQ_NR\n", __func__);
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return NULL;
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pr_err("%s: too few FPGA IRQ controllers, increase CONFIG_PLAT_VERSATILE_FPGA_IRQ_NR\n", __func__);
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return;
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}
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f = &fpga_irq_devices[fpga_irq_id];
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f->base = base;
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@ -147,29 +149,28 @@ fpga_irq_prep_struct(void __iomem *base, const char *name, u32 valid) {
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f->chip.irq_mask = fpga_irq_mask;
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f->chip.irq_unmask = fpga_irq_unmask;
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f->valid = valid;
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fpga_irq_id++;
|
||||
|
||||
return f;
|
||||
}
|
||||
|
||||
void __init fpga_irq_init(void __iomem *base, const char *name, int irq_start,
|
||||
int parent_irq, u32 valid, struct device_node *node)
|
||||
{
|
||||
struct fpga_irq_data *f;
|
||||
|
||||
f = fpga_irq_prep_struct(base, name, valid);
|
||||
if (!f)
|
||||
return;
|
||||
|
||||
if (parent_irq != -1) {
|
||||
irq_set_handler_data(parent_irq, f);
|
||||
irq_set_chained_handler(parent_irq, fpga_irq_handle);
|
||||
}
|
||||
|
||||
f->domain = irq_domain_add_legacy(node, fls(valid), irq_start, 0,
|
||||
/* This will also allocate irq descriptors */
|
||||
f->domain = irq_domain_add_simple(node, fls(valid), irq_start,
|
||||
&fpga_irqdomain_ops, f);
|
||||
|
||||
/* This will allocate all valid descriptors in the linear case */
|
||||
for (i = 0; i < fls(valid); i++)
|
||||
if (valid & BIT(i)) {
|
||||
if (!irq_start)
|
||||
irq_create_mapping(f->domain, i);
|
||||
f->used_irqs++;
|
||||
}
|
||||
|
||||
pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs\n",
|
||||
fpga_irq_id, name, base, f->used_irqs);
|
||||
|
||||
fpga_irq_id++;
|
||||
}
|
||||
|
||||
#ifdef CONFIG_OF
|
||||
|
|
@ -193,18 +194,11 @@ int __init fpga_irq_of_init(struct device_node *node,
|
|||
if (of_property_read_u32(node, "valid-mask", &valid_mask))
|
||||
valid_mask = 0;
|
||||
|
||||
f = fpga_irq_prep_struct(base, node->name, valid_mask);
|
||||
if (!f)
|
||||
return -ENOMEM;
|
||||
fpga_irq_init(base, node->name, 0, -1, valid_mask, node);
|
||||
|
||||
writel(clear_mask, base + IRQ_ENABLE_CLEAR);
|
||||
writel(clear_mask, base + FIQ_ENABLE_CLEAR);
|
||||
|
||||
f->domain = irq_domain_add_linear(node, fls(valid_mask), &fpga_irqdomain_ops, f);
|
||||
f->used_irqs = hweight32(valid_mask);
|
||||
|
||||
pr_info("FPGA IRQ chip %d \"%s\" @ %p, %u irqs\n",
|
||||
fpga_irq_id, node->name, base, f->used_irqs);
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
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