clk: berlin: Migrate to clk_hw based registration and OF APIs
Now that we have clk_hw based provider APIs to register clks, we can get rid of struct clk pointers while registering clks in these drivers, allowing us to move closer to a clear split of consumer and provider clk APIs. We also remove some __init markings in header files as they're useless and we're in the area. Tested-by: Jisheng Zhang <jszhang@marvell.com> Cc: Alexandre Belloni <alexandre.belloni@free-electrons.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Stephen Boyd
Stephen Boyd
Родитель
57c4a2ac8f
Коммит
f6475e2982
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@ -188,7 +188,7 @@ static const struct clk_ops berlin2_avpll_vco_ops = {
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.recalc_rate = berlin2_avpll_vco_recalc_rate,
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};
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struct clk * __init berlin2_avpll_vco_register(void __iomem *base,
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int __init berlin2_avpll_vco_register(void __iomem *base,
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const char *name, const char *parent_name,
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u8 vco_flags, unsigned long flags)
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{
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@ -197,7 +197,7 @@ struct clk * __init berlin2_avpll_vco_register(void __iomem *base,
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vco = kzalloc(sizeof(*vco), GFP_KERNEL);
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if (!vco)
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return ERR_PTR(-ENOMEM);
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return -ENOMEM;
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vco->base = base;
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vco->flags = vco_flags;
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@ -208,7 +208,7 @@ struct clk * __init berlin2_avpll_vco_register(void __iomem *base,
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init.num_parents = 1;
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init.flags = flags;
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return clk_register(NULL, &vco->hw);
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return clk_hw_register(NULL, &vco->hw);
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}
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struct berlin2_avpll_channel {
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@ -364,7 +364,7 @@ static const struct clk_ops berlin2_avpll_channel_ops = {
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*/
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static const u8 quirk_index[] __initconst = { 0, 6, 5, 4, 3, 2, 1, 7 };
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struct clk * __init berlin2_avpll_channel_register(void __iomem *base,
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int __init berlin2_avpll_channel_register(void __iomem *base,
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const char *name, u8 index, const char *parent_name,
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u8 ch_flags, unsigned long flags)
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{
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@ -373,7 +373,7 @@ struct clk * __init berlin2_avpll_channel_register(void __iomem *base,
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ch = kzalloc(sizeof(*ch), GFP_KERNEL);
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if (!ch)
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return ERR_PTR(-ENOMEM);
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return -ENOMEM;
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ch->base = base;
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if (ch_flags & BERLIN2_AVPLL_SCRAMBLE_QUIRK)
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@ -389,5 +389,5 @@ struct clk * __init berlin2_avpll_channel_register(void __iomem *base,
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init.num_parents = 1;
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init.flags = flags;
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return clk_register(NULL, &ch->hw);
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return clk_hw_register(NULL, &ch->hw);
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}
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@ -19,17 +19,13 @@
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#ifndef __BERLIN2_AVPLL_H
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#define __BERLIN2_AVPLL_H
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struct clk;
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#define BERLIN2_AVPLL_BIT_QUIRK BIT(0)
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#define BERLIN2_AVPLL_SCRAMBLE_QUIRK BIT(1)
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struct clk * __init
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berlin2_avpll_vco_register(void __iomem *base, const char *name,
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int berlin2_avpll_vco_register(void __iomem *base, const char *name,
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const char *parent_name, u8 vco_flags, unsigned long flags);
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struct clk * __init
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berlin2_avpll_channel_register(void __iomem *base, const char *name,
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int berlin2_avpll_channel_register(void __iomem *base, const char *name,
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u8 index, const char *parent_name, u8 ch_flags,
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unsigned long flags);
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@ -234,7 +234,7 @@ static const struct clk_ops berlin2_div_mux_ops = {
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.get_parent = berlin2_div_get_parent,
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};
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struct clk * __init
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struct clk_hw * __init
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berlin2_div_register(const struct berlin2_div_map *map,
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void __iomem *base, const char *name, u8 div_flags,
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const char **parent_names, int num_parents,
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@ -259,7 +259,7 @@ berlin2_div_register(const struct berlin2_div_map *map,
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if ((div_flags & BERLIN2_DIV_HAS_MUX) == 0)
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mux_ops = NULL;
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return clk_register_composite(NULL, name, parent_names, num_parents,
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return clk_hw_register_composite(NULL, name, parent_names, num_parents,
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&div->hw, mux_ops, &div->hw, rate_ops,
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&div->hw, gate_ops, flags);
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}
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@ -19,7 +19,7 @@
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#ifndef __BERLIN2_DIV_H
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#define __BERLIN2_DIV_H
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struct clk;
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struct clk_hw;
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#define BERLIN2_DIV_HAS_GATE BIT(0)
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#define BERLIN2_DIV_HAS_MUX BIT(1)
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@ -80,7 +80,7 @@ struct berlin2_div_data {
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u8 div_flags;
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};
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struct clk * __init
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struct clk_hw *
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berlin2_div_register(const struct berlin2_div_map *map,
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void __iomem *base, const char *name, u8 div_flags,
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const char **parent_names, int num_parents,
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@ -84,7 +84,7 @@ static const struct clk_ops berlin2_pll_ops = {
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.recalc_rate = berlin2_pll_recalc_rate,
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};
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struct clk * __init
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int __init
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berlin2_pll_register(const struct berlin2_pll_map *map,
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void __iomem *base, const char *name,
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const char *parent_name, unsigned long flags)
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@ -94,7 +94,7 @@ berlin2_pll_register(const struct berlin2_pll_map *map,
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pll = kzalloc(sizeof(*pll), GFP_KERNEL);
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if (!pll)
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return ERR_PTR(-ENOMEM);
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return -ENOMEM;
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/* copy pll_map to allow __initconst */
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memcpy(&pll->map, map, sizeof(*map));
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@ -106,5 +106,5 @@ berlin2_pll_register(const struct berlin2_pll_map *map,
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init.num_parents = 1;
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init.flags = flags;
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return clk_register(NULL, &pll->hw);
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return clk_hw_register(NULL, &pll->hw);
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}
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@ -19,8 +19,6 @@
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#ifndef __BERLIN2_PLL_H
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#define __BERLIN2_PLL_H
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struct clk;
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struct berlin2_pll_map {
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const u8 vcodiv[16];
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u8 mult;
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@ -29,9 +27,8 @@ struct berlin2_pll_map {
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u8 divsel_shift;
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};
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struct clk * __init
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berlin2_pll_register(const struct berlin2_pll_map *map,
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void __iomem *base, const char *name,
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const char *parent_name, unsigned long flags);
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int berlin2_pll_register(const struct berlin2_pll_map *map,
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void __iomem *base, const char *name,
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const char *parent_name, unsigned long flags);
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#endif /* __BERLIN2_PLL_H */
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@ -92,8 +92,7 @@
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*/
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#define MAX_CLKS 41
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static struct clk *clks[MAX_CLKS];
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static struct clk_onecell_data clk_data;
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static struct clk_hw_onecell_data *clk_data;
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static DEFINE_SPINLOCK(lock);
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static void __iomem *gbase;
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@ -505,8 +504,17 @@ static void __init berlin2_clock_setup(struct device_node *np)
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struct device_node *parent_np = of_get_parent(np);
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const char *parent_names[9];
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struct clk *clk;
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struct clk_hw *hw;
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struct clk_hw **hws;
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u8 avpll_flags = 0;
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int n;
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int n, ret;
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clk_data = kzalloc(sizeof(*clk_data) +
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sizeof(*clk_data->hws) * MAX_CLKS, GFP_KERNEL);
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if (!clk_data)
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return;
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clk_data->num = MAX_CLKS;
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hws = clk_data->hws;
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gbase = of_iomap(parent_np, 0);
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if (!gbase)
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@ -526,118 +534,118 @@ static void __init berlin2_clock_setup(struct device_node *np)
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}
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/* simple register PLLs */
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clk = berlin2_pll_register(&bg2_pll_map, gbase + REG_SYSPLLCTL0,
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ret = berlin2_pll_register(&bg2_pll_map, gbase + REG_SYSPLLCTL0,
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clk_names[SYSPLL], clk_names[REFCLK], 0);
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if (IS_ERR(clk))
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if (ret)
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goto bg2_fail;
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clk = berlin2_pll_register(&bg2_pll_map, gbase + REG_MEMPLLCTL0,
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ret = berlin2_pll_register(&bg2_pll_map, gbase + REG_MEMPLLCTL0,
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clk_names[MEMPLL], clk_names[REFCLK], 0);
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if (IS_ERR(clk))
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if (ret)
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goto bg2_fail;
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clk = berlin2_pll_register(&bg2_pll_map, gbase + REG_CPUPLLCTL0,
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ret = berlin2_pll_register(&bg2_pll_map, gbase + REG_CPUPLLCTL0,
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clk_names[CPUPLL], clk_names[REFCLK], 0);
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if (IS_ERR(clk))
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if (ret)
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goto bg2_fail;
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if (of_device_is_compatible(np, "marvell,berlin2-global-register"))
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avpll_flags |= BERLIN2_AVPLL_SCRAMBLE_QUIRK;
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/* audio/video VCOs */
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clk = berlin2_avpll_vco_register(gbase + REG_AVPLLCTL0, "avpll_vcoA",
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ret = berlin2_avpll_vco_register(gbase + REG_AVPLLCTL0, "avpll_vcoA",
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clk_names[REFCLK], avpll_flags, 0);
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if (IS_ERR(clk))
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if (ret)
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goto bg2_fail;
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for (n = 0; n < 8; n++) {
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clk = berlin2_avpll_channel_register(gbase + REG_AVPLLCTL0,
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ret = berlin2_avpll_channel_register(gbase + REG_AVPLLCTL0,
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clk_names[AVPLL_A1 + n], n, "avpll_vcoA",
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avpll_flags, 0);
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if (IS_ERR(clk))
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if (ret)
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goto bg2_fail;
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}
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clk = berlin2_avpll_vco_register(gbase + REG_AVPLLCTL31, "avpll_vcoB",
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ret = berlin2_avpll_vco_register(gbase + REG_AVPLLCTL31, "avpll_vcoB",
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clk_names[REFCLK], BERLIN2_AVPLL_BIT_QUIRK |
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avpll_flags, 0);
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if (IS_ERR(clk))
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if (ret)
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goto bg2_fail;
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for (n = 0; n < 8; n++) {
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clk = berlin2_avpll_channel_register(gbase + REG_AVPLLCTL31,
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ret = berlin2_avpll_channel_register(gbase + REG_AVPLLCTL31,
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clk_names[AVPLL_B1 + n], n, "avpll_vcoB",
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BERLIN2_AVPLL_BIT_QUIRK | avpll_flags, 0);
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if (IS_ERR(clk))
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if (ret)
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goto bg2_fail;
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}
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/* reference clock bypass switches */
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parent_names[0] = clk_names[SYSPLL];
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parent_names[1] = clk_names[REFCLK];
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clk = clk_register_mux(NULL, "syspll_byp", parent_names, 2,
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hw = clk_hw_register_mux(NULL, "syspll_byp", parent_names, 2,
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0, gbase + REG_CLKSWITCH0, 0, 1, 0, &lock);
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if (IS_ERR(clk))
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if (IS_ERR(hw))
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goto bg2_fail;
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clk_names[SYSPLL] = __clk_get_name(clk);
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clk_names[SYSPLL] = clk_hw_get_name(hw);
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parent_names[0] = clk_names[MEMPLL];
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parent_names[1] = clk_names[REFCLK];
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clk = clk_register_mux(NULL, "mempll_byp", parent_names, 2,
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hw = clk_hw_register_mux(NULL, "mempll_byp", parent_names, 2,
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0, gbase + REG_CLKSWITCH0, 1, 1, 0, &lock);
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if (IS_ERR(clk))
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if (IS_ERR(hw))
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goto bg2_fail;
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clk_names[MEMPLL] = __clk_get_name(clk);
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clk_names[MEMPLL] = clk_hw_get_name(hw);
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parent_names[0] = clk_names[CPUPLL];
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parent_names[1] = clk_names[REFCLK];
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clk = clk_register_mux(NULL, "cpupll_byp", parent_names, 2,
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hw = clk_hw_register_mux(NULL, "cpupll_byp", parent_names, 2,
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0, gbase + REG_CLKSWITCH0, 2, 1, 0, &lock);
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if (IS_ERR(clk))
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if (IS_ERR(hw))
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goto bg2_fail;
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clk_names[CPUPLL] = __clk_get_name(clk);
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clk_names[CPUPLL] = clk_hw_get_name(hw);
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/* clock muxes */
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parent_names[0] = clk_names[AVPLL_B3];
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parent_names[1] = clk_names[AVPLL_A3];
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clk = clk_register_mux(NULL, clk_names[AUDIO1_PLL], parent_names, 2,
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hw = clk_hw_register_mux(NULL, clk_names[AUDIO1_PLL], parent_names, 2,
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0, gbase + REG_CLKSELECT2, 29, 1, 0, &lock);
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if (IS_ERR(clk))
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if (IS_ERR(hw))
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goto bg2_fail;
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parent_names[0] = clk_names[VIDEO0_PLL];
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parent_names[1] = clk_names[VIDEO_EXT0];
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clk = clk_register_mux(NULL, clk_names[VIDEO0_IN], parent_names, 2,
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hw = clk_hw_register_mux(NULL, clk_names[VIDEO0_IN], parent_names, 2,
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0, gbase + REG_CLKSELECT3, 4, 1, 0, &lock);
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if (IS_ERR(clk))
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if (IS_ERR(hw))
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goto bg2_fail;
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parent_names[0] = clk_names[VIDEO1_PLL];
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parent_names[1] = clk_names[VIDEO_EXT0];
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clk = clk_register_mux(NULL, clk_names[VIDEO1_IN], parent_names, 2,
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hw = clk_hw_register_mux(NULL, clk_names[VIDEO1_IN], parent_names, 2,
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0, gbase + REG_CLKSELECT3, 6, 1, 0, &lock);
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if (IS_ERR(clk))
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if (IS_ERR(hw))
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goto bg2_fail;
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parent_names[0] = clk_names[AVPLL_A2];
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parent_names[1] = clk_names[AVPLL_B2];
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clk = clk_register_mux(NULL, clk_names[VIDEO1_PLL], parent_names, 2,
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hw = clk_hw_register_mux(NULL, clk_names[VIDEO1_PLL], parent_names, 2,
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0, gbase + REG_CLKSELECT3, 7, 1, 0, &lock);
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if (IS_ERR(clk))
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if (IS_ERR(hw))
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goto bg2_fail;
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parent_names[0] = clk_names[VIDEO2_PLL];
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parent_names[1] = clk_names[VIDEO_EXT0];
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clk = clk_register_mux(NULL, clk_names[VIDEO2_IN], parent_names, 2,
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hw = clk_hw_register_mux(NULL, clk_names[VIDEO2_IN], parent_names, 2,
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0, gbase + REG_CLKSELECT3, 9, 1, 0, &lock);
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if (IS_ERR(clk))
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if (IS_ERR(hw))
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goto bg2_fail;
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parent_names[0] = clk_names[AVPLL_B1];
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parent_names[1] = clk_names[AVPLL_A5];
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clk = clk_register_mux(NULL, clk_names[VIDEO2_PLL], parent_names, 2,
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hw = clk_hw_register_mux(NULL, clk_names[VIDEO2_PLL], parent_names, 2,
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0, gbase + REG_CLKSELECT3, 10, 1, 0, &lock);
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if (IS_ERR(clk))
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if (IS_ERR(hw))
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goto bg2_fail;
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/* clock divider cells */
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@ -648,7 +656,7 @@ static void __init berlin2_clock_setup(struct device_node *np)
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for (k = 0; k < dd->num_parents; k++)
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parent_names[k] = clk_names[dd->parent_ids[k]];
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clks[CLKID_SYS + n] = berlin2_div_register(&dd->map, gbase,
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hws[CLKID_SYS + n] = berlin2_div_register(&dd->map, gbase,
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dd->name, dd->div_flags, parent_names,
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dd->num_parents, dd->flags, &lock);
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}
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@ -657,18 +665,18 @@ static void __init berlin2_clock_setup(struct device_node *np)
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for (n = 0; n < ARRAY_SIZE(bg2_gates); n++) {
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const struct berlin2_gate_data *gd = &bg2_gates[n];
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clks[CLKID_GETH0 + n] = clk_register_gate(NULL, gd->name,
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hws[CLKID_GETH0 + n] = clk_hw_register_gate(NULL, gd->name,
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gd->parent_name, gd->flags, gbase + REG_CLKENABLE,
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gd->bit_idx, 0, &lock);
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}
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/* twdclk is derived from cpu/3 */
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clks[CLKID_TWD] =
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clk_register_fixed_factor(NULL, "twd", "cpu", 0, 1, 3);
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hws[CLKID_TWD] =
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clk_hw_register_fixed_factor(NULL, "twd", "cpu", 0, 1, 3);
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/* check for errors on leaf clocks */
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for (n = 0; n < MAX_CLKS; n++) {
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if (!IS_ERR(clks[n]))
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if (!IS_ERR(hws[n]))
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continue;
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pr_err("%s: Unable to register leaf clock %d\n",
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@ -677,9 +685,7 @@ static void __init berlin2_clock_setup(struct device_node *np)
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}
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/* register clk-provider */
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clk_data.clks = clks;
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clk_data.clk_num = MAX_CLKS;
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data);
|
||||
|
||||
return;
|
||||
|
||||
|
|
|
|||
|
|
@ -46,8 +46,7 @@
|
|||
#define REG_SDIO1XIN_CLKCTL 0x015c
|
||||
|
||||
#define MAX_CLKS 28
|
||||
static struct clk *clks[MAX_CLKS];
|
||||
static struct clk_onecell_data clk_data;
|
||||
static struct clk_hw_onecell_data *clk_data;
|
||||
static DEFINE_SPINLOCK(lock);
|
||||
static void __iomem *gbase;
|
||||
static void __iomem *cpupll_base;
|
||||
|
|
@ -293,7 +292,15 @@ static void __init berlin2q_clock_setup(struct device_node *np)
|
|||
struct device_node *parent_np = of_get_parent(np);
|
||||
const char *parent_names[9];
|
||||
struct clk *clk;
|
||||
int n;
|
||||
struct clk_hw **hws;
|
||||
int n, ret;
|
||||
|
||||
clk_data = kzalloc(sizeof(*clk_data) +
|
||||
sizeof(*clk_data->hws) * MAX_CLKS, GFP_KERNEL);
|
||||
if (!clk_data)
|
||||
return;
|
||||
clk_data->num = MAX_CLKS;
|
||||
hws = clk_data->hws;
|
||||
|
||||
gbase = of_iomap(parent_np, 0);
|
||||
if (!gbase) {
|
||||
|
|
@ -317,14 +324,14 @@ static void __init berlin2q_clock_setup(struct device_node *np)
|
|||
}
|
||||
|
||||
/* simple register PLLs */
|
||||
clk = berlin2_pll_register(&bg2q_pll_map, gbase + REG_SYSPLLCTL0,
|
||||
ret = berlin2_pll_register(&bg2q_pll_map, gbase + REG_SYSPLLCTL0,
|
||||
clk_names[SYSPLL], clk_names[REFCLK], 0);
|
||||
if (IS_ERR(clk))
|
||||
if (ret)
|
||||
goto bg2q_fail;
|
||||
|
||||
clk = berlin2_pll_register(&bg2q_pll_map, cpupll_base,
|
||||
ret = berlin2_pll_register(&bg2q_pll_map, cpupll_base,
|
||||
clk_names[CPUPLL], clk_names[REFCLK], 0);
|
||||
if (IS_ERR(clk))
|
||||
if (ret)
|
||||
goto bg2q_fail;
|
||||
|
||||
/* TODO: add BG2Q AVPLL */
|
||||
|
|
@ -342,7 +349,7 @@ static void __init berlin2q_clock_setup(struct device_node *np)
|
|||
for (k = 0; k < dd->num_parents; k++)
|
||||
parent_names[k] = clk_names[dd->parent_ids[k]];
|
||||
|
||||
clks[CLKID_SYS + n] = berlin2_div_register(&dd->map, gbase,
|
||||
hws[CLKID_SYS + n] = berlin2_div_register(&dd->map, gbase,
|
||||
dd->name, dd->div_flags, parent_names,
|
||||
dd->num_parents, dd->flags, &lock);
|
||||
}
|
||||
|
|
@ -351,22 +358,22 @@ static void __init berlin2q_clock_setup(struct device_node *np)
|
|||
for (n = 0; n < ARRAY_SIZE(bg2q_gates); n++) {
|
||||
const struct berlin2_gate_data *gd = &bg2q_gates[n];
|
||||
|
||||
clks[CLKID_GFX2DAXI + n] = clk_register_gate(NULL, gd->name,
|
||||
hws[CLKID_GFX2DAXI + n] = clk_hw_register_gate(NULL, gd->name,
|
||||
gd->parent_name, gd->flags, gbase + REG_CLKENABLE,
|
||||
gd->bit_idx, 0, &lock);
|
||||
}
|
||||
|
||||
/* cpuclk divider is fixed to 1 */
|
||||
clks[CLKID_CPU] =
|
||||
clk_register_fixed_factor(NULL, "cpu", clk_names[CPUPLL],
|
||||
hws[CLKID_CPU] =
|
||||
clk_hw_register_fixed_factor(NULL, "cpu", clk_names[CPUPLL],
|
||||
0, 1, 1);
|
||||
/* twdclk is derived from cpu/3 */
|
||||
clks[CLKID_TWD] =
|
||||
clk_register_fixed_factor(NULL, "twd", "cpu", 0, 1, 3);
|
||||
hws[CLKID_TWD] =
|
||||
clk_hw_register_fixed_factor(NULL, "twd", "cpu", 0, 1, 3);
|
||||
|
||||
/* check for errors on leaf clocks */
|
||||
for (n = 0; n < MAX_CLKS; n++) {
|
||||
if (!IS_ERR(clks[n]))
|
||||
if (!IS_ERR(hws[n]))
|
||||
continue;
|
||||
|
||||
pr_err("%s: Unable to register leaf clock %d\n",
|
||||
|
|
@ -375,9 +382,7 @@ static void __init berlin2q_clock_setup(struct device_node *np)
|
|||
}
|
||||
|
||||
/* register clk-provider */
|
||||
clk_data.clks = clks;
|
||||
clk_data.clk_num = MAX_CLKS;
|
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
|
||||
of_clk_add_hw_provider(np, of_clk_hw_onecell_get, &clk_data);
|
||||
|
||||
return;
|
||||
|
||||
|
|
|
|||
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