ARM: S5PV210: Add sclk clocks of type 'struct clksrc_clk' clock
Add sclk clocks of type 'struct clksrc_clk' clock. The 'group2' of clock clock sources is also added. This patch also changes the the 'id' member value of the uclk1 clock for instance instance 0 since there are 4 instances of the uclk1 clock. Signed-off-by: Thomas Abraham <thomas.ab@samsung.com> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Ben Dooks <ben-linux@fluff.org>
This commit is contained in:
Thomas Abraham
Ben Dooks
Родитель
4583487c43
Коммит
f64cacc319
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@ -173,6 +173,11 @@ static int s5pv210_clk_ip3_ctrl(struct clk *clk, int enable)
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return s5p_gatectrl(S5P_CLKGATE_IP3, clk, enable);
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}
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static int s5pv210_clk_ip4_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(S5P_CLKGATE_IP4, clk, enable);
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}
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static int s5pv210_clk_mask0_ctrl(struct clk *clk, int enable)
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{
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return s5p_gatectrl(S5P_CLK_SRC_MASK0, clk, enable);
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@ -637,6 +642,23 @@ static struct clksrc_sources clkset_sclk_spdif = {
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.nr_sources = ARRAY_SIZE(clkset_sclk_spdif_list),
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};
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static struct clk *clkset_group2_list[] = {
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[0] = &clk_ext_xtal_mux,
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[1] = &clk_xusbxti,
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[2] = &clk_sclk_hdmi27m,
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[3] = &clk_sclk_usbphy0,
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[4] = &clk_sclk_usbphy1,
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[5] = &clk_sclk_hdmiphy,
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[6] = &clk_mout_mpll.clk,
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[7] = &clk_mout_epll.clk,
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[8] = &clk_sclk_vpll.clk,
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};
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static struct clksrc_sources clkset_group2 = {
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.sources = clkset_group2_list,
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.nr_sources = ARRAY_SIZE(clkset_group2_list),
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};
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static struct clksrc_clk clksrcs[] = {
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{
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.clk = {
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@ -657,13 +679,43 @@ static struct clksrc_clk clksrcs[] = {
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}, {
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.clk = {
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.name = "uclk1",
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.id = -1,
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.id = 0,
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.ctrlbit = (1<<17),
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.enable = s5pv210_clk_ip3_ctrl,
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},
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.sources = &clkset_uart,
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.reg_src = { .reg = S5P_CLK_SRC4, .shift = 16, .size = 4 },
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.reg_div = { .reg = S5P_CLK_DIV4, .shift = 16, .size = 4 },
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}, {
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.clk = {
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.name = "uclk1",
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.id = 1,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1 << 18),
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},
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.sources = &clkset_uart,
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.reg_src = { .reg = S5P_CLK_SRC4, .shift = 20, .size = 4 },
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.reg_div = { .reg = S5P_CLK_DIV4, .shift = 20, .size = 4 },
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}, {
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.clk = {
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.name = "uclk1",
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.id = 2,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1 << 19),
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},
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.sources = &clkset_uart,
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.reg_src = { .reg = S5P_CLK_SRC4, .shift = 24, .size = 4 },
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.reg_div = { .reg = S5P_CLK_DIV4, .shift = 24, .size = 4 },
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}, {
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.clk = {
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.name = "uclk1",
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.id = 3,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1 << 20),
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},
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.sources = &clkset_uart,
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.reg_src = { .reg = S5P_CLK_SRC4, .shift = 28, .size = 4 },
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.reg_div = { .reg = S5P_CLK_DIV4, .shift = 28, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_mixer",
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@ -682,6 +734,182 @@ static struct clksrc_clk clksrcs[] = {
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},
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.sources = &clkset_sclk_spdif,
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.reg_src = { .reg = S5P_CLK_SRC6, .shift = 12, .size = 2 },
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}, {
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.clk = {
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.name = "sclk_fimc",
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.id = 0,
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.enable = s5pv210_clk_ip0_ctrl,
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.ctrlbit = (1 << 24),
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P_CLK_SRC3, .shift = 12, .size = 4 },
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.reg_div = { .reg = S5P_CLK_DIV3, .shift = 12, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_fimc",
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.id = 1,
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.enable = s5pv210_clk_ip0_ctrl,
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.ctrlbit = (1 << 25),
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P_CLK_SRC3, .shift = 16, .size = 4 },
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.reg_div = { .reg = S5P_CLK_DIV3, .shift = 16, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_fimc",
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.id = 2,
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.enable = s5pv210_clk_ip0_ctrl,
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.ctrlbit = (1 << 26),
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P_CLK_SRC3, .shift = 20, .size = 4 },
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.reg_div = { .reg = S5P_CLK_DIV3, .shift = 20, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_cam",
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.id = 0,
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P_CLK_SRC1, .shift = 12, .size = 4 },
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.reg_div = { .reg = S5P_CLK_DIV1, .shift = 12, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_cam",
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.id = 1,
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P_CLK_SRC1, .shift = 16, .size = 4 },
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.reg_div = { .reg = S5P_CLK_DIV1, .shift = 16, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_fimd",
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.id = -1,
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.enable = s5pv210_clk_ip1_ctrl,
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.ctrlbit = (1 << 0),
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P_CLK_SRC1, .shift = 20, .size = 4 },
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.reg_div = { .reg = S5P_CLK_DIV1, .shift = 20, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_mmc",
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.id = 0,
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.enable = s5pv210_clk_ip2_ctrl,
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.ctrlbit = (1 << 16),
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P_CLK_SRC4, .shift = 0, .size = 4 },
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.reg_div = { .reg = S5P_CLK_DIV4, .shift = 0, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_mmc",
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.id = 1,
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.enable = s5pv210_clk_ip2_ctrl,
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.ctrlbit = (1 << 17),
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P_CLK_SRC4, .shift = 4, .size = 4 },
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.reg_div = { .reg = S5P_CLK_DIV4, .shift = 4, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_mmc",
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.id = 2,
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.enable = s5pv210_clk_ip2_ctrl,
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.ctrlbit = (1 << 18),
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P_CLK_SRC4, .shift = 8, .size = 4 },
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.reg_div = { .reg = S5P_CLK_DIV4, .shift = 8, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_mmc",
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.id = 3,
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.enable = s5pv210_clk_ip2_ctrl,
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.ctrlbit = (1 << 19),
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P_CLK_SRC4, .shift = 12, .size = 4 },
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.reg_div = { .reg = S5P_CLK_DIV4, .shift = 12, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_mfc",
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.id = -1,
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.enable = s5pv210_clk_ip0_ctrl,
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.ctrlbit = (1 << 16),
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},
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.sources = &clkset_group1,
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.reg_src = { .reg = S5P_CLK_SRC2, .shift = 4, .size = 2 },
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.reg_div = { .reg = S5P_CLK_DIV2, .shift = 4, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_g2d",
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.id = -1,
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.enable = s5pv210_clk_ip0_ctrl,
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.ctrlbit = (1 << 12),
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},
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.sources = &clkset_group1,
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.reg_src = { .reg = S5P_CLK_SRC2, .shift = 8, .size = 2 },
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.reg_div = { .reg = S5P_CLK_DIV2, .shift = 8, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_g3d",
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.id = -1,
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.enable = s5pv210_clk_ip0_ctrl,
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.ctrlbit = (1 << 8),
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},
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.sources = &clkset_group1,
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.reg_src = { .reg = S5P_CLK_SRC2, .shift = 0, .size = 2 },
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.reg_div = { .reg = S5P_CLK_DIV2, .shift = 0, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_csis",
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.id = -1,
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.enable = s5pv210_clk_ip0_ctrl,
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.ctrlbit = (1 << 31),
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P_CLK_SRC1, .shift = 24, .size = 4 },
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.reg_div = { .reg = S5P_CLK_DIV1, .shift = 28, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_spi",
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.id = 0,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1 << 12),
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P_CLK_SRC5, .shift = 0, .size = 4 },
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.reg_div = { .reg = S5P_CLK_DIV5, .shift = 0, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_spi",
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.id = 1,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1 << 13),
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P_CLK_SRC5, .shift = 4, .size = 4 },
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.reg_div = { .reg = S5P_CLK_DIV5, .shift = 4, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_pwi",
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.id = -1,
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.enable = &s5pv210_clk_ip4_ctrl,
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.ctrlbit = (1 << 2),
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P_CLK_SRC6, .shift = 20, .size = 4 },
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.reg_div = { .reg = S5P_CLK_DIV6, .shift = 24, .size = 4 },
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}, {
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.clk = {
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.name = "sclk_pwm",
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.id = -1,
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.enable = s5pv210_clk_ip3_ctrl,
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.ctrlbit = (1 << 23),
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},
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.sources = &clkset_group2,
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.reg_src = { .reg = S5P_CLK_SRC5, .shift = 12, .size = 4 },
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.reg_div = { .reg = S5P_CLK_DIV5, .shift = 12, .size = 4 },
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},
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};
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