drm/amd/powerplay: move functions to amd_pm_funcs table
those functions are exported to DC Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Rex Zhu
Alex Deucher
Родитель
2c2b67b479
Коммит
f685d71432
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@ -131,11 +131,12 @@ bool dm_pp_apply_display_requirements(
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adev->pm.pm_display_cfg.min_bus_bandwidth = 0;
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/* TODO: complete implementation of
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* amd_powerplay_display_configuration_change().
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* pp_display_configuration_change().
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* Follow example of:
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* PHM_StoreDALConfigurationData - powerplay\hwmgr\hardwaremanager.c
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* PP_IRI_DisplayConfigurationChange - powerplay\eventmgr\iri.c */
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amd_powerplay_display_configuration_change(
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if (adev->powerplay.pp_funcs->display_configuration_change)
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adev->powerplay.pp_funcs->display_configuration_change(
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adev->powerplay.pp_handle,
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&adev->pm.pm_display_cfg);
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@ -264,22 +265,26 @@ bool dm_pp_get_clock_levels_by_type(
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struct amd_pp_simple_clock_info validation_clks = { 0 };
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uint32_t i;
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if (amd_powerplay_get_clock_by_type(pp_handle,
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if (adev->powerplay.pp_funcs->get_clock_by_type) {
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if (adev->powerplay.pp_funcs->get_clock_by_type(pp_handle,
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dc_to_pp_clock_type(clk_type), &pp_clks)) {
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/* Error in pplib. Provide default values. */
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get_default_clock_levels(clk_type, dc_clks);
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return true;
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get_default_clock_levels(clk_type, dc_clks);
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return true;
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}
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}
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pp_to_dc_clock_levels(&pp_clks, dc_clks, clk_type);
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if (amd_powerplay_get_display_mode_validation_clocks(pp_handle,
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&validation_clks)) {
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/* Error in pplib. Provide default values. */
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DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n");
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validation_clks.engine_max_clock = 72000;
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validation_clks.memory_max_clock = 80000;
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validation_clks.level = 0;
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if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks) {
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if (adev->powerplay.pp_funcs->get_display_mode_validation_clocks(
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pp_handle, &validation_clks)) {
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/* Error in pplib. Provide default values. */
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DRM_INFO("DM_PPLIB: Warning: using default validation clocks!\n");
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validation_clks.engine_max_clock = 72000;
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validation_clks.memory_max_clock = 80000;
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validation_clks.level = 0;
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}
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}
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DRM_INFO("DM_PPLIB: Validation clocks:\n");
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@ -788,6 +788,26 @@ static int pp_dpm_get_pp_table(void *handle, char **table)
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return size;
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}
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static int amd_powerplay_reset(void *handle)
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{
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struct pp_instance *instance = (struct pp_instance *)handle;
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int ret;
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ret = pp_check(instance);
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if (ret)
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return ret;
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ret = pp_hw_fini(instance);
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if (ret)
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return ret;
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ret = hwmgr_hw_init(instance);
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if (ret)
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return ret;
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return hwmgr_handle_task(instance, AMD_PP_TASK_COMPLETE_INIT, NULL, NULL);
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}
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static int pp_dpm_set_pp_table(void *handle, const char *buf, size_t size)
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{
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struct pp_hwmgr *hwmgr;
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@ -1146,64 +1166,9 @@ static int pp_dpm_switch_power_profile(void *handle,
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return 0;
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}
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const struct amd_pm_funcs pp_dpm_funcs = {
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.get_temperature = pp_dpm_get_temperature,
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.load_firmware = pp_dpm_load_fw,
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.wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
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.force_performance_level = pp_dpm_force_performance_level,
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.get_performance_level = pp_dpm_get_performance_level,
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.get_current_power_state = pp_dpm_get_current_power_state,
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.get_sclk = pp_dpm_get_sclk,
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.get_mclk = pp_dpm_get_mclk,
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.powergate_vce = pp_dpm_powergate_vce,
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.powergate_uvd = pp_dpm_powergate_uvd,
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.dispatch_tasks = pp_dpm_dispatch_tasks,
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.set_fan_control_mode = pp_dpm_set_fan_control_mode,
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.get_fan_control_mode = pp_dpm_get_fan_control_mode,
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.set_fan_speed_percent = pp_dpm_set_fan_speed_percent,
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.get_fan_speed_percent = pp_dpm_get_fan_speed_percent,
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.get_fan_speed_rpm = pp_dpm_get_fan_speed_rpm,
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.get_pp_num_states = pp_dpm_get_pp_num_states,
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.get_pp_table = pp_dpm_get_pp_table,
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.set_pp_table = pp_dpm_set_pp_table,
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.force_clock_level = pp_dpm_force_clock_level,
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.print_clock_levels = pp_dpm_print_clock_levels,
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.get_sclk_od = pp_dpm_get_sclk_od,
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.set_sclk_od = pp_dpm_set_sclk_od,
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.get_mclk_od = pp_dpm_get_mclk_od,
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.set_mclk_od = pp_dpm_set_mclk_od,
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.read_sensor = pp_dpm_read_sensor,
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.get_vce_clock_state = pp_dpm_get_vce_clock_state,
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.reset_power_profile_state = pp_dpm_reset_power_profile_state,
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.get_power_profile_state = pp_dpm_get_power_profile_state,
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.set_power_profile_state = pp_dpm_set_power_profile_state,
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.switch_power_profile = pp_dpm_switch_power_profile,
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.set_clockgating_by_smu = pp_set_clockgating_by_smu,
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};
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int amd_powerplay_reset(void *handle)
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{
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struct pp_instance *instance = (struct pp_instance *)handle;
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int ret;
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ret = pp_check(instance);
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if (ret)
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return ret;
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ret = pp_hw_fini(instance);
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if (ret)
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return ret;
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ret = hwmgr_hw_init(instance);
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if (ret)
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return ret;
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return hwmgr_handle_task(instance, AMD_PP_TASK_COMPLETE_INIT, NULL, NULL);
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}
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/* export this function to DAL */
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int amd_powerplay_display_configuration_change(void *handle,
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static int pp_display_configuration_change(void *handle,
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const struct amd_pp_display_configuration *display_config)
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{
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struct pp_hwmgr *hwmgr;
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@ -1222,7 +1187,7 @@ int amd_powerplay_display_configuration_change(void *handle,
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return 0;
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}
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int amd_powerplay_get_display_power_level(void *handle,
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static int pp_get_display_power_level(void *handle,
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struct amd_pp_simple_clock_info *output)
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{
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struct pp_hwmgr *hwmgr;
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@ -1245,7 +1210,7 @@ int amd_powerplay_get_display_power_level(void *handle,
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return ret;
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}
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int amd_powerplay_get_current_clocks(void *handle,
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static int pp_get_current_clocks(void *handle,
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struct amd_pp_clock_info *clocks)
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{
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struct amd_pp_simple_clock_info simple_clocks;
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@ -1299,7 +1264,7 @@ int amd_powerplay_get_current_clocks(void *handle,
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return 0;
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}
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int amd_powerplay_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
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static int pp_get_clock_by_type(void *handle, enum amd_pp_clock_type type, struct amd_pp_clocks *clocks)
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{
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struct pp_hwmgr *hwmgr;
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struct pp_instance *pp_handle = (struct pp_instance *)handle;
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@ -1321,7 +1286,7 @@ int amd_powerplay_get_clock_by_type(void *handle, enum amd_pp_clock_type type, s
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return ret;
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}
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int amd_powerplay_get_clock_by_type_with_latency(void *handle,
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static int pp_get_clock_by_type_with_latency(void *handle,
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enum amd_pp_clock_type type,
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struct pp_clock_levels_with_latency *clocks)
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{
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@ -1343,7 +1308,7 @@ int amd_powerplay_get_clock_by_type_with_latency(void *handle,
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return ret;
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}
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int amd_powerplay_get_clock_by_type_with_voltage(void *handle,
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static int pp_get_clock_by_type_with_voltage(void *handle,
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enum amd_pp_clock_type type,
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struct pp_clock_levels_with_voltage *clocks)
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{
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@ -1368,7 +1333,7 @@ int amd_powerplay_get_clock_by_type_with_voltage(void *handle,
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return ret;
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}
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int amd_powerplay_set_watermarks_for_clocks_ranges(void *handle,
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static int pp_set_watermarks_for_clocks_ranges(void *handle,
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struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges)
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{
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struct pp_hwmgr *hwmgr;
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@ -1392,7 +1357,7 @@ int amd_powerplay_set_watermarks_for_clocks_ranges(void *handle,
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return ret;
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}
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int amd_powerplay_display_clock_voltage_request(void *handle,
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static int pp_display_clock_voltage_request(void *handle,
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struct pp_display_clock_request *clock)
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{
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struct pp_hwmgr *hwmgr;
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@ -1415,7 +1380,7 @@ int amd_powerplay_display_clock_voltage_request(void *handle,
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return ret;
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}
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int amd_powerplay_get_display_mode_validation_clocks(void *handle,
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static int pp_get_display_mode_validation_clocks(void *handle,
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struct amd_pp_simple_clock_info *clocks)
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{
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struct pp_hwmgr *hwmgr;
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@ -1441,3 +1406,47 @@ int amd_powerplay_get_display_mode_validation_clocks(void *handle,
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return ret;
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}
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const struct amd_pm_funcs pp_dpm_funcs = {
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.get_temperature = pp_dpm_get_temperature,
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.load_firmware = pp_dpm_load_fw,
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.wait_for_fw_loading_complete = pp_dpm_fw_loading_complete,
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.force_performance_level = pp_dpm_force_performance_level,
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.get_performance_level = pp_dpm_get_performance_level,
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.get_current_power_state = pp_dpm_get_current_power_state,
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.powergate_vce = pp_dpm_powergate_vce,
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.powergate_uvd = pp_dpm_powergate_uvd,
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.dispatch_tasks = pp_dpm_dispatch_tasks,
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.set_fan_control_mode = pp_dpm_set_fan_control_mode,
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.get_fan_control_mode = pp_dpm_get_fan_control_mode,
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.set_fan_speed_percent = pp_dpm_set_fan_speed_percent,
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.get_fan_speed_percent = pp_dpm_get_fan_speed_percent,
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.get_fan_speed_rpm = pp_dpm_get_fan_speed_rpm,
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.get_pp_num_states = pp_dpm_get_pp_num_states,
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.get_pp_table = pp_dpm_get_pp_table,
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.set_pp_table = pp_dpm_set_pp_table,
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.force_clock_level = pp_dpm_force_clock_level,
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.print_clock_levels = pp_dpm_print_clock_levels,
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.get_sclk_od = pp_dpm_get_sclk_od,
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.set_sclk_od = pp_dpm_set_sclk_od,
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.get_mclk_od = pp_dpm_get_mclk_od,
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.set_mclk_od = pp_dpm_set_mclk_od,
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.read_sensor = pp_dpm_read_sensor,
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.get_vce_clock_state = pp_dpm_get_vce_clock_state,
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.reset_power_profile_state = pp_dpm_reset_power_profile_state,
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.get_power_profile_state = pp_dpm_get_power_profile_state,
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.set_power_profile_state = pp_dpm_set_power_profile_state,
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.switch_power_profile = pp_dpm_switch_power_profile,
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.set_clockgating_by_smu = pp_set_clockgating_by_smu,
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/* export to DC */
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.get_sclk = pp_dpm_get_sclk,
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.get_mclk = pp_dpm_get_mclk,
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.display_configuration_change = pp_display_configuration_change,
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.get_display_power_level = pp_get_display_power_level,
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.get_current_clocks = pp_get_current_clocks,
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.get_clock_by_type = pp_get_clock_by_type,
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.get_clock_by_type_with_latency = pp_get_clock_by_type_with_latency,
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.get_clock_by_type_with_voltage = pp_get_clock_by_type_with_voltage,
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.set_watermarks_for_clocks_ranges = pp_set_watermarks_for_clocks_ranges,
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.display_clock_voltage_request = pp_display_clock_voltage_request,
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.get_display_mode_validation_clocks = pp_get_display_mode_validation_clocks,
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};
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@ -129,37 +129,5 @@ struct amd_powerplay {
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const struct amd_pm_funcs *pp_funcs;
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};
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int amd_powerplay_reset(void *handle);
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int amd_powerplay_display_configuration_change(void *handle,
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const struct amd_pp_display_configuration *input);
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int amd_powerplay_get_display_power_level(void *handle,
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struct amd_pp_simple_clock_info *output);
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int amd_powerplay_get_current_clocks(void *handle,
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struct amd_pp_clock_info *output);
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int amd_powerplay_get_clock_by_type(void *handle,
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enum amd_pp_clock_type type,
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struct amd_pp_clocks *clocks);
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int amd_powerplay_get_clock_by_type_with_latency(void *handle,
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enum amd_pp_clock_type type,
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struct pp_clock_levels_with_latency *clocks);
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int amd_powerplay_get_clock_by_type_with_voltage(void *handle,
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enum amd_pp_clock_type type,
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struct pp_clock_levels_with_voltage *clocks);
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int amd_powerplay_set_watermarks_for_clocks_ranges(void *handle,
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struct pp_wm_sets_with_clock_ranges_soc15 *wm_with_clock_ranges);
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int amd_powerplay_display_clock_voltage_request(void *handle,
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struct pp_display_clock_request *clock);
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int amd_powerplay_get_display_mode_validation_clocks(void *handle,
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struct amd_pp_simple_clock_info *output);
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#endif /* _AMD_POWERPLAY_H_ */
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