ARM: dts: am43xx: add support for parallel NAND flash
This patch:
- enables GPMC h/w and ELM h/w engine for AM43xx devices (am4372.dtsi)
- adds pinmux and DT node for Micron 4K-paged x8 NAND device (MT29F4G08AB)
present on following boards:
am43x-epos-evm:
On this board, NAND Flash control lines are muxed with QSPI, Thus only
one of the two can be used at a time. Selection is controlled by:
(a) dynamically driving following GPIO pin from software
GPMC_A0(GPIO) == 0 NAND is selected (default)
GPMC_A0(GPIO) == 1 eMMC is selected
Signed-off-by: Pekon Gupta <pekon@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Pekon Gupta
Tony Lindgren
Родитель
c06c527016
Коммит
f68e355c86
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@ -701,6 +701,30 @@
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<&edma 11>;
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dma-names = "tx", "rx";
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};
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elm: elm@48080000 {
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compatible = "ti,am3352-elm";
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reg = <0x48080000 0x2000>;
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interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
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ti,hwmods = "elm";
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clocks = <&l4ls_gclk>;
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clock-names = "fck";
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status = "disabled";
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};
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gpmc: gpmc@50000000 {
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compatible = "ti,am3352-gpmc";
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ti,hwmods = "gpmc";
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clocks = <&l3s_gclk>;
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clock-names = "fck";
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reg = <0x50000000 0x2000>;
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interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
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gpmc,num-cs = <7>;
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gpmc,num-waitpins = <2>;
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#address-cells = <2>;
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#size-cells = <1>;
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status = "disabled";
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};
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};
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};
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@ -79,6 +79,27 @@
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0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */
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>;
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};
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nand_flash_x8: nand_flash_x8 {
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pinctrl-single,pins = <
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0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */
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0x0 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */
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0x4 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */
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0x8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */
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0xc (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */
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0x10 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */
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0x14 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */
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0x18 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */
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0x1c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */
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0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */
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0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */
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0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */
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0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */
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0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */
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0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */
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0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */
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>;
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};
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};
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matrix_keypad: matrix_keypad@0 {
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@ -184,3 +205,89 @@
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&gpio3 {
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status = "okay";
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};
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&elm {
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status = "okay";
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};
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&gpmc {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&nand_flash_x8>;
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ranges = <0 0 0x08000000 0x10000000>; /* CS0: NAND */
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nand@0,0 {
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reg = <0 0 0>; /* CS0, offset 0 */
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ti,nand-ecc-opt = "bch8";
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ti,elm-id = <&elm>;
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nand-bus-width = <8>;
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gpmc,device-width = <1>;
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gpmc,sync-clk-ps = <0>;
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gpmc,cs-on-ns = <0>;
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gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */
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gpmc,cs-wr-off-ns = <40>;
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gpmc,adv-on-ns = <0>; /* cs-on-ns */
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gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */
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gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */
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gpmc,we-on-ns = <0>; /* cs-on-ns */
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gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */
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gpmc,oe-on-ns = <3>; /* cs-on-ns + tRR + 2 */
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gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */
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gpmc,access-ns = <30>; /* tCEA + 4*/
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gpmc,rd-cycle-ns = <40>;
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gpmc,wr-cycle-ns = <40>;
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gpmc,wait-on-read = "true";
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gpmc,wait-on-write = "true";
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gpmc,bus-turnaround-ns = <0>;
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gpmc,cycle2cycle-delay-ns = <0>;
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gpmc,clk-activation-ns = <0>;
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gpmc,wait-monitoring-ns = <0>;
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gpmc,wr-access-ns = <40>;
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gpmc,wr-data-mux-bus-ns = <0>;
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/* MTD partition table */
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/* All SPL-* partitions are sized to minimal length
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* which can be independently programmable. For
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* NAND flash this is equal to size of erase-block */
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "NAND.SPL";
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reg = <0x00000000 0x00040000>;
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};
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partition@1 {
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label = "NAND.SPL.backup1";
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reg = <0x00040000 0x00040000>;
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};
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partition@2 {
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label = "NAND.SPL.backup2";
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reg = <0x00080000 0x00040000>;
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};
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partition@3 {
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label = "NAND.SPL.backup3";
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reg = <0x000C0000 0x00040000>;
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};
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partition@4 {
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label = "NAND.u-boot-spl-os";
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reg = <0x00100000 0x00080000>;
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};
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partition@5 {
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label = "NAND.u-boot";
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reg = <0x00180000 0x00100000>;
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};
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partition@6 {
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label = "NAND.u-boot-env";
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reg = <0x00280000 0x00040000>;
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};
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partition@7 {
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label = "NAND.u-boot-env.backup1";
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reg = <0x002C0000 0x00040000>;
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};
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partition@8 {
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label = "NAND.kernel";
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reg = <0x00300000 0x00700000>;
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};
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partition@9 {
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label = "NAND.file-system";
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reg = <0x00800000 0x1F600000>;
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};
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};
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};
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