ioat: preserve chanctrl bits when re-arming interrupts
The register write in ioat_dma_cleanup_tasklet is unfortunate in two ways: 1/ It clears the extra 'enable' bits that we set at alloc_chan_resources time 2/ It gives the impression that it disables interrupts when it is in fact re-arming interrupts [ Impact: fix, persist the value of the chanctrl register when re-arming ] Signed-off-by: Maciej Sosnowski <maciej.sosnowski@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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Родитель
bb32078630
Коммит
f6ab95b557
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@ -452,7 +452,6 @@ static int ioat1_dma_alloc_chan_resources(struct dma_chan *c)
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struct ioat_dma_chan *ioat = to_ioat_chan(c);
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struct ioat_dma_chan *ioat = to_ioat_chan(c);
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struct ioat_chan_common *chan = &ioat->base;
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struct ioat_chan_common *chan = &ioat->base;
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struct ioat_desc_sw *desc;
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struct ioat_desc_sw *desc;
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u16 chanctrl;
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u32 chanerr;
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u32 chanerr;
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int i;
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int i;
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LIST_HEAD(tmp_list);
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LIST_HEAD(tmp_list);
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@ -462,10 +461,7 @@ static int ioat1_dma_alloc_chan_resources(struct dma_chan *c)
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return ioat->desccount;
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return ioat->desccount;
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/* Setup register to interrupt and write completion status on error */
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/* Setup register to interrupt and write completion status on error */
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chanctrl = IOAT_CHANCTRL_ERR_INT_EN |
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writew(IOAT_CHANCTRL_RUN, chan->reg_base + IOAT_CHANCTRL_OFFSET);
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IOAT_CHANCTRL_ANY_ERR_ABORT_EN |
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IOAT_CHANCTRL_ERR_COMPLETION_EN;
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writew(chanctrl, chan->reg_base + IOAT_CHANCTRL_OFFSET);
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chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
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chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
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if (chanerr) {
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if (chanerr) {
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@ -672,9 +668,9 @@ ioat1_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest,
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static void ioat1_cleanup_tasklet(unsigned long data)
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static void ioat1_cleanup_tasklet(unsigned long data)
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{
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{
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struct ioat_dma_chan *chan = (void *)data;
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struct ioat_dma_chan *chan = (void *)data;
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ioat1_cleanup(chan);
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ioat1_cleanup(chan);
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writew(IOAT_CHANCTRL_INT_DISABLE,
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writew(IOAT_CHANCTRL_RUN, chan->base.reg_base + IOAT_CHANCTRL_OFFSET);
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chan->base.reg_base + IOAT_CHANCTRL_OFFSET);
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}
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}
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static void ioat_unmap(struct pci_dev *pdev, dma_addr_t addr, size_t len,
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static void ioat_unmap(struct pci_dev *pdev, dma_addr_t addr, size_t len,
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@ -341,8 +341,7 @@ static void ioat2_cleanup_tasklet(unsigned long data)
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struct ioat2_dma_chan *ioat = (void *) data;
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struct ioat2_dma_chan *ioat = (void *) data;
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ioat2_cleanup(ioat);
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ioat2_cleanup(ioat);
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writew(IOAT_CHANCTRL_INT_DISABLE,
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writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET);
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ioat->base.reg_base + IOAT_CHANCTRL_OFFSET);
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}
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}
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/**
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/**
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@ -454,7 +453,6 @@ static int ioat2_alloc_chan_resources(struct dma_chan *c)
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struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
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struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
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struct ioat_chan_common *chan = &ioat->base;
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struct ioat_chan_common *chan = &ioat->base;
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struct ioat_ring_ent **ring;
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struct ioat_ring_ent **ring;
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u16 chanctrl;
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u32 chanerr;
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u32 chanerr;
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int descs;
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int descs;
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int i;
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int i;
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@ -464,9 +462,7 @@ static int ioat2_alloc_chan_resources(struct dma_chan *c)
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return 1 << ioat->alloc_order;
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return 1 << ioat->alloc_order;
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/* Setup register to interrupt and write completion status on error */
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/* Setup register to interrupt and write completion status on error */
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chanctrl = IOAT_CHANCTRL_ERR_INT_EN | IOAT_CHANCTRL_ANY_ERR_ABORT_EN |
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writew(IOAT_CHANCTRL_RUN, chan->reg_base + IOAT_CHANCTRL_OFFSET);
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IOAT_CHANCTRL_ERR_COMPLETION_EN;
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writew(chanctrl, chan->reg_base + IOAT_CHANCTRL_OFFSET);
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chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
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chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
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if (chanerr) {
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if (chanerr) {
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@ -75,7 +75,11 @@
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#define IOAT_CHANCTRL_ERR_INT_EN 0x0010
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#define IOAT_CHANCTRL_ERR_INT_EN 0x0010
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#define IOAT_CHANCTRL_ANY_ERR_ABORT_EN 0x0008
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#define IOAT_CHANCTRL_ANY_ERR_ABORT_EN 0x0008
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#define IOAT_CHANCTRL_ERR_COMPLETION_EN 0x0004
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#define IOAT_CHANCTRL_ERR_COMPLETION_EN 0x0004
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#define IOAT_CHANCTRL_INT_DISABLE 0x0001
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#define IOAT_CHANCTRL_INT_REARM 0x0001
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#define IOAT_CHANCTRL_RUN (IOAT_CHANCTRL_INT_REARM |\
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IOAT_CHANCTRL_ERR_COMPLETION_EN |\
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IOAT_CHANCTRL_ANY_ERR_ABORT_EN |\
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IOAT_CHANCTRL_ERR_INT_EN)
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#define IOAT_DMA_COMP_OFFSET 0x02 /* 16-bit DMA channel compatibility */
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#define IOAT_DMA_COMP_OFFSET 0x02 /* 16-bit DMA channel compatibility */
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#define IOAT_DMA_COMP_V1 0x0001 /* Compatibility with DMA version 1 */
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#define IOAT_DMA_COMP_V1 0x0001 /* Compatibility with DMA version 1 */
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