ioat: preserve chanctrl bits when re-arming interrupts

The register write in ioat_dma_cleanup_tasklet is unfortunate in two
ways:
1/ It clears the extra 'enable' bits that we set at alloc_chan_resources time
2/ It gives the impression that it disables interrupts when it is in
   fact re-arming interrupts

[ Impact: fix, persist the value of the chanctrl register when re-arming ]

Signed-off-by: Maciej Sosnowski <maciej.sosnowski@intel.com>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
This commit is contained in:
Dan Williams 2009-09-08 12:01:21 -07:00
Родитель bb32078630
Коммит f6ab95b557
3 изменённых файлов: 10 добавлений и 14 удалений

Просмотреть файл

@ -452,7 +452,6 @@ static int ioat1_dma_alloc_chan_resources(struct dma_chan *c)
struct ioat_dma_chan *ioat = to_ioat_chan(c); struct ioat_dma_chan *ioat = to_ioat_chan(c);
struct ioat_chan_common *chan = &ioat->base; struct ioat_chan_common *chan = &ioat->base;
struct ioat_desc_sw *desc; struct ioat_desc_sw *desc;
u16 chanctrl;
u32 chanerr; u32 chanerr;
int i; int i;
LIST_HEAD(tmp_list); LIST_HEAD(tmp_list);
@ -462,10 +461,7 @@ static int ioat1_dma_alloc_chan_resources(struct dma_chan *c)
return ioat->desccount; return ioat->desccount;
/* Setup register to interrupt and write completion status on error */ /* Setup register to interrupt and write completion status on error */
chanctrl = IOAT_CHANCTRL_ERR_INT_EN | writew(IOAT_CHANCTRL_RUN, chan->reg_base + IOAT_CHANCTRL_OFFSET);
IOAT_CHANCTRL_ANY_ERR_ABORT_EN |
IOAT_CHANCTRL_ERR_COMPLETION_EN;
writew(chanctrl, chan->reg_base + IOAT_CHANCTRL_OFFSET);
chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
if (chanerr) { if (chanerr) {
@ -672,9 +668,9 @@ ioat1_dma_prep_memcpy(struct dma_chan *c, dma_addr_t dma_dest,
static void ioat1_cleanup_tasklet(unsigned long data) static void ioat1_cleanup_tasklet(unsigned long data)
{ {
struct ioat_dma_chan *chan = (void *)data; struct ioat_dma_chan *chan = (void *)data;
ioat1_cleanup(chan); ioat1_cleanup(chan);
writew(IOAT_CHANCTRL_INT_DISABLE, writew(IOAT_CHANCTRL_RUN, chan->base.reg_base + IOAT_CHANCTRL_OFFSET);
chan->base.reg_base + IOAT_CHANCTRL_OFFSET);
} }
static void ioat_unmap(struct pci_dev *pdev, dma_addr_t addr, size_t len, static void ioat_unmap(struct pci_dev *pdev, dma_addr_t addr, size_t len,

Просмотреть файл

@ -341,8 +341,7 @@ static void ioat2_cleanup_tasklet(unsigned long data)
struct ioat2_dma_chan *ioat = (void *) data; struct ioat2_dma_chan *ioat = (void *) data;
ioat2_cleanup(ioat); ioat2_cleanup(ioat);
writew(IOAT_CHANCTRL_INT_DISABLE, writew(IOAT_CHANCTRL_RUN, ioat->base.reg_base + IOAT_CHANCTRL_OFFSET);
ioat->base.reg_base + IOAT_CHANCTRL_OFFSET);
} }
/** /**
@ -454,7 +453,6 @@ static int ioat2_alloc_chan_resources(struct dma_chan *c)
struct ioat2_dma_chan *ioat = to_ioat2_chan(c); struct ioat2_dma_chan *ioat = to_ioat2_chan(c);
struct ioat_chan_common *chan = &ioat->base; struct ioat_chan_common *chan = &ioat->base;
struct ioat_ring_ent **ring; struct ioat_ring_ent **ring;
u16 chanctrl;
u32 chanerr; u32 chanerr;
int descs; int descs;
int i; int i;
@ -464,9 +462,7 @@ static int ioat2_alloc_chan_resources(struct dma_chan *c)
return 1 << ioat->alloc_order; return 1 << ioat->alloc_order;
/* Setup register to interrupt and write completion status on error */ /* Setup register to interrupt and write completion status on error */
chanctrl = IOAT_CHANCTRL_ERR_INT_EN | IOAT_CHANCTRL_ANY_ERR_ABORT_EN | writew(IOAT_CHANCTRL_RUN, chan->reg_base + IOAT_CHANCTRL_OFFSET);
IOAT_CHANCTRL_ERR_COMPLETION_EN;
writew(chanctrl, chan->reg_base + IOAT_CHANCTRL_OFFSET);
chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET); chanerr = readl(chan->reg_base + IOAT_CHANERR_OFFSET);
if (chanerr) { if (chanerr) {

Просмотреть файл

@ -75,7 +75,11 @@
#define IOAT_CHANCTRL_ERR_INT_EN 0x0010 #define IOAT_CHANCTRL_ERR_INT_EN 0x0010
#define IOAT_CHANCTRL_ANY_ERR_ABORT_EN 0x0008 #define IOAT_CHANCTRL_ANY_ERR_ABORT_EN 0x0008
#define IOAT_CHANCTRL_ERR_COMPLETION_EN 0x0004 #define IOAT_CHANCTRL_ERR_COMPLETION_EN 0x0004
#define IOAT_CHANCTRL_INT_DISABLE 0x0001 #define IOAT_CHANCTRL_INT_REARM 0x0001
#define IOAT_CHANCTRL_RUN (IOAT_CHANCTRL_INT_REARM |\
IOAT_CHANCTRL_ERR_COMPLETION_EN |\
IOAT_CHANCTRL_ANY_ERR_ABORT_EN |\
IOAT_CHANCTRL_ERR_INT_EN)
#define IOAT_DMA_COMP_OFFSET 0x02 /* 16-bit DMA channel compatibility */ #define IOAT_DMA_COMP_OFFSET 0x02 /* 16-bit DMA channel compatibility */
#define IOAT_DMA_COMP_V1 0x0001 /* Compatibility with DMA version 1 */ #define IOAT_DMA_COMP_V1 0x0001 /* Compatibility with DMA version 1 */