drm/amd/powerplay: correct the APIs' naming
'UVD' is a HW engine name for Vega20 and before ASICs. For newer ASICs, the similar engine is named as 'VCN'. Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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f6b4b4a1db
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@ -455,10 +455,15 @@ int smu_dpm_set_power_gate(struct smu_context *smu, uint32_t block_type,
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return -EOPNOTSUPP;
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switch (block_type) {
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/*
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* Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses
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* AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept.
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*/
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case AMD_IP_BLOCK_TYPE_UVD:
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ret = smu_dpm_set_uvd_enable(smu, !gate);
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case AMD_IP_BLOCK_TYPE_VCN:
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ret = smu_dpm_set_vcn_enable(smu, !gate);
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if (ret)
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dev_err(smu->adev->dev, "Failed to power %s UVD!\n",
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dev_err(smu->adev->dev, "Failed to power %s VCN!\n",
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gate ? "gate" : "ungate");
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break;
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case AMD_IP_BLOCK_TYPE_GFX:
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@ -1328,7 +1333,7 @@ static int smu_hw_init(void *handle)
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if (smu->is_apu) {
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smu_powergate_sdma(&adev->smu, false);
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smu_dpm_set_uvd_enable(smu, true);
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smu_dpm_set_vcn_enable(smu, true);
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smu_dpm_set_jpeg_enable(smu, true);
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smu_set_gfx_cgpg(&adev->smu, true);
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}
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@ -1460,7 +1465,7 @@ static int smu_hw_fini(void *handle)
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if (smu->is_apu) {
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smu_powergate_sdma(&adev->smu, true);
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smu_dpm_set_uvd_enable(smu, false);
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smu_dpm_set_vcn_enable(smu, false);
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smu_dpm_set_jpeg_enable(smu, false);
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}
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@ -2118,7 +2118,7 @@ static bool arcturus_is_dpm_running(struct smu_context *smu)
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return !!(feature_enabled & SMC_DPM_FEATURE);
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}
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static int arcturus_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
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static int arcturus_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
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{
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struct smu_power_context *smu_power = &smu->smu_power;
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struct smu_power_gate *power_gate = &smu_power->power_gate;
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@ -2617,7 +2617,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
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.dump_pptable = arcturus_dump_pptable,
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.get_power_limit = arcturus_get_power_limit,
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.is_dpm_running = arcturus_is_dpm_running,
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.dpm_set_uvd_enable = arcturus_dpm_set_uvd_enable,
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.dpm_set_vcn_enable = arcturus_dpm_set_vcn_enable,
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.i2c_eeprom_init = arcturus_i2c_eeprom_control_init,
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.i2c_eeprom_fini = arcturus_i2c_eeprom_control_fini,
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.get_unique_id = arcturus_get_unique_id,
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@ -453,7 +453,7 @@ struct pptable_funcs {
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*clocks);
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int (*get_power_profile_mode)(struct smu_context *smu, char *buf);
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int (*set_power_profile_mode)(struct smu_context *smu, long *input, uint32_t size);
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int (*dpm_set_uvd_enable)(struct smu_context *smu, bool enable);
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int (*dpm_set_vcn_enable)(struct smu_context *smu, bool enable);
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int (*dpm_set_jpeg_enable)(struct smu_context *smu, bool enable);
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int (*read_sensor)(struct smu_context *smu, enum amd_pp_sensors sensor,
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void *data, uint32_t *size);
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@ -729,7 +729,7 @@ static int navi10_set_default_dpm_table(struct smu_context *smu)
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return 0;
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}
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static int navi10_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
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static int navi10_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
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{
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struct smu_power_context *smu_power = &smu->smu_power;
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struct smu_power_gate *power_gate = &smu_power->power_gate;
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@ -2429,7 +2429,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
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.get_workload_type = navi10_get_workload_type,
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.get_allowed_feature_mask = navi10_get_allowed_feature_mask,
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.set_default_dpm_table = navi10_set_default_dpm_table,
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.dpm_set_uvd_enable = navi10_dpm_set_uvd_enable,
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.dpm_set_vcn_enable = navi10_dpm_set_vcn_enable,
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.dpm_set_jpeg_enable = navi10_dpm_set_jpeg_enable,
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.get_current_clk_freq_by_table = navi10_get_current_clk_freq_by_table,
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.print_clk_levels = navi10_print_clk_levels,
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@ -349,7 +349,7 @@ static enum amd_pm_state_type renoir_get_current_power_state(struct smu_context
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return pm_type;
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}
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static int renoir_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
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static int renoir_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
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{
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struct smu_power_context *smu_power = &smu->smu_power;
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struct smu_power_gate *power_gate = &smu_power->power_gate;
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@ -929,7 +929,7 @@ static const struct pptable_funcs renoir_ppt_funcs = {
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.get_dpm_clk_limited = renoir_get_dpm_clk_limited,
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.print_clk_levels = renoir_print_clk_levels,
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.get_current_power_state = renoir_get_current_power_state,
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.dpm_set_uvd_enable = renoir_dpm_set_uvd_enable,
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.dpm_set_vcn_enable = renoir_dpm_set_vcn_enable,
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.dpm_set_jpeg_enable = renoir_dpm_set_jpeg_enable,
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.get_current_clk_freq_by_table = renoir_get_current_clk_freq_by_table,
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.force_dpm_limit_value = renoir_force_dpm_limit_value,
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@ -722,7 +722,7 @@ static int sienna_cichlid_set_default_dpm_table(struct smu_context *smu)
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return 0;
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}
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static int sienna_cichlid_dpm_set_uvd_enable(struct smu_context *smu, bool enable)
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static int sienna_cichlid_dpm_set_vcn_enable(struct smu_context *smu, bool enable)
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{
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struct smu_power_context *smu_power = &smu->smu_power;
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struct smu_power_gate *power_gate = &smu_power->power_gate;
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@ -2602,7 +2602,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
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.get_workload_type = sienna_cichlid_get_workload_type,
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.get_allowed_feature_mask = sienna_cichlid_get_allowed_feature_mask,
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.set_default_dpm_table = sienna_cichlid_set_default_dpm_table,
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.dpm_set_uvd_enable = sienna_cichlid_dpm_set_uvd_enable,
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.dpm_set_vcn_enable = sienna_cichlid_dpm_set_vcn_enable,
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.dpm_set_jpeg_enable = sienna_cichlid_dpm_set_jpeg_enable,
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.get_current_clk_freq_by_table = sienna_cichlid_get_current_clk_freq_by_table,
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.print_clk_levels = sienna_cichlid_print_clk_levels,
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@ -157,8 +157,8 @@ static inline int smu_send_smc_msg(struct smu_context *smu, enum smu_message_typ
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#define smu_get_current_shallow_sleep_clocks(smu, clocks) \
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((smu)->ppt_funcs->get_current_shallow_sleep_clocks ? (smu)->ppt_funcs->get_current_shallow_sleep_clocks((smu), (clocks)) : 0)
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#define smu_dpm_set_uvd_enable(smu, enable) \
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((smu)->ppt_funcs->dpm_set_uvd_enable ? (smu)->ppt_funcs->dpm_set_uvd_enable((smu), (enable)) : 0)
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#define smu_dpm_set_vcn_enable(smu, enable) \
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((smu)->ppt_funcs->dpm_set_vcn_enable ? (smu)->ppt_funcs->dpm_set_vcn_enable((smu), (enable)) : 0)
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#define smu_dpm_set_jpeg_enable(smu, enable) \
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((smu)->ppt_funcs->dpm_set_jpeg_enable ? (smu)->ppt_funcs->dpm_set_jpeg_enable((smu), (enable)) : 0)
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