- Remove arch_timer_rate1 variable as it is unused in the architected
ARM timer (Jisheng Zhang) - Minor cleanups (whitespace, constification, ...) for the Samsung pwm timer (Krzysztof Kozlowski) - Acknowledge and disable the timer interrupt at suspend time to prevent the suspend to be aborted by the ATF if there is a pending one on the Mediatek timer (Evan Benn) - Save and restore the configuration register at suspend/resume time for TI dm timer (Tony Lindgren) - Set the scene for the next timers support by renaming the array variables on the Ingenic time (Zhou Yanjie) - Add the clock rate change notification to adjust the prescalar value and compensate the clock source on the ARM global timer (Andrea Merello) - Add missing variable static annotation on the ARM global timer (Zou Wei) - Remove a duplicate argument when building the bits field on the ARM global timer (Wan Jiabing) - Improve the timer workaround function by reducing the loop on the Allwinner A64 timer (Samuel Holland) - Do no restore the register context in case of error on the TI dm timer (Tony Lindgren) -----BEGIN PGP SIGNATURE----- iQEzBAABCAAdFiEEGn3N4YVz0WNVyHskqDIjiipP6E8FAmDKNmQACgkQqDIjiipP 6E9iAAf+Jbh1rIdxRBFYvJz7R78/AR8H4JTPNXdyrHGkPa4Dx/1tuYJRVsLzLELk 28yWRjU/rl0lBzZjoUmszsYuyTXghjqEdTMU8KYkU5/9n8LfGXuA5d0y1qulYh6a UoK0RNiVzgDs49v7gj5khDBQQDCDf8RVdgaUyNiE7ciXsBxE6jir3UMiUT5fvVwW 0utGbXLUEr/FpVXOb/9XBem6BUGAWvkNM2566qXgVRp7t+Y0py75GZklLrJ3/3lI +UI6uAQrBwOr54kqKp5/+GMuRIXtnGy4jud391X9rbIwr/tPgnGJXwlqg+Ups7x5 ICCU42f5JX9ukKBT+XwoXcp3sk91OA== =XeyC -----END PGP SIGNATURE----- Merge tag 'timers-v5.14' of https://git.linaro.org/people/daniel.lezcano/linux into timers/core Pull clockevent/source updates from Daniel Lezcano: - Remove arch_timer_rate1 variable as it is unused in the architected ARM timer (Jisheng Zhang) - Minor cleanups (whitespace, constification, ...) for the Samsung pwm timer (Krzysztof Kozlowski) - Acknowledge and disable the timer interrupt at suspend time to prevent the suspend to be aborted by the ATF if there is a pending one on the Mediatek timer (Evan Benn) - Save and restore the configuration register at suspend/resume time for TI dm timer (Tony Lindgren) - Set the scene for the next timers support by renaming the array variables on the Ingenic time (Zhou Yanjie) - Add the clock rate change notification to adjust the prescalar value and compensate the clock source on the ARM global timer (Andrea Merello) - Add missing variable static annotation on the ARM global timer (Zou Wei) - Remove a duplicate argument when building the bits field on the ARM global timer (Wan Jiabing) - Improve the timer workaround function by reducing the loop on the Allwinner A64 timer (Samuel Holland) - Do no restore the register context in case of error on the TI dm timer (Tony Lindgren) Link: https://lore.kernel.org/r/65ed5f60-d7a5-b4ae-ff78-0382d4671cc5@linaro.org
This commit is contained in:
Thomas Gleixner
Коммит
f6b6a80360
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|
@ -6,7 +6,7 @@ config ARCH_ZYNQ
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select ARCH_SUPPORTS_BIG_ENDIAN
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select ARM_AMBA
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select ARM_GIC
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select ARM_GLOBAL_TIMER if !CPU_FREQ
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select ARM_GLOBAL_TIMER
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select CADENCE_TTC_TIMER
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select HAVE_ARM_SCU if SMP
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select HAVE_ARM_TWD if SMP
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|
|
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@ -358,6 +358,20 @@ config ARM_GLOBAL_TIMER
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help
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This option enables support for the ARM global timer unit.
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config ARM_GT_INITIAL_PRESCALER_VAL
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int "ARM global timer initial prescaler value"
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default 2 if ARCH_ZYNQ
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default 1
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depends on ARM_GLOBAL_TIMER
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help
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When the ARM global timer initializes, its current rate is declared
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to the kernel and maintained forever. Should it's parent clock
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change, the driver tries to fix the timer's internal prescaler.
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On some machs (i.e. Zynq) the initial prescaler value thus poses
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bounds about how much the parent clock is allowed to decrease or
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increase wrt the initial clock value.
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This affects CPU_FREQ max delta from the initial frequency.
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config ARM_TIMER_SP804
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bool "Support for Dual Timer SP804 module" if COMPILE_TEST
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depends on GENERIC_SCHED_CLOCK && CLKDEV_LOOKUP
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|
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@ -64,7 +64,6 @@ struct arch_timer {
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#define to_arch_timer(e) container_of(e, struct arch_timer, evt)
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static u32 arch_timer_rate __ro_after_init;
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u32 arch_timer_rate1 __ro_after_init;
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static int arch_timer_ppi[ARCH_TIMER_MAX_TIMER_PPI] __ro_after_init;
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static const char *arch_timer_ppi_names[ARCH_TIMER_MAX_TIMER_PPI] = {
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|
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@ -365,7 +364,7 @@ static u64 notrace arm64_858921_read_cntvct_el0(void)
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do { \
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_val = read_sysreg(reg); \
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_retries--; \
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} while (((_val + 1) & GENMASK(9, 0)) <= 1 && _retries); \
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} while (((_val + 1) & GENMASK(8, 0)) <= 1 && _retries); \
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\
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WARN_ON_ONCE(!_retries); \
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_val; \
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|
|
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@ -31,6 +31,10 @@
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#define GT_CONTROL_COMP_ENABLE BIT(1) /* banked */
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#define GT_CONTROL_IRQ_ENABLE BIT(2) /* banked */
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#define GT_CONTROL_AUTO_INC BIT(3) /* banked */
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#define GT_CONTROL_PRESCALER_SHIFT 8
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#define GT_CONTROL_PRESCALER_MAX 0xF
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#define GT_CONTROL_PRESCALER_MASK (GT_CONTROL_PRESCALER_MAX << \
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GT_CONTROL_PRESCALER_SHIFT)
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#define GT_INT_STATUS 0x0c
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#define GT_INT_STATUS_EVENT_FLAG BIT(0)
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@ -39,6 +43,7 @@
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#define GT_COMP1 0x14
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#define GT_AUTO_INC 0x18
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#define MAX_F_ERR 50
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/*
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* We are expecting to be clocked by the ARM peripheral clock.
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*
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@ -46,7 +51,8 @@
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* the units for all operations.
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*/
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static void __iomem *gt_base;
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static unsigned long gt_clk_rate;
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static struct notifier_block gt_clk_rate_change_nb;
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static u32 gt_psv_new, gt_psv_bck, gt_target_rate;
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static int gt_ppi;
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static struct clock_event_device __percpu *gt_evt;
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@ -96,7 +102,10 @@ static void gt_compare_set(unsigned long delta, int periodic)
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unsigned long ctrl;
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counter += delta;
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ctrl = GT_CONTROL_TIMER_ENABLE;
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ctrl = readl(gt_base + GT_CONTROL);
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ctrl &= ~(GT_CONTROL_COMP_ENABLE | GT_CONTROL_IRQ_ENABLE |
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GT_CONTROL_AUTO_INC);
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ctrl |= GT_CONTROL_TIMER_ENABLE;
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writel_relaxed(ctrl, gt_base + GT_CONTROL);
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writel_relaxed(lower_32_bits(counter), gt_base + GT_COMP0);
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writel_relaxed(upper_32_bits(counter), gt_base + GT_COMP1);
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|
@ -123,7 +132,7 @@ static int gt_clockevent_shutdown(struct clock_event_device *evt)
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static int gt_clockevent_set_periodic(struct clock_event_device *evt)
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{
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gt_compare_set(DIV_ROUND_CLOSEST(gt_clk_rate, HZ), 1);
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gt_compare_set(DIV_ROUND_CLOSEST(gt_target_rate, HZ), 1);
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return 0;
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}
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@ -177,7 +186,7 @@ static int gt_starting_cpu(unsigned int cpu)
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clk->cpumask = cpumask_of(cpu);
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clk->rating = 300;
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clk->irq = gt_ppi;
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clockevents_config_and_register(clk, gt_clk_rate,
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clockevents_config_and_register(clk, gt_target_rate,
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1, 0xffffffff);
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enable_percpu_irq(clk->irq, IRQ_TYPE_NONE);
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return 0;
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|
|
@ -232,9 +241,28 @@ static struct delay_timer gt_delay_timer = {
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.read_current_timer = gt_read_long,
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};
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static void gt_write_presc(u32 psv)
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{
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u32 reg;
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reg = readl(gt_base + GT_CONTROL);
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reg &= ~GT_CONTROL_PRESCALER_MASK;
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reg |= psv << GT_CONTROL_PRESCALER_SHIFT;
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writel(reg, gt_base + GT_CONTROL);
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}
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static u32 gt_read_presc(void)
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{
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u32 reg;
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reg = readl(gt_base + GT_CONTROL);
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reg &= GT_CONTROL_PRESCALER_MASK;
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return reg >> GT_CONTROL_PRESCALER_SHIFT;
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}
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static void __init gt_delay_timer_init(void)
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{
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gt_delay_timer.freq = gt_clk_rate;
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gt_delay_timer.freq = gt_target_rate;
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register_current_timer_delay(>_delay_timer);
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}
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@ -243,18 +271,81 @@ static int __init gt_clocksource_init(void)
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writel(0, gt_base + GT_CONTROL);
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writel(0, gt_base + GT_COUNTER0);
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writel(0, gt_base + GT_COUNTER1);
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/* enables timer on all the cores */
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writel(GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
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/* set prescaler and enable timer on all the cores */
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writel(((CONFIG_ARM_GT_INITIAL_PRESCALER_VAL - 1) <<
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GT_CONTROL_PRESCALER_SHIFT)
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| GT_CONTROL_TIMER_ENABLE, gt_base + GT_CONTROL);
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#ifdef CONFIG_CLKSRC_ARM_GLOBAL_TIMER_SCHED_CLOCK
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sched_clock_register(gt_sched_clock_read, 64, gt_clk_rate);
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sched_clock_register(gt_sched_clock_read, 64, gt_target_rate);
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#endif
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return clocksource_register_hz(>_clocksource, gt_clk_rate);
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return clocksource_register_hz(>_clocksource, gt_target_rate);
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}
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static int gt_clk_rate_change_cb(struct notifier_block *nb,
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unsigned long event, void *data)
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{
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struct clk_notifier_data *ndata = data;
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switch (event) {
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case PRE_RATE_CHANGE:
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{
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int psv;
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psv = DIV_ROUND_CLOSEST(ndata->new_rate,
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gt_target_rate);
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if (abs(gt_target_rate - (ndata->new_rate / psv)) > MAX_F_ERR)
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return NOTIFY_BAD;
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psv--;
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/* prescaler within legal range? */
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if (psv < 0 || psv > GT_CONTROL_PRESCALER_MAX)
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return NOTIFY_BAD;
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/*
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* store timer clock ctrl register so we can restore it in case
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* of an abort.
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*/
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gt_psv_bck = gt_read_presc();
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gt_psv_new = psv;
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/* scale down: adjust divider in post-change notification */
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if (ndata->new_rate < ndata->old_rate)
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return NOTIFY_DONE;
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/* scale up: adjust divider now - before frequency change */
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gt_write_presc(psv);
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break;
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}
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case POST_RATE_CHANGE:
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/* scale up: pre-change notification did the adjustment */
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if (ndata->new_rate > ndata->old_rate)
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return NOTIFY_OK;
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/* scale down: adjust divider now - after frequency change */
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gt_write_presc(gt_psv_new);
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break;
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case ABORT_RATE_CHANGE:
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/* we have to undo the adjustment in case we scale up */
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if (ndata->new_rate < ndata->old_rate)
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return NOTIFY_OK;
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/* restore original register value */
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gt_write_presc(gt_psv_bck);
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break;
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default:
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return NOTIFY_DONE;
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}
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return NOTIFY_DONE;
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}
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static int __init global_timer_of_register(struct device_node *np)
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{
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struct clk *gt_clk;
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static unsigned long gt_clk_rate;
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int err = 0;
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/*
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|
|
@ -292,11 +383,20 @@ static int __init global_timer_of_register(struct device_node *np)
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}
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gt_clk_rate = clk_get_rate(gt_clk);
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gt_target_rate = gt_clk_rate / CONFIG_ARM_GT_INITIAL_PRESCALER_VAL;
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gt_clk_rate_change_nb.notifier_call =
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gt_clk_rate_change_cb;
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err = clk_notifier_register(gt_clk, >_clk_rate_change_nb);
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if (err) {
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pr_warn("Unable to register clock notifier\n");
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goto out_clk;
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}
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|
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gt_evt = alloc_percpu(struct clock_event_device);
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if (!gt_evt) {
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pr_warn("global-timer: can't allocate memory\n");
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err = -ENOMEM;
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goto out_clk;
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goto out_clk_nb;
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}
|
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|
||||
err = request_percpu_irq(gt_ppi, gt_clockevent_interrupt,
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|
|
@ -326,6 +426,8 @@ out_irq:
|
|||
free_percpu_irq(gt_ppi, gt_evt);
|
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out_free:
|
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free_percpu(gt_evt);
|
||||
out_clk_nb:
|
||||
clk_notifier_unregister(gt_clk, >_clk_rate_change_nb);
|
||||
out_clk:
|
||||
clk_disable_unprepare(gt_clk);
|
||||
out_unmap:
|
||||
|
|
|
|||
|
|
@ -186,7 +186,7 @@ static const struct clk_ops ingenic_ost_global_timer_ops = {
|
|||
|
||||
static const char * const ingenic_ost_clk_parents[] = { "ext" };
|
||||
|
||||
static const struct ingenic_ost_clk_info ingenic_ost_clk_info[] = {
|
||||
static const struct ingenic_ost_clk_info x1000_ost_clk_info[] = {
|
||||
[OST_CLK_PERCPU_TIMER] = {
|
||||
.init_data = {
|
||||
.name = "percpu timer",
|
||||
|
|
@ -414,14 +414,14 @@ static const struct ingenic_soc_info x1000_soc_info = {
|
|||
.num_channels = 2,
|
||||
};
|
||||
|
||||
static const struct of_device_id __maybe_unused ingenic_ost_of_match[] __initconst = {
|
||||
{ .compatible = "ingenic,x1000-ost", .data = &x1000_soc_info, },
|
||||
static const struct of_device_id __maybe_unused ingenic_ost_of_matches[] __initconst = {
|
||||
{ .compatible = "ingenic,x1000-ost", .data = &x1000_soc_info },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
|
||||
static int __init ingenic_ost_probe(struct device_node *np)
|
||||
{
|
||||
const struct of_device_id *id = of_match_node(ingenic_ost_of_match, np);
|
||||
const struct of_device_id *id = of_match_node(ingenic_ost_of_matches, np);
|
||||
struct ingenic_ost *ost;
|
||||
unsigned int i;
|
||||
int ret;
|
||||
|
|
@ -462,7 +462,7 @@ static int __init ingenic_ost_probe(struct device_node *np)
|
|||
ost->clocks->num = ost->soc_info->num_channels;
|
||||
|
||||
for (i = 0; i < ost->clocks->num; i++) {
|
||||
ret = ingenic_ost_register_clock(ost, i, &ingenic_ost_clk_info[i], ost->clocks);
|
||||
ret = ingenic_ost_register_clock(ost, i, &x1000_ost_clk_info[i], ost->clocks);
|
||||
if (ret) {
|
||||
pr_crit("%s: Cannot register clock %d\n", __func__, i);
|
||||
goto err_unregister_ost_clocks;
|
||||
|
|
|
|||
|
|
@ -4,7 +4,7 @@
|
|||
* http://www.samsung.com/
|
||||
*
|
||||
* samsung - Common hr-timer support (s3c and s5p)
|
||||
*/
|
||||
*/
|
||||
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/irq.h>
|
||||
|
|
@ -22,7 +22,6 @@
|
|||
|
||||
#include <clocksource/samsung_pwm.h>
|
||||
|
||||
|
||||
/*
|
||||
* Clocksource driver
|
||||
*/
|
||||
|
|
@ -38,8 +37,8 @@
|
|||
#define TCFG0_PRESCALER_MASK 0xff
|
||||
#define TCFG0_PRESCALER1_SHIFT 8
|
||||
|
||||
#define TCFG1_SHIFT(x) ((x) * 4)
|
||||
#define TCFG1_MUX_MASK 0xf
|
||||
#define TCFG1_SHIFT(x) ((x) * 4)
|
||||
#define TCFG1_MUX_MASK 0xf
|
||||
|
||||
/*
|
||||
* Each channel occupies 4 bits in TCON register, but there is a gap of 4
|
||||
|
|
@ -62,7 +61,7 @@ EXPORT_SYMBOL(samsung_pwm_lock);
|
|||
|
||||
struct samsung_pwm_clocksource {
|
||||
void __iomem *base;
|
||||
void __iomem *source_reg;
|
||||
const void __iomem *source_reg;
|
||||
unsigned int irq[SAMSUNG_PWM_NUM];
|
||||
struct samsung_pwm_variant variant;
|
||||
|
||||
|
|
@ -183,7 +182,7 @@ static void samsung_time_start(unsigned int channel, bool periodic)
|
|||
}
|
||||
|
||||
static int samsung_set_next_event(unsigned long cycles,
|
||||
struct clock_event_device *evt)
|
||||
struct clock_event_device *evt)
|
||||
{
|
||||
/*
|
||||
* This check is needed to account for internal rounding
|
||||
|
|
@ -225,6 +224,7 @@ static void samsung_clockevent_resume(struct clock_event_device *cev)
|
|||
|
||||
if (pwm.variant.has_tint_cstat) {
|
||||
u32 mask = (1 << pwm.event_id);
|
||||
|
||||
writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
|
||||
}
|
||||
}
|
||||
|
|
@ -248,6 +248,7 @@ static irqreturn_t samsung_clock_event_isr(int irq, void *dev_id)
|
|||
|
||||
if (pwm.variant.has_tint_cstat) {
|
||||
u32 mask = (1 << pwm.event_id);
|
||||
|
||||
writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
|
||||
}
|
||||
|
||||
|
|
@ -272,7 +273,7 @@ static void __init samsung_clockevent_init(void)
|
|||
|
||||
time_event_device.cpumask = cpumask_of(0);
|
||||
clockevents_config_and_register(&time_event_device,
|
||||
clock_rate, 1, pwm.tcnt_max);
|
||||
clock_rate, 1, pwm.tcnt_max);
|
||||
|
||||
irq_number = pwm.irq[pwm.event_id];
|
||||
if (request_irq(irq_number, samsung_clock_event_isr,
|
||||
|
|
@ -282,6 +283,7 @@ static void __init samsung_clockevent_init(void)
|
|||
|
||||
if (pwm.variant.has_tint_cstat) {
|
||||
u32 mask = (1 << pwm.event_id);
|
||||
|
||||
writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
|
||||
}
|
||||
}
|
||||
|
|
@ -347,7 +349,7 @@ static int __init samsung_clocksource_init(void)
|
|||
pwm.source_reg = pwm.base + pwm.source_id * 0x0c + 0x14;
|
||||
|
||||
sched_clock_register(samsung_read_sched_clock,
|
||||
pwm.variant.bits, clock_rate);
|
||||
pwm.variant.bits, clock_rate);
|
||||
|
||||
samsung_clocksource.mask = CLOCKSOURCE_MASK(pwm.variant.bits);
|
||||
return clocksource_register_hz(&samsung_clocksource, clock_rate);
|
||||
|
|
@ -398,7 +400,8 @@ static int __init _samsung_pwm_clocksource_init(void)
|
|||
}
|
||||
|
||||
void __init samsung_pwm_clocksource_init(void __iomem *base,
|
||||
unsigned int *irqs, struct samsung_pwm_variant *variant)
|
||||
unsigned int *irqs,
|
||||
const struct samsung_pwm_variant *variant)
|
||||
{
|
||||
pwm.base = base;
|
||||
memcpy(&pwm.variant, variant, sizeof(pwm.variant));
|
||||
|
|
@ -418,7 +421,7 @@ static int __init samsung_pwm_alloc(struct device_node *np,
|
|||
struct property *prop;
|
||||
const __be32 *cur;
|
||||
u32 val;
|
||||
int i;
|
||||
int i, ret;
|
||||
|
||||
memcpy(&pwm.variant, variant, sizeof(pwm.variant));
|
||||
for (i = 0; i < SAMSUNG_PWM_NUM; ++i)
|
||||
|
|
@ -441,10 +444,24 @@ static int __init samsung_pwm_alloc(struct device_node *np,
|
|||
pwm.timerclk = of_clk_get_by_name(np, "timers");
|
||||
if (IS_ERR(pwm.timerclk)) {
|
||||
pr_crit("failed to get timers clock for timer\n");
|
||||
return PTR_ERR(pwm.timerclk);
|
||||
ret = PTR_ERR(pwm.timerclk);
|
||||
goto err_clk;
|
||||
}
|
||||
|
||||
return _samsung_pwm_clocksource_init();
|
||||
ret = _samsung_pwm_clocksource_init();
|
||||
if (ret)
|
||||
goto err_clocksource;
|
||||
|
||||
return 0;
|
||||
|
||||
err_clocksource:
|
||||
clk_put(pwm.timerclk);
|
||||
pwm.timerclk = NULL;
|
||||
err_clk:
|
||||
iounmap(pwm.base);
|
||||
pwm.base = NULL;
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct samsung_pwm_variant s3c24xx_variant = {
|
||||
|
|
|
|||
|
|
@ -241,6 +241,28 @@ static void mtk_gpt_enable_irq(struct timer_of *to, u8 timer)
|
|||
timer_of_base(to) + GPT_IRQ_EN_REG);
|
||||
}
|
||||
|
||||
static void mtk_gpt_resume(struct clock_event_device *clk)
|
||||
{
|
||||
struct timer_of *to = to_timer_of(clk);
|
||||
|
||||
mtk_gpt_enable_irq(to, TIMER_CLK_EVT);
|
||||
}
|
||||
|
||||
static void mtk_gpt_suspend(struct clock_event_device *clk)
|
||||
{
|
||||
struct timer_of *to = to_timer_of(clk);
|
||||
|
||||
/* Disable all interrupts */
|
||||
writel(0x0, timer_of_base(to) + GPT_IRQ_EN_REG);
|
||||
|
||||
/*
|
||||
* This is called with interrupts disabled,
|
||||
* so we need to ack any interrupt that is pending
|
||||
* or for example ATF will prevent a suspend from completing.
|
||||
*/
|
||||
writel(0x3f, timer_of_base(to) + GPT_IRQ_ACK_REG);
|
||||
}
|
||||
|
||||
static struct timer_of to = {
|
||||
.flags = TIMER_OF_IRQ | TIMER_OF_BASE | TIMER_OF_CLOCK,
|
||||
|
||||
|
|
@ -286,6 +308,8 @@ static int __init mtk_gpt_init(struct device_node *node)
|
|||
to.clkevt.set_state_oneshot = mtk_gpt_clkevt_shutdown;
|
||||
to.clkevt.tick_resume = mtk_gpt_clkevt_shutdown;
|
||||
to.clkevt.set_next_event = mtk_gpt_clkevt_next_event;
|
||||
to.clkevt.suspend = mtk_gpt_suspend;
|
||||
to.clkevt.resume = mtk_gpt_resume;
|
||||
to.of_irq.handler = mtk_gpt_interrupt;
|
||||
|
||||
ret = timer_of_init(node, &to);
|
||||
|
|
|
|||
|
|
@ -78,6 +78,9 @@ static void omap_dm_timer_write_reg(struct omap_dm_timer *timer, u32 reg,
|
|||
|
||||
static void omap_timer_restore_context(struct omap_dm_timer *timer)
|
||||
{
|
||||
__omap_dm_timer_write(timer, OMAP_TIMER_OCP_CFG_OFFSET,
|
||||
timer->context.ocp_cfg, 0);
|
||||
|
||||
omap_dm_timer_write_reg(timer, OMAP_TIMER_WAKEUP_EN_REG,
|
||||
timer->context.twer);
|
||||
omap_dm_timer_write_reg(timer, OMAP_TIMER_COUNTER_REG,
|
||||
|
|
@ -95,6 +98,9 @@ static void omap_timer_restore_context(struct omap_dm_timer *timer)
|
|||
|
||||
static void omap_timer_save_context(struct omap_dm_timer *timer)
|
||||
{
|
||||
timer->context.ocp_cfg =
|
||||
__omap_dm_timer_read(timer, OMAP_TIMER_OCP_CFG_OFFSET, 0);
|
||||
|
||||
timer->context.tclr =
|
||||
omap_dm_timer_read_reg(timer, OMAP_TIMER_CTRL_REG);
|
||||
timer->context.twer =
|
||||
|
|
@ -122,7 +128,8 @@ static int omap_timer_context_notifier(struct notifier_block *nb,
|
|||
break;
|
||||
omap_timer_save_context(timer);
|
||||
break;
|
||||
case CPU_CLUSTER_PM_ENTER_FAILED:
|
||||
case CPU_CLUSTER_PM_ENTER_FAILED: /* No need to restore context */
|
||||
break;
|
||||
case CPU_CLUSTER_PM_EXIT:
|
||||
if ((timer->capability & OMAP_TIMER_ALWON) ||
|
||||
!atomic_read(&timer->enabled))
|
||||
|
|
|
|||
|
|
@ -27,6 +27,7 @@ struct samsung_pwm_variant {
|
|||
};
|
||||
|
||||
void samsung_pwm_clocksource_init(void __iomem *base,
|
||||
unsigned int *irqs, struct samsung_pwm_variant *variant);
|
||||
unsigned int *irqs,
|
||||
const struct samsung_pwm_variant *variant);
|
||||
|
||||
#endif /* __CLOCKSOURCE_SAMSUNG_PWM_H */
|
||||
|
|
|
|||
|
|
@ -74,6 +74,7 @@
|
|||
#define OMAP_TIMER_ERRATA_I103_I767 0x80000000
|
||||
|
||||
struct timer_regs {
|
||||
u32 ocp_cfg;
|
||||
u32 tidr;
|
||||
u32 tier;
|
||||
u32 twer;
|
||||
|
|
|
|||
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