amd64_edac: unify MCGCTL ECC switching
Unify almost identical code into one function and remove NUMA-specific usage (specifically cpumask_of_node()) in favor of generic topology methods. Remove unused defines, while at it. Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
This commit is contained in:
Borislav Petkov
Родитель
ba578cb34a
Коммит
f6d6ae9657
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@ -2624,121 +2624,6 @@ static int amd64_init_csrows(struct mem_ctl_info *mci)
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return empty;
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return empty;
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}
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}
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/*
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* Only if 'ecc_enable_override' is set AND BIOS had ECC disabled, do "we"
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* enable it.
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*/
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static void amd64_enable_ecc_error_reporting(struct mem_ctl_info *mci)
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{
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struct amd64_pvt *pvt = mci->pvt_info;
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const struct cpumask *cpumask = cpumask_of_node(pvt->mc_node_id);
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int cpu, idx = 0, err = 0;
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struct msr msrs[cpumask_weight(cpumask)];
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u32 value;
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u32 mask = K8_NBCTL_CECCEn | K8_NBCTL_UECCEn;
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if (!ecc_enable_override)
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return;
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memset(msrs, 0, sizeof(msrs));
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amd64_printk(KERN_WARNING,
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"'ecc_enable_override' parameter is active, "
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"Enabling AMD ECC hardware now: CAUTION\n");
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err = pci_read_config_dword(pvt->misc_f3_ctl, K8_NBCTL, &value);
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if (err)
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debugf0("Reading K8_NBCTL failed\n");
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/* turn on UECCn and CECCEn bits */
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pvt->old_nbctl = value & mask;
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pvt->nbctl_mcgctl_saved = 1;
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value |= mask;
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pci_write_config_dword(pvt->misc_f3_ctl, K8_NBCTL, value);
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rdmsr_on_cpus(cpumask, K8_MSR_MCGCTL, msrs);
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for_each_cpu(cpu, cpumask) {
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if (msrs[idx].l & K8_MSR_MCGCTL_NBE)
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set_bit(idx, &pvt->old_mcgctl);
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msrs[idx].l |= K8_MSR_MCGCTL_NBE;
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idx++;
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}
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wrmsr_on_cpus(cpumask, K8_MSR_MCGCTL, msrs);
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err = pci_read_config_dword(pvt->misc_f3_ctl, K8_NBCFG, &value);
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if (err)
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debugf0("Reading K8_NBCFG failed\n");
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debugf0("NBCFG(1)= 0x%x CHIPKILL= %s ECC_ENABLE= %s\n", value,
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(value & K8_NBCFG_CHIPKILL) ? "Enabled" : "Disabled",
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(value & K8_NBCFG_ECC_ENABLE) ? "Enabled" : "Disabled");
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if (!(value & K8_NBCFG_ECC_ENABLE)) {
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amd64_printk(KERN_WARNING,
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"This node reports that DRAM ECC is "
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"currently Disabled; ENABLING now\n");
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/* Attempt to turn on DRAM ECC Enable */
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value |= K8_NBCFG_ECC_ENABLE;
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pci_write_config_dword(pvt->misc_f3_ctl, K8_NBCFG, value);
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err = pci_read_config_dword(pvt->misc_f3_ctl, K8_NBCFG, &value);
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if (err)
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debugf0("Reading K8_NBCFG failed\n");
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if (!(value & K8_NBCFG_ECC_ENABLE)) {
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amd64_printk(KERN_WARNING,
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"Hardware rejects Enabling DRAM ECC checking\n"
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"Check memory DIMM configuration\n");
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} else {
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amd64_printk(KERN_DEBUG,
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"Hardware accepted DRAM ECC Enable\n");
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}
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}
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debugf0("NBCFG(2)= 0x%x CHIPKILL= %s ECC_ENABLE= %s\n", value,
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(value & K8_NBCFG_CHIPKILL) ? "Enabled" : "Disabled",
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(value & K8_NBCFG_ECC_ENABLE) ? "Enabled" : "Disabled");
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pvt->ctl_error_info.nbcfg = value;
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}
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static void amd64_restore_ecc_error_reporting(struct amd64_pvt *pvt)
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{
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const struct cpumask *cpumask = cpumask_of_node(pvt->mc_node_id);
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int cpu, idx = 0, err = 0;
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struct msr msrs[cpumask_weight(cpumask)];
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u32 value;
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u32 mask = K8_NBCTL_CECCEn | K8_NBCTL_UECCEn;
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if (!pvt->nbctl_mcgctl_saved)
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return;
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memset(msrs, 0, sizeof(msrs));
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err = pci_read_config_dword(pvt->misc_f3_ctl, K8_NBCTL, &value);
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if (err)
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debugf0("Reading K8_NBCTL failed\n");
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value &= ~mask;
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value |= pvt->old_nbctl;
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/* restore the NB Enable MCGCTL bit */
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pci_write_config_dword(pvt->misc_f3_ctl, K8_NBCTL, value);
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rdmsr_on_cpus(cpumask, K8_MSR_MCGCTL, msrs);
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for_each_cpu(cpu, cpumask) {
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msrs[idx].l &= ~K8_MSR_MCGCTL_NBE;
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msrs[idx].l |=
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test_bit(idx, &pvt->old_mcgctl) << K8_MSR_MCGCTL_NBE;
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idx++;
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}
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wrmsr_on_cpus(cpumask, K8_MSR_MCGCTL, msrs);
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}
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/* get all cores on this DCT */
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/* get all cores on this DCT */
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static void get_cpus_on_this_dct_cpumask(struct cpumask *mask, int nid)
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static void get_cpus_on_this_dct_cpumask(struct cpumask *mask, int nid)
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{
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{
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@ -2795,6 +2680,144 @@ out:
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return ret;
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return ret;
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}
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}
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static int amd64_toggle_ecc_err_reporting(struct amd64_pvt *pvt, bool on)
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{
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cpumask_var_t cmask;
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struct msr *msrs = NULL;
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int cpu, idx = 0;
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if (!zalloc_cpumask_var(&cmask, GFP_KERNEL)) {
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amd64_printk(KERN_WARNING, "%s: error allocating mask\n",
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__func__);
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return false;
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}
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get_cpus_on_this_dct_cpumask(cmask, pvt->mc_node_id);
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msrs = kzalloc(sizeof(struct msr) * cpumask_weight(cmask), GFP_KERNEL);
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if (!msrs) {
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amd64_printk(KERN_WARNING, "%s: error allocating msrs\n",
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__func__);
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return -ENOMEM;
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}
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rdmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs);
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for_each_cpu(cpu, cmask) {
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if (on) {
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if (msrs[idx].l & K8_MSR_MCGCTL_NBE)
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pvt->flags.ecc_report = 1;
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msrs[idx].l |= K8_MSR_MCGCTL_NBE;
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} else {
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/*
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* Turn off ECC reporting only when it was off before
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*/
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if (!pvt->flags.ecc_report)
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msrs[idx].l &= ~K8_MSR_MCGCTL_NBE;
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}
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idx++;
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}
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wrmsr_on_cpus(cmask, MSR_IA32_MCG_CTL, msrs);
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kfree(msrs);
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free_cpumask_var(cmask);
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return 0;
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}
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/*
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* Only if 'ecc_enable_override' is set AND BIOS had ECC disabled, do "we"
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* enable it.
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*/
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static void amd64_enable_ecc_error_reporting(struct mem_ctl_info *mci)
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{
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struct amd64_pvt *pvt = mci->pvt_info;
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int err = 0;
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u32 value, mask = K8_NBCTL_CECCEn | K8_NBCTL_UECCEn;
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if (!ecc_enable_override)
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return;
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amd64_printk(KERN_WARNING,
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"'ecc_enable_override' parameter is active, "
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"Enabling AMD ECC hardware now: CAUTION\n");
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err = pci_read_config_dword(pvt->misc_f3_ctl, K8_NBCTL, &value);
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if (err)
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debugf0("Reading K8_NBCTL failed\n");
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/* turn on UECCn and CECCEn bits */
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pvt->old_nbctl = value & mask;
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pvt->nbctl_mcgctl_saved = 1;
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value |= mask;
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pci_write_config_dword(pvt->misc_f3_ctl, K8_NBCTL, value);
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if (amd64_toggle_ecc_err_reporting(pvt, ON))
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amd64_printk(KERN_WARNING, "Error enabling ECC reporting over "
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"MCGCTL!\n");
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err = pci_read_config_dword(pvt->misc_f3_ctl, K8_NBCFG, &value);
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if (err)
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debugf0("Reading K8_NBCFG failed\n");
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debugf0("NBCFG(1)= 0x%x CHIPKILL= %s ECC_ENABLE= %s\n", value,
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(value & K8_NBCFG_CHIPKILL) ? "Enabled" : "Disabled",
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(value & K8_NBCFG_ECC_ENABLE) ? "Enabled" : "Disabled");
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if (!(value & K8_NBCFG_ECC_ENABLE)) {
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amd64_printk(KERN_WARNING,
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"This node reports that DRAM ECC is "
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"currently Disabled; ENABLING now\n");
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/* Attempt to turn on DRAM ECC Enable */
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value |= K8_NBCFG_ECC_ENABLE;
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pci_write_config_dword(pvt->misc_f3_ctl, K8_NBCFG, value);
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err = pci_read_config_dword(pvt->misc_f3_ctl, K8_NBCFG, &value);
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if (err)
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debugf0("Reading K8_NBCFG failed\n");
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if (!(value & K8_NBCFG_ECC_ENABLE)) {
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amd64_printk(KERN_WARNING,
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"Hardware rejects Enabling DRAM ECC checking\n"
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"Check memory DIMM configuration\n");
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} else {
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amd64_printk(KERN_DEBUG,
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"Hardware accepted DRAM ECC Enable\n");
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}
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}
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debugf0("NBCFG(2)= 0x%x CHIPKILL= %s ECC_ENABLE= %s\n", value,
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(value & K8_NBCFG_CHIPKILL) ? "Enabled" : "Disabled",
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(value & K8_NBCFG_ECC_ENABLE) ? "Enabled" : "Disabled");
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pvt->ctl_error_info.nbcfg = value;
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}
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static void amd64_restore_ecc_error_reporting(struct amd64_pvt *pvt)
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{
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int err = 0;
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u32 value, mask = K8_NBCTL_CECCEn | K8_NBCTL_UECCEn;
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if (!pvt->nbctl_mcgctl_saved)
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return;
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err = pci_read_config_dword(pvt->misc_f3_ctl, K8_NBCTL, &value);
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if (err)
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debugf0("Reading K8_NBCTL failed\n");
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value &= ~mask;
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value |= pvt->old_nbctl;
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/* restore the NB Enable MCGCTL bit */
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pci_write_config_dword(pvt->misc_f3_ctl, K8_NBCTL, value);
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if (amd64_toggle_ecc_err_reporting(pvt, OFF))
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amd64_printk(KERN_WARNING, "Error restoring ECC reporting over "
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"MCGCTL!\n");
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}
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/*
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/*
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* EDAC requires that the BIOS have ECC enabled before taking over the
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* EDAC requires that the BIOS have ECC enabled before taking over the
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* processing of ECC errors. This is because the BIOS can properly initialize
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* processing of ECC errors. This is because the BIOS can properly initialize
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@ -2921,7 +2944,6 @@ static int amd64_probe_one_instance(struct pci_dev *dram_f2_ctl,
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pvt->ext_model = boot_cpu_data.x86_model >> 4;
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pvt->ext_model = boot_cpu_data.x86_model >> 4;
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pvt->mc_type_index = mc_type_index;
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pvt->mc_type_index = mc_type_index;
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pvt->ops = family_ops(mc_type_index);
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pvt->ops = family_ops(mc_type_index);
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pvt->old_mcgctl = 0;
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/*
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/*
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* We have the dram_f2_ctl device as an argument, now go reserve its
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* We have the dram_f2_ctl device as an argument, now go reserve its
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@ -147,6 +147,8 @@
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#define MAX_CS_COUNT 8
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#define MAX_CS_COUNT 8
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#define DRAM_REG_COUNT 8
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#define DRAM_REG_COUNT 8
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#define ON true
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#define OFF false
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/*
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/*
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* PCI-defined configuration space registers
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* PCI-defined configuration space registers
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@ -386,10 +388,7 @@ enum {
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#define K8_NBCAP_DUAL_NODE BIT(1)
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#define K8_NBCAP_DUAL_NODE BIT(1)
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#define K8_NBCAP_DCT_DUAL BIT(0)
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#define K8_NBCAP_DCT_DUAL BIT(0)
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/*
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/* MSRs */
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* MSR Regs
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*/
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#define K8_MSR_MCGCTL 0x017b
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#define K8_MSR_MCGCTL_NBE BIT(4)
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#define K8_MSR_MCGCTL_NBE BIT(4)
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#define K8_MSR_MC4CTL 0x0410
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#define K8_MSR_MC4CTL 0x0410
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@ -487,7 +486,6 @@ struct amd64_pvt {
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/* Save old hw registers' values before we modified them */
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/* Save old hw registers' values before we modified them */
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u32 nbctl_mcgctl_saved; /* When true, following 2 are valid */
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u32 nbctl_mcgctl_saved; /* When true, following 2 are valid */
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u32 old_nbctl;
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u32 old_nbctl;
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unsigned long old_mcgctl; /* per core on this node */
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/* MC Type Index value: socket F vs Family 10h */
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/* MC Type Index value: socket F vs Family 10h */
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u32 mc_type_index;
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u32 mc_type_index;
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@ -495,6 +493,7 @@ struct amd64_pvt {
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/* misc settings */
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/* misc settings */
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struct flags {
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struct flags {
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unsigned long cf8_extcfg:1;
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unsigned long cf8_extcfg:1;
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unsigned long ecc_report:1;
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} flags;
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} flags;
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};
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};
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