tg3: Add 5717 asic rev
This patch adds the 5717 asic rev. Signed-off-by: Matt Carlson <mcarlson@broadcom.com> Reviewed-by: Benjamin Li <benli@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Matt Carlson
David S. Miller
Родитель
8d9d7cfc0e
Коммит
f6eb9b1fc1
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@ -111,7 +111,8 @@
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* replace things like '% foo' with '& (foo - 1)'.
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*/
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#define TG3_RX_RCB_RING_SIZE(tp) \
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((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ? 512 : 1024)
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(((tp->tg3_flags & TG3_FLAG_JUMBO_CAPABLE) && \
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!(tp->tg3_flags2 & TG3_FLG2_5780_CLASS)) ? 512 : 1024)
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#define TG3_TX_RING_SIZE 512
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#define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
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@ -733,13 +734,15 @@ static inline void tg3_netif_start(struct tg3 *tp)
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static void tg3_switch_clocks(struct tg3 *tp)
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{
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u32 clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
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u32 clock_ctrl;
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u32 orig_clock_ctrl;
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if ((tp->tg3_flags & TG3_FLAG_CPMU_PRESENT) ||
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(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
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return;
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clock_ctrl = tr32(TG3PCI_CLOCK_CTRL);
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orig_clock_ctrl = clock_ctrl;
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clock_ctrl &= (CLOCK_CTRL_FORCE_CLKRUN |
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CLOCK_CTRL_CLKRUN_OENABLE |
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@ -1993,8 +1996,9 @@ static void tg3_frob_aux_power(struct tg3 *tp)
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if ((tp->tg3_flags2 & TG3_FLG2_IS_NIC) == 0)
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return;
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if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
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(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714)) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
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struct net_device *dev_peer;
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dev_peer = pci_get_drvdata(tp->pdev_peer);
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@ -5211,6 +5215,7 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
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mss = 0;
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if ((mss = skb_shinfo(skb)->gso_size) != 0) {
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int tcp_opt_len, ip_tcp_len;
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u32 hdrlen;
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if (skb_header_cloned(skb) &&
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pskb_expand_head(skb, 0, 0, GFP_ATOMIC)) {
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@ -5219,7 +5224,7 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
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}
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if (skb_shinfo(skb)->gso_type & SKB_GSO_TCPV6)
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mss |= (skb_headlen(skb) - ETH_HLEN) << 9;
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hdrlen = skb_headlen(skb) - ETH_HLEN;
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else {
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struct iphdr *iph = ip_hdr(skb);
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@ -5228,9 +5233,17 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
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iph->check = 0;
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iph->tot_len = htons(mss + ip_tcp_len + tcp_opt_len);
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mss |= (ip_tcp_len + tcp_opt_len) << 9;
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hdrlen = ip_tcp_len + tcp_opt_len;
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}
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
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mss |= (hdrlen & 0xc) << 12;
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if (hdrlen & 0x10)
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base_flags |= 0x00000010;
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base_flags |= (hdrlen & 0x3e0) << 5;
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} else
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mss |= hdrlen << 9;
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base_flags |= (TXD_FLAG_CPU_PRE_DMA |
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TXD_FLAG_CPU_POST_DMA);
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@ -5258,6 +5271,10 @@ static netdev_tx_t tg3_start_xmit(struct sk_buff *skb,
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len = skb_headlen(skb);
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
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!mss && skb->len > ETH_DATA_LEN)
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base_flags |= TXD_FLAG_JMB_PKT;
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tg3_set_txd(tnapi, entry, mapping, len, base_flags,
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(skb_shinfo(skb)->nr_frags == 0) | (mss << 1));
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@ -6564,7 +6581,9 @@ static int tg3_chip_reset(struct tg3 *tp)
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tg3_mdio_start(tp);
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if ((tp->tg3_flags2 & TG3_FLG2_PCI_EXPRESS) &&
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tp->pci_chip_rev_id != CHIPREV_ID_5750_A0) {
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tp->pci_chip_rev_id != CHIPREV_ID_5750_A0 &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
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val = tr32(0x7c00);
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tw32(0x7c00, val | (1 << 25));
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@ -6993,7 +7012,9 @@ static void tg3_rings_reset(struct tg3 *tp)
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/* Disable all receive return rings but the first. */
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if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
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limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17;
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else if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS))
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limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16;
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else if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755)
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limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4;
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@ -7197,7 +7218,8 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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return err;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5784 &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761) {
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5761 &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
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/* This value is determined during the probe time DMA
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* engine test, tg3_test_dma.
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*/
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@ -7351,6 +7373,10 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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BDINFO_FLAGS_DISABLED);
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}
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
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val = (RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT) |
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(RX_STD_MAX_SIZE << 2);
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else
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val = RX_STD_MAX_SIZE << BDINFO_FLAGS_MAXLEN_SHIFT;
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} else
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val = RX_STD_MAX_SIZE_5705 << BDINFO_FLAGS_MAXLEN_SHIFT;
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@ -7366,6 +7392,11 @@ static int tg3_reset_hw(struct tg3 *tp, int reset_phy)
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tw32_rx_mbox(MAILBOX_RCV_JUMBO_PROD_IDX + TG3_64BIT_REG_LOW,
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tpr->rx_jmb_ptr);
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
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tw32(STD_REPLENISH_LWM, 32);
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tw32(JMB_REPLENISH_LWM, 16);
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}
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tg3_rings_reset(tp);
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/* Initialize MAC address and backoff seed. */
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@ -8021,6 +8052,7 @@ static int tg3_test_interrupt(struct tg3 *tp)
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struct tg3_napi *tnapi = &tp->napi[0];
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struct net_device *dev = tp->dev;
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int err, i, intr_ok = 0;
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u32 val;
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if (!netif_running(dev))
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return -ENODEV;
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@ -8029,6 +8061,16 @@ static int tg3_test_interrupt(struct tg3 *tp)
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free_irq(tnapi->irq_vec, tnapi);
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/*
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* Turn off MSI one shot mode. Otherwise this test has no
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* observable way to know whether the interrupt was delivered.
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*/
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
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(tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
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val = tr32(MSGINT_MODE) | MSGINT_MODE_ONE_SHOT_DISABLE;
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tw32(MSGINT_MODE, val);
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}
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err = request_irq(tnapi->irq_vec, tg3_test_isr,
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IRQF_SHARED | IRQF_SAMPLE_RANDOM, dev->name, tnapi);
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if (err)
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@ -8064,8 +8106,15 @@ static int tg3_test_interrupt(struct tg3 *tp)
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if (err)
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return err;
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if (intr_ok)
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if (intr_ok) {
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/* Reenable MSI one shot mode. */
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717 &&
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(tp->tg3_flags2 & TG3_FLG2_USING_MSI)) {
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val = tr32(MSGINT_MODE) & ~MSGINT_MODE_ONE_SHOT_DISABLE;
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tw32(MSGINT_MODE, val);
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}
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return 0;
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}
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return -EIO;
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}
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@ -8350,15 +8399,15 @@ static int tg3_open(struct net_device *dev)
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goto err_out2;
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}
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if (tp->tg3_flags2 & TG3_FLG2_USING_MSI) {
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if (tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717 &&
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(tp->tg3_flags2 & TG3_FLG2_USING_MSI) &&
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(tp->tg3_flags2 & TG3_FLG2_1SHOT_MSI)) {
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u32 val = tr32(PCIE_TRANSACTION_CFG);
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tw32(PCIE_TRANSACTION_CFG,
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val | PCIE_TRANS_CFG_1SHOT_MSI);
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}
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}
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}
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tg3_phy_start(tp);
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@ -9392,7 +9441,8 @@ static int tg3_set_tso(struct net_device *dev, u32 value)
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(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
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GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
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dev->features |= NETIF_F_TSO_ECN;
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} else
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dev->features &= ~(NETIF_F_TSO6 | NETIF_F_TSO_ECN);
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@ -12291,8 +12341,17 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_USE_PROD_ID_REG) {
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u32 prod_id_asic_rev;
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if (tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717C ||
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tp->pdev->device == TG3PCI_DEVICE_TIGON3_5717S ||
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tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718C ||
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tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718S)
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pci_read_config_dword(tp->pdev,
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TG3PCI_GEN2_PRODID_ASICREV,
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&prod_id_asic_rev);
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else
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pci_read_config_dword(tp->pdev, TG3PCI_PRODID_ASICREV,
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&prod_id_asic_rev);
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tp->pci_chip_rev_id = prod_id_asic_rev;
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}
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@ -12430,8 +12489,9 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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pci_write_config_dword(tp->pdev, TG3PCI_MISC_HOST_CTRL,
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tp->misc_host_ctrl);
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if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704) ||
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(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714))
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5714 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
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tp->pdev_peer = tg3_find_peer(tp);
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/* Intentionally exclude ASIC_REV_5906 */
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@ -12440,7 +12500,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
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tp->tg3_flags3 |= TG3_FLG3_5755_PLUS;
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5750 ||
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@ -12490,8 +12551,16 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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tp->irq_max = 1;
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#ifdef TG3_NAPI
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717) {
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tp->tg3_flags |= TG3_FLAG_SUPPORT_MSIX;
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tp->irq_max = TG3_IRQ_MAX_VECS;
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}
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#endif
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if (!(tp->tg3_flags2 & TG3_FLG2_5705_PLUS) ||
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(tp->tg3_flags2 & TG3_FLG2_5780_CLASS))
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(tp->tg3_flags2 & TG3_FLG2_5780_CLASS) ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
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tp->tg3_flags |= TG3_FLAG_JUMBO_CAPABLE;
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pci_read_config_dword(tp->pdev, TG3PCI_PCISTATE,
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@ -12625,7 +12694,6 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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tp->write32 = tg3_write_flush_reg32;
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}
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if ((tp->tg3_flags & TG3_FLAG_TXD_MBOX_HWBUG) ||
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(tp->tg3_flags & TG3_FLAG_MBOX_WRITE_REORDER)) {
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tp->write32_tx_mbox = tg3_write32_tx_mbox;
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@ -12684,7 +12752,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5761 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
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tp->tg3_flags |= TG3_FLAG_CPMU_PRESENT;
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/* Set up tp->grc_local_ctrl before calling tg3_set_power_state().
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@ -12762,7 +12831,8 @@ static int __devinit tg3_get_invariants(struct tg3 *tp)
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if ((tp->tg3_flags2 & TG3_FLG2_5705_PLUS) &&
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!(tp->tg3_flags3 & TG3_FLG3_PHY_IS_FET) &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5785 &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780) {
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_57780 &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5755 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5787 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 ||
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@ -13486,7 +13556,8 @@ static void __devinit tg3_init_link_config(struct tg3 *tp)
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static void __devinit tg3_init_bufmgr_config(struct tg3 *tp)
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{
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if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS) {
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if (tp->tg3_flags2 & TG3_FLG2_5705_PLUS &&
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GET_ASIC_REV(tp->pci_chip_rev_id) != ASIC_REV_5717) {
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tp->bufmgr_config.mbuf_read_dma_low_water =
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DEFAULT_MB_RDMA_LOW_WATER_5705;
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tp->bufmgr_config.mbuf_mac_rx_low_water =
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@ -13925,7 +13996,8 @@ static int __devinit tg3_init_one(struct pci_dev *pdev,
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(GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
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GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5785 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780)
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57780 ||
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GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5717)
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dev->features |= NETIF_F_TSO_ECN;
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}
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@ -46,6 +46,10 @@
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#define TG3PCI_DEVICE_TIGON3_57788 0x1691
|
||||
#define TG3PCI_DEVICE_TIGON3_5785_G 0x1699 /* GPHY */
|
||||
#define TG3PCI_DEVICE_TIGON3_5785_F 0x16a0 /* 10/100 only */
|
||||
#define TG3PCI_DEVICE_TIGON3_5717C 0x1655
|
||||
#define TG3PCI_DEVICE_TIGON3_5717S 0x1656
|
||||
#define TG3PCI_DEVICE_TIGON3_5718C 0x1665
|
||||
#define TG3PCI_DEVICE_TIGON3_5718S 0x1666
|
||||
/* 0x04 --> 0x64 unused */
|
||||
#define TG3PCI_MSI_DATA 0x00000064
|
||||
/* 0x66 --> 0x68 unused */
|
||||
|
|
@ -117,6 +121,7 @@
|
|||
#define ASIC_REV_5761 0x5761
|
||||
#define ASIC_REV_5785 0x5785
|
||||
#define ASIC_REV_57780 0x57780
|
||||
#define ASIC_REV_5717 0x5717
|
||||
#define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8)
|
||||
#define CHIPREV_5700_AX 0x70
|
||||
#define CHIPREV_5700_BX 0x71
|
||||
|
|
@ -203,20 +208,20 @@
|
|||
#define TG3PCI_MEM_WIN_BASE_ADDR 0x0000007c
|
||||
#define TG3PCI_REG_DATA 0x00000080
|
||||
#define TG3PCI_MEM_WIN_DATA 0x00000084
|
||||
#define TG3PCI_MODE_CTRL 0x00000088
|
||||
#define TG3PCI_MISC_CFG 0x0000008c
|
||||
#define TG3PCI_MISC_LOCAL_CTRL 0x00000090
|
||||
/* 0x94 --> 0x98 unused */
|
||||
#define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */
|
||||
#define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */
|
||||
#define TG3PCI_SND_PROD_IDX 0x000000a8 /* 64-bit */
|
||||
/* 0xb0 --> 0xb8 unused */
|
||||
/* 0xa0 --> 0xb8 unused */
|
||||
#define TG3PCI_DUAL_MAC_CTRL 0x000000b8
|
||||
#define DUAL_MAC_CTRL_CH_MASK 0x00000003
|
||||
#define DUAL_MAC_CTRL_ID 0x00000004
|
||||
#define TG3PCI_PRODID_ASICREV 0x000000bc
|
||||
#define PROD_ID_ASIC_REV_MASK 0x0fffffff
|
||||
/* 0xc0 --> 0x110 unused */
|
||||
/* 0xc0 --> 0xf4 unused */
|
||||
|
||||
#define TG3PCI_GEN2_PRODID_ASICREV 0x000000f4
|
||||
/* 0xf8 --> 0x200 unused */
|
||||
|
||||
#define TG3_CORR_ERR_STAT 0x00000110
|
||||
#define TG3_CORR_ERR_STAT_CLEAR 0xffffffff
|
||||
|
|
@ -972,7 +977,11 @@
|
|||
#define RCVBDI_MINI_THRESH 0x00002c14
|
||||
#define RCVBDI_STD_THRESH 0x00002c18
|
||||
#define RCVBDI_JUMBO_THRESH 0x00002c1c
|
||||
/* 0x2c20 --> 0x3000 unused */
|
||||
/* 0x2c20 --> 0x2d00 unused */
|
||||
|
||||
#define STD_REPLENISH_LWM 0x00002d00
|
||||
#define JMB_REPLENISH_LWM 0x00002d04
|
||||
/* 0x2d08 --> 0x3000 unused */
|
||||
|
||||
/* Receive BD Completion Control Registers */
|
||||
#define RCVCC_MODE 0x00003000
|
||||
|
|
@ -1486,6 +1495,7 @@
|
|||
#define MSGINT_MODE 0x00006000
|
||||
#define MSGINT_MODE_RESET 0x00000001
|
||||
#define MSGINT_MODE_ENABLE 0x00000002
|
||||
#define MSGINT_MODE_ONE_SHOT_DISABLE 0x00000020
|
||||
#define MSGINT_MODE_MULTIVEC_EN 0x00000080
|
||||
#define MSGINT_STATUS 0x00006004
|
||||
#define MSGINT_FIFO 0x00006008
|
||||
|
|
@ -2124,6 +2134,7 @@ struct tg3_tx_buffer_desc {
|
|||
#define TXD_FLAG_IP_CSUM 0x0002
|
||||
#define TXD_FLAG_END 0x0004
|
||||
#define TXD_FLAG_IP_FRAG 0x0008
|
||||
#define TXD_FLAG_JMB_PKT 0x0008
|
||||
#define TXD_FLAG_IP_FRAG_END 0x0010
|
||||
#define TXD_FLAG_VLAN 0x0040
|
||||
#define TXD_FLAG_COAL_NOW 0x0080
|
||||
|
|
@ -2520,7 +2531,7 @@ struct tg3_rx_prodring_set {
|
|||
dma_addr_t rx_jmb_mapping;
|
||||
};
|
||||
|
||||
#define TG3_IRQ_MAX_VECS 1
|
||||
#define TG3_IRQ_MAX_VECS 5
|
||||
|
||||
struct tg3_napi {
|
||||
struct napi_struct napi ____cacheline_aligned;
|
||||
|
|
|
|||
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