Merge tag 'mips_kvm_4.11_1' into mips-for-linux-next
MIPS dependencies for KVM Miscellaneous MIPS architecture changes depended on by the MIPS KVM changes in the KVM tree. - Move pgd_alloc() out of header. - Exports so KVM can access page table management and TLBEX functions. - Add return errors to protected cache ops.
This commit is contained in:
James Hogan
Коммит
f700a42008
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@ -43,21 +43,7 @@ static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
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* Initialize a new pgd / pmd table with invalid pointers.
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*/
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extern void pgd_init(unsigned long page);
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static inline pgd_t *pgd_alloc(struct mm_struct *mm)
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{
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pgd_t *ret, *init;
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ret = (pgd_t *) __get_free_pages(GFP_KERNEL, PGD_ORDER);
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if (ret) {
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init = pgd_offset(&init_mm, 0UL);
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pgd_init((unsigned long)ret);
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memcpy(ret + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
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(PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
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}
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return ret;
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}
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extern pgd_t *pgd_alloc(struct mm_struct *mm);
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static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
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{
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@ -147,49 +147,64 @@ static inline void flush_scache_line(unsigned long addr)
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}
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#define protected_cache_op(op,addr) \
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({ \
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int __err = 0; \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noreorder \n" \
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" .set "MIPS_ISA_ARCH_LEVEL" \n" \
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"1: cache %0, (%1) \n" \
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"1: cache %1, (%2) \n" \
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"2: .set pop \n" \
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" .section .fixup,\"ax\" \n" \
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"3: li %0, %3 \n" \
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" j 2b \n" \
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" .previous \n" \
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" .section __ex_table,\"a\" \n" \
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" "STR(PTR)" 1b, 2b \n" \
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" "STR(PTR)" 1b, 3b \n" \
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" .previous" \
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: \
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: "i" (op), "r" (addr))
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: "+r" (__err) \
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: "i" (op), "r" (addr), "i" (-EFAULT)); \
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__err; \
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})
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#define protected_cachee_op(op,addr) \
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({ \
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int __err = 0; \
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__asm__ __volatile__( \
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" .set push \n" \
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" .set noreorder \n" \
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" .set mips0 \n" \
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" .set eva \n" \
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"1: cachee %0, (%1) \n" \
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"1: cachee %1, (%2) \n" \
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"2: .set pop \n" \
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" .section .fixup,\"ax\" \n" \
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"3: li %0, %3 \n" \
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" j 2b \n" \
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" .previous \n" \
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" .section __ex_table,\"a\" \n" \
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" "STR(PTR)" 1b, 2b \n" \
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" "STR(PTR)" 1b, 3b \n" \
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" .previous" \
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: \
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: "i" (op), "r" (addr))
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: "+r" (__err) \
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: "i" (op), "r" (addr), "i" (-EFAULT)); \
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__err; \
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})
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/*
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* The next two are for badland addresses like signal trampolines.
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*/
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static inline void protected_flush_icache_line(unsigned long addr)
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static inline int protected_flush_icache_line(unsigned long addr)
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{
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switch (boot_cpu_type()) {
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case CPU_LOONGSON2:
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protected_cache_op(Hit_Invalidate_I_Loongson2, addr);
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break;
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return protected_cache_op(Hit_Invalidate_I_Loongson2, addr);
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default:
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#ifdef CONFIG_EVA
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protected_cachee_op(Hit_Invalidate_I, addr);
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return protected_cachee_op(Hit_Invalidate_I, addr);
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#else
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protected_cache_op(Hit_Invalidate_I, addr);
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return protected_cache_op(Hit_Invalidate_I, addr);
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#endif
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break;
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}
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}
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@ -199,21 +214,21 @@ static inline void protected_flush_icache_line(unsigned long addr)
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* caches. We're talking about one cacheline unnecessarily getting invalidated
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* here so the penalty isn't overly hard.
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*/
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static inline void protected_writeback_dcache_line(unsigned long addr)
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static inline int protected_writeback_dcache_line(unsigned long addr)
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{
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#ifdef CONFIG_EVA
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protected_cachee_op(Hit_Writeback_Inv_D, addr);
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return protected_cachee_op(Hit_Writeback_Inv_D, addr);
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#else
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protected_cache_op(Hit_Writeback_Inv_D, addr);
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return protected_cache_op(Hit_Writeback_Inv_D, addr);
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#endif
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}
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static inline void protected_writeback_scache_line(unsigned long addr)
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static inline int protected_writeback_scache_line(unsigned long addr)
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{
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#ifdef CONFIG_EVA
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protected_cachee_op(Hit_Writeback_Inv_SD, addr);
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return protected_cachee_op(Hit_Writeback_Inv_SD, addr);
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#else
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protected_cache_op(Hit_Writeback_Inv_SD, addr);
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return protected_cache_op(Hit_Writeback_Inv_SD, addr);
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#endif
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}
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@ -0,0 +1,26 @@
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#ifndef __ASM_TLBEX_H
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#define __ASM_TLBEX_H
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#include <asm/uasm.h>
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/*
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* Write random or indexed TLB entry, and care about the hazards from
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* the preceding mtc0 and for the following eret.
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*/
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enum tlb_write_entry {
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tlb_random,
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tlb_indexed
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};
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extern int pgd_reg;
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void build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
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unsigned int tmp, unsigned int ptr);
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void build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr);
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void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr);
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void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep);
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void build_tlb_write_entry(u32 **p, struct uasm_label **l,
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struct uasm_reloc **r,
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enum tlb_write_entry wmode);
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#endif /* __ASM_TLBEX_H */
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@ -9,6 +9,9 @@
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* Copyright (C) 2012, 2013 MIPS Technologies, Inc. All rights reserved.
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*/
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#ifndef __ASM_UASM_H
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#define __ASM_UASM_H
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#include <linux/types.h>
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#ifdef CONFIG_EXPORT_UASM
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@ -309,3 +312,5 @@ void uasm_il_bltz(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
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void uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1,
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unsigned int reg2, int lid);
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void uasm_il_bnez(u32 **p, struct uasm_reloc **r, unsigned int reg, int lid);
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#endif /* __ASM_UASM_H */
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@ -4,7 +4,7 @@
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obj-y += cache.o dma-default.o extable.o fault.o \
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gup.o init.o mmap.o page.o page-funcs.o \
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tlbex.o tlbex-fault.o tlb-funcs.o
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pgtable.o tlbex.o tlbex-fault.o tlb-funcs.o
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ifdef CONFIG_CPU_MICROMIPS
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obj-y += uasm-micromips.o
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@ -539,6 +539,7 @@ unsigned long pgd_current[NR_CPUS];
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pgd_t swapper_pg_dir[_PTRS_PER_PGD] __section(.bss..swapper_pg_dir);
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#ifndef __PAGETABLE_PMD_FOLDED
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pmd_t invalid_pmd_table[PTRS_PER_PMD] __page_aligned_bss;
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EXPORT_SYMBOL_GPL(invalid_pmd_table);
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#endif
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pte_t invalid_pte_table[PTRS_PER_PTE] __page_aligned_bss;
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EXPORT_SYMBOL(invalid_pte_table);
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@ -6,6 +6,7 @@
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* Copyright (C) 1999, 2000 by Silicon Graphics
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* Copyright (C) 2003 by Ralf Baechle
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*/
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#include <linux/export.h>
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#include <linux/init.h>
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#include <linux/mm.h>
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#include <asm/fixmap.h>
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@ -60,6 +61,7 @@ void pmd_init(unsigned long addr, unsigned long pagetable)
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p[-1] = pagetable;
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} while (p != end);
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}
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EXPORT_SYMBOL_GPL(pmd_init);
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#endif
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pmd_t mk_pmd(struct page *page, pgprot_t prot)
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@ -0,0 +1,25 @@
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/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/export.h>
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#include <linux/mm.h>
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#include <linux/string.h>
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#include <asm/pgalloc.h>
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pgd_t *pgd_alloc(struct mm_struct *mm)
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{
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pgd_t *ret, *init;
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ret = (pgd_t *) __get_free_pages(GFP_KERNEL, PGD_ORDER);
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if (ret) {
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init = pgd_offset(&init_mm, 0UL);
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pgd_init((unsigned long)ret);
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memcpy(ret + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
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(PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
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}
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return ret;
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}
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EXPORT_SYMBOL_GPL(pgd_alloc);
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@ -22,6 +22,7 @@
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*/
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#include <linux/bug.h>
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#include <linux/export.h>
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/smp.h>
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@ -34,6 +35,7 @@
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#include <asm/war.h>
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#include <asm/uasm.h>
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#include <asm/setup.h>
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#include <asm/tlbex.h>
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static int mips_xpa_disabled;
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@ -344,7 +346,8 @@ static int allocate_kscratch(void)
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}
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static int scratch_reg;
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static int pgd_reg;
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int pgd_reg;
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EXPORT_SYMBOL_GPL(pgd_reg);
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enum vmalloc64_mode {not_refill, refill_scratch, refill_noscratch};
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static struct work_registers build_get_work_registers(u32 **p)
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@ -496,15 +499,9 @@ static void __maybe_unused build_tlb_probe_entry(u32 **p)
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}
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}
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/*
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* Write random or indexed TLB entry, and care about the hazards from
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* the preceding mtc0 and for the following eret.
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*/
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enum tlb_write_entry { tlb_random, tlb_indexed };
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static void build_tlb_write_entry(u32 **p, struct uasm_label **l,
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struct uasm_reloc **r,
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enum tlb_write_entry wmode)
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void build_tlb_write_entry(u32 **p, struct uasm_label **l,
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struct uasm_reloc **r,
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enum tlb_write_entry wmode)
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{
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void(*tlbw)(u32 **) = NULL;
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@ -627,6 +624,7 @@ static void build_tlb_write_entry(u32 **p, struct uasm_label **l,
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break;
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}
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}
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EXPORT_SYMBOL_GPL(build_tlb_write_entry);
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static __maybe_unused void build_convert_pte_to_entrylo(u32 **p,
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unsigned int reg)
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@ -781,9 +779,8 @@ static void build_huge_handler_tail(u32 **p, struct uasm_reloc **r,
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* TMP and PTR are scratch.
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* TMP will be clobbered, PTR will hold the pmd entry.
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*/
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static void
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build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
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unsigned int tmp, unsigned int ptr)
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void build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
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unsigned int tmp, unsigned int ptr)
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{
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#ifndef CONFIG_MIPS_PGD_C0_CONTEXT
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long pgdc = (long)pgd_current;
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@ -859,6 +856,7 @@ build_get_pmde64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
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uasm_i_daddu(p, ptr, ptr, tmp); /* add in pmd offset */
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#endif
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}
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EXPORT_SYMBOL_GPL(build_get_pmde64);
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/*
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* BVADDR is the faulting address, PTR is scratch.
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@ -934,8 +932,7 @@ build_get_pgd_vmalloc64(u32 **p, struct uasm_label **l, struct uasm_reloc **r,
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* TMP and PTR are scratch.
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* TMP will be clobbered, PTR will hold the pgd entry.
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*/
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static void __maybe_unused
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build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
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void build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
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{
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if (pgd_reg != -1) {
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/* pgd is in pgd_reg */
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@ -960,6 +957,7 @@ build_get_pgde32(u32 **p, unsigned int tmp, unsigned int ptr)
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uasm_i_sll(p, tmp, tmp, PGD_T_LOG2);
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uasm_i_addu(p, ptr, ptr, tmp); /* add in pgd offset */
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}
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EXPORT_SYMBOL_GPL(build_get_pgde32);
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#endif /* !CONFIG_64BIT */
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@ -989,7 +987,7 @@ static void build_adjust_context(u32 **p, unsigned int ctx)
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uasm_i_andi(p, ctx, ctx, mask);
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}
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static void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
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void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
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{
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/*
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* Bug workaround for the Nevada. It seems as if under certain
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@ -1013,8 +1011,9 @@ static void build_get_ptep(u32 **p, unsigned int tmp, unsigned int ptr)
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build_adjust_context(p, tmp);
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UASM_i_ADDU(p, ptr, ptr, tmp); /* add in offset */
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}
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EXPORT_SYMBOL_GPL(build_get_ptep);
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static void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep)
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void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep)
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{
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int pte_off_even = 0;
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int pte_off_odd = sizeof(pte_t);
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@ -1063,6 +1062,7 @@ static void build_update_entries(u32 **p, unsigned int tmp, unsigned int ptep)
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UASM_i_MTC0(p, 0, C0_ENTRYLO1);
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UASM_i_MTC0(p, ptep, C0_ENTRYLO1); /* load it */
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}
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EXPORT_SYMBOL_GPL(build_update_entries);
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struct mips_huge_tlb_info {
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int huge_pte;
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@ -1536,7 +1536,9 @@ static void build_loongson3_tlb_refill_handler(void)
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extern u32 handle_tlbl[], handle_tlbl_end[];
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extern u32 handle_tlbs[], handle_tlbs_end[];
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extern u32 handle_tlbm[], handle_tlbm_end[];
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extern u32 tlbmiss_handler_setup_pgd_start[], tlbmiss_handler_setup_pgd[];
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extern u32 tlbmiss_handler_setup_pgd_start[];
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extern u32 tlbmiss_handler_setup_pgd[];
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EXPORT_SYMBOL_GPL(tlbmiss_handler_setup_pgd);
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extern u32 tlbmiss_handler_setup_pgd_end[];
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static void build_setup_pgd(void)
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