clk: ns2: add clock support for Broadcom Northstar 2 SoC
The Broadcom Northstar 2 SoC is architected under the iProc architecture. It has the following PLLs: GENPLL SCR, GENPLL SW, LCPLL DDR, LCPLL Ports, all derived from an onboard crystal. Signed-off-by: Jon Mason <jonmason@broadcom.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
This commit is contained in:
Jon Mason
Stephen Boyd
Родитель
40c8bec3f2
Коммит
f7225a832d
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@ -47,7 +47,7 @@ obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
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obj-$(CONFIG_COMMON_CLK_XGENE) += clk-xgene.o
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obj-$(CONFIG_COMMON_CLK_PWM) += clk-pwm.o
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obj-$(CONFIG_COMMON_CLK_AT91) += at91/
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obj-$(CONFIG_ARCH_BCM) += bcm/
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obj-y += bcm/
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obj-$(CONFIG_ARCH_BERLIN) += berlin/
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obj-$(CONFIG_ARCH_HISI) += hisilicon/
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obj-$(CONFIG_ARCH_MXC) += imx/
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@ -3,6 +3,7 @@ obj-$(CONFIG_CLK_BCM_KONA) += clk-kona-setup.o
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obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm281xx.o
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obj-$(CONFIG_CLK_BCM_KONA) += clk-bcm21664.o
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obj-$(CONFIG_COMMON_CLK_IPROC) += clk-iproc-armpll.o clk-iproc-pll.o clk-iproc-asiu.o
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obj-$(CONFIG_COMMON_CLK_IPROC) += clk-ns2.o
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obj-$(CONFIG_ARCH_BCM_CYGNUS) += clk-cygnus.o
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obj-$(CONFIG_ARCH_BCM_NSP) += clk-nsp.o
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obj-$(CONFIG_ARCH_BCM_5301X) += clk-nsp.o
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@ -0,0 +1,288 @@
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/*
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* Copyright (C) 2015 Broadcom Corporation
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation version 2.
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*
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any
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* kind, whether express or implied; without even the implied warranty
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include <linux/clk-provider.h>
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#include <linux/io.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <dt-bindings/clock/bcm-ns2.h>
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#include "clk-iproc.h"
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#define REG_VAL(o, s, w) { .offset = o, .shift = s, .width = w, }
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#define AON_VAL(o, pw, ps, is) { .offset = o, .pwr_width = pw, \
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.pwr_shift = ps, .iso_shift = is }
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#define RESET_VAL(o, rs, prs) { .offset = o, .reset_shift = rs, \
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.p_reset_shift = prs }
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#define DF_VAL(o, kis, kiw, kps, kpw, kas, kaw) { .offset = o, .ki_shift = kis,\
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.ki_width = kiw, .kp_shift = kps, .kp_width = kpw, .ka_shift = kas, \
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.ka_width = kaw }
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#define VCO_CTRL_VAL(uo, lo) { .u_offset = uo, .l_offset = lo }
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#define ENABLE_VAL(o, es, hs, bs) { .offset = o, .enable_shift = es, \
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.hold_shift = hs, .bypass_shift = bs }
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static const struct iproc_pll_ctrl genpll_scr = {
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.flags = IPROC_CLK_AON | IPROC_CLK_PLL_SPLIT_STAT_CTRL,
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.aon = AON_VAL(0x0, 1, 15, 12),
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.reset = RESET_VAL(0x4, 2, 1),
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.dig_filter = DF_VAL(0x0, 9, 3, 5, 4, 2, 3),
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.ndiv_int = REG_VAL(0x8, 4, 10),
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.pdiv = REG_VAL(0x8, 0, 4),
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.vco_ctrl = VCO_CTRL_VAL(0x10, 0xc),
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.status = REG_VAL(0x0, 27, 1),
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};
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static const struct iproc_clk_ctrl genpll_scr_clk[] = {
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/* bypass_shift, the last value passed into ENABLE_VAL(), is not defined
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* in NS2. However, it doesn't appear to be used anywhere, so setting
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* it to 0.
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*/
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[BCM_NS2_GENPLL_SCR_SCR_CLK] = {
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.channel = BCM_NS2_GENPLL_SCR_SCR_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 18, 12, 0),
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.mdiv = REG_VAL(0x18, 0, 8),
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},
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[BCM_NS2_GENPLL_SCR_FS_CLK] = {
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.channel = BCM_NS2_GENPLL_SCR_FS_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 19, 13, 0),
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.mdiv = REG_VAL(0x18, 8, 8),
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},
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[BCM_NS2_GENPLL_SCR_AUDIO_CLK] = {
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.channel = BCM_NS2_GENPLL_SCR_AUDIO_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 20, 14, 0),
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.mdiv = REG_VAL(0x14, 0, 8),
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},
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[BCM_NS2_GENPLL_SCR_CH3_UNUSED] = {
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.channel = BCM_NS2_GENPLL_SCR_CH3_UNUSED,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 21, 15, 0),
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.mdiv = REG_VAL(0x14, 8, 8),
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},
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[BCM_NS2_GENPLL_SCR_CH4_UNUSED] = {
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.channel = BCM_NS2_GENPLL_SCR_CH4_UNUSED,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 22, 16, 0),
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.mdiv = REG_VAL(0x14, 16, 8),
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},
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[BCM_NS2_GENPLL_SCR_CH5_UNUSED] = {
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.channel = BCM_NS2_GENPLL_SCR_CH5_UNUSED,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 23, 17, 0),
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.mdiv = REG_VAL(0x14, 24, 8),
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},
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};
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static void __init ns2_genpll_scr_clk_init(struct device_node *node)
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{
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iproc_pll_clk_setup(node, &genpll_scr, NULL, 0, genpll_scr_clk,
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ARRAY_SIZE(genpll_scr_clk));
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}
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CLK_OF_DECLARE(ns2_genpll_src_clk, "brcm,ns2-genpll-scr",
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ns2_genpll_scr_clk_init);
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static const struct iproc_pll_ctrl genpll_sw = {
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.flags = IPROC_CLK_AON | IPROC_CLK_PLL_SPLIT_STAT_CTRL,
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.aon = AON_VAL(0x0, 2, 9, 8),
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.reset = RESET_VAL(0x4, 2, 1),
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.dig_filter = DF_VAL(0x0, 9, 3, 5, 4, 2, 3),
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.ndiv_int = REG_VAL(0x8, 4, 10),
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.pdiv = REG_VAL(0x8, 0, 4),
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.vco_ctrl = VCO_CTRL_VAL(0x10, 0xc),
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.status = REG_VAL(0x0, 13, 1),
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};
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static const struct iproc_clk_ctrl genpll_sw_clk[] = {
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/* bypass_shift, the last value passed into ENABLE_VAL(), is not defined
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* in NS2. However, it doesn't appear to be used anywhere, so setting
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* it to 0.
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*/
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[BCM_NS2_GENPLL_SW_RPE_CLK] = {
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.channel = BCM_NS2_GENPLL_SW_RPE_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 18, 12, 0),
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.mdiv = REG_VAL(0x18, 0, 8),
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},
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[BCM_NS2_GENPLL_SW_250_CLK] = {
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.channel = BCM_NS2_GENPLL_SW_250_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 19, 13, 0),
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.mdiv = REG_VAL(0x18, 8, 8),
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},
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[BCM_NS2_GENPLL_SW_NIC_CLK] = {
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.channel = BCM_NS2_GENPLL_SW_NIC_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 20, 14, 0),
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.mdiv = REG_VAL(0x14, 0, 8),
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},
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[BCM_NS2_GENPLL_SW_CHIMP_CLK] = {
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.channel = BCM_NS2_GENPLL_SW_CHIMP_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 21, 15, 0),
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.mdiv = REG_VAL(0x14, 8, 8),
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},
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[BCM_NS2_GENPLL_SW_PORT_CLK] = {
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.channel = BCM_NS2_GENPLL_SW_PORT_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 22, 16, 0),
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.mdiv = REG_VAL(0x14, 16, 8),
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},
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[BCM_NS2_GENPLL_SW_SDIO_CLK] = {
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.channel = BCM_NS2_GENPLL_SW_SDIO_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 23, 17, 0),
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.mdiv = REG_VAL(0x14, 24, 8),
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},
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};
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static void __init ns2_genpll_sw_clk_init(struct device_node *node)
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{
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iproc_pll_clk_setup(node, &genpll_sw, NULL, 0, genpll_sw_clk,
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ARRAY_SIZE(genpll_sw_clk));
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}
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CLK_OF_DECLARE(ns2_genpll_sw_clk, "brcm,ns2-genpll-sw",
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ns2_genpll_sw_clk_init);
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static const struct iproc_pll_ctrl lcpll_ddr = {
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.flags = IPROC_CLK_AON | IPROC_CLK_PLL_SPLIT_STAT_CTRL,
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.aon = AON_VAL(0x0, 2, 1, 0),
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.reset = RESET_VAL(0x4, 2, 1),
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.dig_filter = DF_VAL(0x0, 9, 3, 5, 4, 1, 4),
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.ndiv_int = REG_VAL(0x8, 4, 10),
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.pdiv = REG_VAL(0x8, 0, 4),
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.vco_ctrl = VCO_CTRL_VAL(0x10, 0xc),
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.status = REG_VAL(0x0, 0, 1),
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};
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static const struct iproc_clk_ctrl lcpll_ddr_clk[] = {
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/* bypass_shift, the last value passed into ENABLE_VAL(), is not defined
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* in NS2. However, it doesn't appear to be used anywhere, so setting
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* it to 0.
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*/
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[BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK] = {
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.channel = BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 18, 12, 0),
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.mdiv = REG_VAL(0x14, 0, 8),
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},
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[BCM_NS2_LCPLL_DDR_DDR_CLK] = {
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.channel = BCM_NS2_LCPLL_DDR_DDR_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 19, 13, 0),
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.mdiv = REG_VAL(0x14, 8, 8),
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},
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[BCM_NS2_LCPLL_DDR_CH2_UNUSED] = {
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.channel = BCM_NS2_LCPLL_DDR_CH2_UNUSED,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 20, 14, 0),
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.mdiv = REG_VAL(0x10, 0, 8),
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},
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[BCM_NS2_LCPLL_DDR_CH3_UNUSED] = {
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.channel = BCM_NS2_LCPLL_DDR_CH3_UNUSED,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 21, 15, 0),
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.mdiv = REG_VAL(0x10, 8, 8),
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},
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[BCM_NS2_LCPLL_DDR_CH4_UNUSED] = {
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.channel = BCM_NS2_LCPLL_DDR_CH4_UNUSED,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 22, 16, 0),
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.mdiv = REG_VAL(0x10, 16, 8),
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},
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[BCM_NS2_LCPLL_DDR_CH5_UNUSED] = {
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.channel = BCM_NS2_LCPLL_DDR_CH5_UNUSED,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 23, 17, 0),
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.mdiv = REG_VAL(0x10, 24, 8),
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},
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};
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static void __init ns2_lcpll_ddr_clk_init(struct device_node *node)
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{
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iproc_pll_clk_setup(node, &lcpll_ddr, NULL, 0, lcpll_ddr_clk,
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ARRAY_SIZE(lcpll_ddr_clk));
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}
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CLK_OF_DECLARE(ns2_lcpll_ddr_clk, "brcm,ns2-lcpll-ddr",
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ns2_lcpll_ddr_clk_init);
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static const struct iproc_pll_ctrl lcpll_ports = {
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.flags = IPROC_CLK_AON | IPROC_CLK_PLL_SPLIT_STAT_CTRL,
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.aon = AON_VAL(0x0, 2, 5, 4),
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.reset = RESET_VAL(0x4, 2, 1),
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.dig_filter = DF_VAL(0x0, 9, 3, 5, 4, 1, 4),
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.ndiv_int = REG_VAL(0x8, 4, 10),
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.pdiv = REG_VAL(0x8, 0, 4),
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.vco_ctrl = VCO_CTRL_VAL(0x10, 0xc),
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.status = REG_VAL(0x0, 0, 1),
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};
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static const struct iproc_clk_ctrl lcpll_ports_clk[] = {
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/* bypass_shift, the last value passed into ENABLE_VAL(), is not defined
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* in NS2. However, it doesn't appear to be used anywhere, so setting
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* it to 0.
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*/
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[BCM_NS2_LCPLL_PORTS_WAN_CLK] = {
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.channel = BCM_NS2_LCPLL_PORTS_WAN_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 18, 12, 0),
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.mdiv = REG_VAL(0x14, 0, 8),
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},
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[BCM_NS2_LCPLL_PORTS_RGMII_CLK] = {
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.channel = BCM_NS2_LCPLL_PORTS_RGMII_CLK,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 19, 13, 0),
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.mdiv = REG_VAL(0x14, 8, 8),
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},
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[BCM_NS2_LCPLL_PORTS_CH2_UNUSED] = {
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.channel = BCM_NS2_LCPLL_PORTS_CH2_UNUSED,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 20, 14, 0),
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.mdiv = REG_VAL(0x10, 0, 8),
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},
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[BCM_NS2_LCPLL_PORTS_CH3_UNUSED] = {
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.channel = BCM_NS2_LCPLL_PORTS_CH3_UNUSED,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 21, 15, 0),
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.mdiv = REG_VAL(0x10, 8, 8),
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},
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[BCM_NS2_LCPLL_PORTS_CH4_UNUSED] = {
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.channel = BCM_NS2_LCPLL_PORTS_CH4_UNUSED,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 22, 16, 0),
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.mdiv = REG_VAL(0x10, 16, 8),
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},
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[BCM_NS2_LCPLL_PORTS_CH5_UNUSED] = {
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.channel = BCM_NS2_LCPLL_PORTS_CH5_UNUSED,
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.flags = IPROC_CLK_AON,
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.enable = ENABLE_VAL(0x0, 23, 17, 0),
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.mdiv = REG_VAL(0x10, 24, 8),
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},
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};
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static void __init ns2_lcpll_ports_clk_init(struct device_node *node)
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{
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iproc_pll_clk_setup(node, &lcpll_ports, NULL, 0, lcpll_ports_clk,
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ARRAY_SIZE(lcpll_ports_clk));
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}
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CLK_OF_DECLARE(ns2_lcpll_ports_clk, "brcm,ns2-lcpll-ports",
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ns2_lcpll_ports_clk_init);
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@ -0,0 +1,72 @@
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/*
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* BSD LICENSE
|
||||
*
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||||
* Copyright(c) 2015 Broadcom Corporation. All rights reserved.
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*
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||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
*
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in
|
||||
* the documentation and/or other materials provided with the
|
||||
* distribution.
|
||||
* * Neither the name of Broadcom Corporation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
|
||||
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
|
||||
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
|
||||
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
|
||||
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
|
||||
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
|
||||
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
|
||||
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
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||||
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#ifndef _CLOCK_BCM_NS2_H
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#define _CLOCK_BCM_NS2_H
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/* GENPLL SCR clock channel ID */
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#define BCM_NS2_GENPLL_SCR 0
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#define BCM_NS2_GENPLL_SCR_SCR_CLK 1
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#define BCM_NS2_GENPLL_SCR_FS_CLK 2
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#define BCM_NS2_GENPLL_SCR_AUDIO_CLK 3
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#define BCM_NS2_GENPLL_SCR_CH3_UNUSED 4
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#define BCM_NS2_GENPLL_SCR_CH4_UNUSED 5
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#define BCM_NS2_GENPLL_SCR_CH5_UNUSED 6
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/* GENPLL SW clock channel ID */
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#define BCM_NS2_GENPLL_SW 0
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#define BCM_NS2_GENPLL_SW_RPE_CLK 1
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#define BCM_NS2_GENPLL_SW_250_CLK 2
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#define BCM_NS2_GENPLL_SW_NIC_CLK 3
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#define BCM_NS2_GENPLL_SW_CHIMP_CLK 4
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#define BCM_NS2_GENPLL_SW_PORT_CLK 5
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#define BCM_NS2_GENPLL_SW_SDIO_CLK 6
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/* LCPLL DDR clock channel ID */
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#define BCM_NS2_LCPLL_DDR 0
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#define BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK 1
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#define BCM_NS2_LCPLL_DDR_DDR_CLK 2
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#define BCM_NS2_LCPLL_DDR_CH2_UNUSED 3
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#define BCM_NS2_LCPLL_DDR_CH3_UNUSED 4
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#define BCM_NS2_LCPLL_DDR_CH4_UNUSED 5
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#define BCM_NS2_LCPLL_DDR_CH5_UNUSED 6
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/* LCPLL PORTS clock channel ID */
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#define BCM_NS2_LCPLL_PORTS 0
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#define BCM_NS2_LCPLL_PORTS_WAN_CLK 1
|
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#define BCM_NS2_LCPLL_PORTS_RGMII_CLK 2
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#define BCM_NS2_LCPLL_PORTS_CH2_UNUSED 3
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#define BCM_NS2_LCPLL_PORTS_CH3_UNUSED 4
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#define BCM_NS2_LCPLL_PORTS_CH4_UNUSED 5
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#define BCM_NS2_LCPLL_PORTS_CH5_UNUSED 6
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||||
#endif /* _CLOCK_BCM_NS2_H */
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