Merge remote-tracking branches 'asoc/fix/cs4265', 'asoc/fix/davinci', 'asoc/fix/rockchip', 'asoc/fix/samsung' and 'asoc/fix/tlv320aic31xx' into asoc-linus
This commit is contained in:
Mark Brown
Коммит
f7667af217
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@ -31,7 +31,7 @@ i2s@ff890000 {
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#address-cells = <1>;
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#size-cells = <0>;
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dmas = <&pdma1 0>, <&pdma1 1>;
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dma-names = "rx", "tx";
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dma-names = "tx", "rx";
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clock-names = "i2s_hclk", "i2s_clk";
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clocks = <&cru HCLK_I2S0>, <&cru SCLK_I2S0>;
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};
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@ -458,12 +458,12 @@ static int cs4265_pcm_hw_params(struct snd_pcm_substream *substream,
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if (params_width(params) == 16) {
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snd_soc_update_bits(codec, CS4265_DAC_CTL,
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CS4265_DAC_CTL_DIF, (1 << 5));
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snd_soc_update_bits(codec, CS4265_ADC_CTL,
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snd_soc_update_bits(codec, CS4265_SPDIF_CTL2,
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CS4265_SPDIF_CTL2_DIF, (1 << 7));
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} else {
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snd_soc_update_bits(codec, CS4265_DAC_CTL,
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CS4265_DAC_CTL_DIF, (3 << 5));
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snd_soc_update_bits(codec, CS4265_ADC_CTL,
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snd_soc_update_bits(codec, CS4265_SPDIF_CTL2,
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CS4265_SPDIF_CTL2_DIF, (1 << 7));
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}
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break;
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@ -472,7 +472,7 @@ static int cs4265_pcm_hw_params(struct snd_pcm_substream *substream,
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CS4265_DAC_CTL_DIF, 0);
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snd_soc_update_bits(codec, CS4265_ADC_CTL,
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CS4265_ADC_DIF, 0);
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snd_soc_update_bits(codec, CS4265_ADC_CTL,
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snd_soc_update_bits(codec, CS4265_SPDIF_CTL2,
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CS4265_SPDIF_CTL2_DIF, (1 << 6));
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break;
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@ -189,46 +189,57 @@ static const struct aic31xx_rate_divs aic31xx_divs[] = {
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/* mclk rate pll: p j d dosr ndac mdac aors nadc madc */
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/* 8k rate */
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{12000000, 8000, 1, 8, 1920, 128, 48, 2, 128, 48, 2},
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{12000000, 8000, 1, 8, 1920, 128, 32, 3, 128, 32, 3},
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{24000000, 8000, 2, 8, 1920, 128, 48, 2, 128, 48, 2},
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{25000000, 8000, 2, 7, 8643, 128, 48, 2, 128, 48, 2},
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/* 11.025k rate */
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{12000000, 11025, 1, 7, 5264, 128, 32, 2, 128, 32, 2},
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{12000000, 11025, 1, 8, 4672, 128, 24, 3, 128, 24, 3},
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{24000000, 11025, 2, 7, 5264, 128, 32, 2, 128, 32, 2},
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{25000000, 11025, 2, 7, 2253, 128, 32, 2, 128, 32, 2},
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/* 16k rate */
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{12000000, 16000, 1, 8, 1920, 128, 24, 2, 128, 24, 2},
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{12000000, 16000, 1, 8, 1920, 128, 16, 3, 128, 16, 3},
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{24000000, 16000, 2, 8, 1920, 128, 24, 2, 128, 24, 2},
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{25000000, 16000, 2, 7, 8643, 128, 24, 2, 128, 24, 2},
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/* 22.05k rate */
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{12000000, 22050, 1, 7, 5264, 128, 16, 2, 128, 16, 2},
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{12000000, 22050, 1, 8, 4672, 128, 12, 3, 128, 12, 3},
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{24000000, 22050, 2, 7, 5264, 128, 16, 2, 128, 16, 2},
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{25000000, 22050, 2, 7, 2253, 128, 16, 2, 128, 16, 2},
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/* 32k rate */
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{12000000, 32000, 1, 8, 1920, 128, 12, 2, 128, 12, 2},
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{12000000, 32000, 1, 8, 1920, 128, 8, 3, 128, 8, 3},
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{24000000, 32000, 2, 8, 1920, 128, 12, 2, 128, 12, 2},
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{25000000, 32000, 2, 7, 8643, 128, 12, 2, 128, 12, 2},
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/* 44.1k rate */
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{12000000, 44100, 1, 7, 5264, 128, 8, 2, 128, 8, 2},
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{12000000, 44100, 1, 8, 4672, 128, 6, 3, 128, 6, 3},
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{24000000, 44100, 2, 7, 5264, 128, 8, 2, 128, 8, 2},
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{25000000, 44100, 2, 7, 2253, 128, 8, 2, 128, 8, 2},
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/* 48k rate */
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{12000000, 48000, 1, 8, 1920, 128, 8, 2, 128, 8, 2},
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{12000000, 48000, 1, 7, 6800, 96, 5, 4, 96, 5, 4},
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{24000000, 48000, 2, 8, 1920, 128, 8, 2, 128, 8, 2},
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{25000000, 48000, 2, 7, 8643, 128, 8, 2, 128, 8, 2},
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/* 88.2k rate */
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{12000000, 88200, 1, 7, 5264, 64, 8, 2, 64, 8, 2},
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{12000000, 88200, 1, 8, 4672, 64, 6, 3, 64, 6, 3},
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{24000000, 88200, 2, 7, 5264, 64, 8, 2, 64, 8, 2},
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{25000000, 88200, 2, 7, 2253, 64, 8, 2, 64, 8, 2},
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/* 96k rate */
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{12000000, 96000, 1, 8, 1920, 64, 8, 2, 64, 8, 2},
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{12000000, 96000, 1, 7, 6800, 48, 5, 4, 48, 5, 4},
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{24000000, 96000, 2, 8, 1920, 64, 8, 2, 64, 8, 2},
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{25000000, 96000, 2, 7, 8643, 64, 8, 2, 64, 8, 2},
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/* 176.4k rate */
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{12000000, 176400, 1, 7, 5264, 32, 8, 2, 32, 8, 2},
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{12000000, 176400, 1, 8, 4672, 32, 6, 3, 32, 6, 3},
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{24000000, 176400, 2, 7, 5264, 32, 8, 2, 32, 8, 2},
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{25000000, 176400, 2, 7, 2253, 32, 8, 2, 32, 8, 2},
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/* 192k rate */
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{12000000, 192000, 1, 8, 1920, 32, 8, 2, 32, 8, 2},
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{12000000, 192000, 1, 7, 6800, 24, 5, 4, 24, 5, 4},
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{24000000, 192000, 2, 8, 1920, 32, 8, 2, 32, 8, 2},
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{25000000, 192000, 2, 7, 8643, 32, 8, 2, 32, 8, 2},
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};
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@ -680,7 +691,9 @@ static int aic31xx_setup_pll(struct snd_soc_codec *codec,
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struct snd_pcm_hw_params *params)
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{
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struct aic31xx_priv *aic31xx = snd_soc_codec_get_drvdata(codec);
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int bclk_score = snd_soc_params_to_frame_size(params);
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int bclk_n = 0;
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int match = -1;
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int i;
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/* Use PLL as CODEC_CLKIN and DAC_CLK as BDIV_CLKIN */
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@ -691,15 +704,37 @@ static int aic31xx_setup_pll(struct snd_soc_codec *codec,
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for (i = 0; i < ARRAY_SIZE(aic31xx_divs); i++) {
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if (aic31xx_divs[i].rate == params_rate(params) &&
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aic31xx_divs[i].mclk == aic31xx->sysclk)
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break;
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aic31xx_divs[i].mclk == aic31xx->sysclk) {
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int s = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) %
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snd_soc_params_to_frame_size(params);
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int bn = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac) /
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snd_soc_params_to_frame_size(params);
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if (s < bclk_score && bn > 0) {
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match = i;
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bclk_n = bn;
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bclk_score = s;
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}
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}
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}
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if (i == ARRAY_SIZE(aic31xx_divs)) {
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dev_err(codec->dev, "%s: Sampling rate %u not supported\n",
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if (match == -1) {
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dev_err(codec->dev,
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"%s: Sample rate (%u) and format not supported\n",
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__func__, params_rate(params));
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/* See bellow for details how fix this. */
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return -EINVAL;
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}
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if (bclk_score != 0) {
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dev_warn(codec->dev, "Can not produce exact bitclock");
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/* This is fine if using dsp format, but if using i2s
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there may be trouble. To fix the issue edit the
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aic31xx_divs table for your mclk and sample
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rate. Details can be found from:
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http://www.ti.com/lit/ds/symlink/tlv320aic3100.pdf
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Section: 5.6 CLOCK Generation and PLL
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*/
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}
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i = match;
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/* PLL configuration */
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snd_soc_update_bits(codec, AIC31XX_PLLPR, AIC31XX_PLL_MASK,
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@ -729,14 +764,6 @@ static int aic31xx_setup_pll(struct snd_soc_codec *codec,
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snd_soc_write(codec, AIC31XX_AOSR, aic31xx_divs[i].aosr);
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/* Bit clock divider configuration. */
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bclk_n = (aic31xx_divs[i].dosr * aic31xx_divs[i].mdac)
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/ snd_soc_params_to_frame_size(params);
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if (bclk_n == 0) {
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dev_err(codec->dev, "%s: Not enough BLCK bandwidth\n",
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__func__);
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return -EINVAL;
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}
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snd_soc_update_bits(codec, AIC31XX_BCLKN,
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AIC31XX_PLL_MASK, bclk_n);
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@ -467,8 +467,17 @@ static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
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{
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u32 fmt;
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u32 tx_rotate = (word_length / 4) & 0x7;
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u32 rx_rotate = (32 - word_length) / 4;
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u32 mask = (1ULL << word_length) - 1;
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/*
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* For captured data we should not rotate, inversion and masking is
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* enoguh to get the data to the right position:
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* Format data from bus after reverse (XRBUF)
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* S16_LE: |LSB|MSB|xxx|xxx| |xxx|xxx|MSB|LSB|
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* S24_3LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
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* S24_LE: |LSB|DAT|MSB|xxx| |xxx|MSB|DAT|LSB|
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* S32_LE: |LSB|DAT|DAT|MSB| |MSB|DAT|DAT|LSB|
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*/
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u32 rx_rotate = 0;
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/*
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* if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv()
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@ -165,13 +165,14 @@ static int rockchip_i2s_set_fmt(struct snd_soc_dai *cpu_dai,
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struct rk_i2s_dev *i2s = to_info(cpu_dai);
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unsigned int mask = 0, val = 0;
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mask = I2S_CKR_MSS_SLAVE;
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mask = I2S_CKR_MSS_MASK;
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switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
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case SND_SOC_DAIFMT_CBS_CFS:
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val = I2S_CKR_MSS_SLAVE;
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/* Set source clock in Master mode */
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val = I2S_CKR_MSS_MASTER;
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break;
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case SND_SOC_DAIFMT_CBM_CFM:
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val = I2S_CKR_MSS_MASTER;
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val = I2S_CKR_MSS_SLAVE;
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break;
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default:
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return -EINVAL;
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@ -361,6 +362,8 @@ static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
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case I2S_XFER:
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case I2S_CLR:
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case I2S_RXDR:
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case I2S_FIFOLR:
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case I2S_INTSR:
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return true;
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default:
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return false;
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@ -370,8 +373,8 @@ static bool rockchip_i2s_rd_reg(struct device *dev, unsigned int reg)
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static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case I2S_FIFOLR:
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case I2S_INTSR:
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case I2S_CLR:
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return true;
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default:
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return false;
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@ -381,8 +384,6 @@ static bool rockchip_i2s_volatile_reg(struct device *dev, unsigned int reg)
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static bool rockchip_i2s_precious_reg(struct device *dev, unsigned int reg)
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{
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switch (reg) {
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case I2S_FIFOLR:
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return true;
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default:
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return false;
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}
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@ -462,7 +462,7 @@ static int i2s_set_sysclk(struct snd_soc_dai *dai,
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if (dir == SND_SOC_CLOCK_IN)
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rfs = 0;
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if ((rfs && other->rfs && (other->rfs != rfs)) ||
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if ((rfs && other && other->rfs && (other->rfs != rfs)) ||
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(any_active(i2s) &&
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(((dir == SND_SOC_CLOCK_IN)
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&& !(mod & MOD_CDCLKCON)) ||
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@ -762,6 +762,7 @@ static void i2s_shutdown(struct snd_pcm_substream *substream,
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} else {
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u32 mod = readl(i2s->addr + I2SMOD);
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i2s->cdclk_out = !(mod & MOD_CDCLKCON);
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if (other)
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other->cdclk_out = i2s->cdclk_out;
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}
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/* Reset any constraint on RFS and BFS */
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