perf mem/c2c: Add load store event mappings for AMD
The 'perf mem' and 'perf c2c' tools are wrappers around 'perf record' with mem load/ store events. IBS tagged load/store sample provides most of the information needed for these tools. Wire in the "ibs_op//" event as mem-ldst event for AMD. There are some limitations though: Only load/store micro-ops provide mem/c2c information. Whereas, IBS does not have a way to choose a particular type of micro-op to tag. This results in many non-LS micro-ops being tagged which appear as N/A in the perf report. IBS, being an uncore pmu from kernel point of view[1], does not support per process monitoring. Thus, perf mem/c2c on AMD are currently supported in per-cpu mode only. Example: $ sudo perf mem record -- -c 10000 ^C[ perf record: Woken up 227 times to write data ] [ perf record: Captured and wrote 58.760 MB perf.data (836978 samples) ] $ sudo perf mem report -F mem,sample,snoop Samples: 836K of event 'ibs_op//', Event count (approx.): 8418762 Memory access Samples Snoop N/A 700620 N/A L1 hit 126675 N/A L2 hit 424 N/A L3 hit 664 HitM L3 hit 10 N/A Local RAM hit 2 N/A Remote RAM (1 hop) hit 8558 N/A Remote Cache (1 hop) hit 3 N/A Remote Cache (1 hop) hit 2 HitM Remote Cache (2 hops) hit 10 HitM Remote Cache (2 hops) hit 6 N/A Uncached hit 4 N/A $ [1]: https://lore.kernel.org/lkml/20220829113347.295-1-ravi.bangoria@amd.com Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com> Acked-by: Jiri Olsa <jolsa@kernel.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ali Saidi <alisaidi@amazon.com> Cc: Ananth Narayan <ananth.narayan@amd.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: H. Peter Anvin <hpa@zytor.com> Cc: Ian Rogers <irogers@google.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Joe Mario <jmario@redhat.com> Cc: Kan Liang <kan.liang@linux.intel.com> Cc: Kim Phillips <kim.phillips@amd.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Sandipan Das <sandipan.das@amd.com> Cc: Santosh Shukla <santosh.shukla@amd.com> Cc: Stephane Eranian <eranian@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: x86@kernel.org Link: https://lore.kernel.org/r/20221006153946.7816-6-ravi.bangoria@amd.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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@ -19,9 +19,10 @@ C2C stands for Cache To Cache.
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The perf c2c tool provides means for Shared Data C2C/HITM analysis. It allows
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you to track down the cacheline contentions.
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On x86, the tool is based on load latency and precise store facility events
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On Intel, the tool is based on load latency and precise store facility events
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provided by Intel CPUs. On PowerPC, the tool uses random instruction sampling
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with thresholding feature.
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with thresholding feature. On AMD, the tool uses IBS op pmu (due to hardware
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limitations, perf c2c is not supported on Zen3 cpus).
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These events provide:
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- memory address of the access
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@ -49,7 +50,8 @@ RECORD OPTIONS
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-l::
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--ldlat::
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Configure mem-loads latency. (x86 only)
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Configure mem-loads latency. Supported on Intel and Arm64 processors
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only. Ignored on other archs.
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-k::
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--all-kernel::
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@ -135,11 +137,15 @@ Following perf record options are configured by default:
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-W,-d,--phys-data,--sample-cpu
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Unless specified otherwise with '-e' option, following events are monitored by
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default on x86:
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default on Intel:
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cpu/mem-loads,ldlat=30/P
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cpu/mem-stores/P
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following on AMD:
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ibs_op//
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and following on PowerPC:
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cpu/mem-loads/
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@ -85,7 +85,8 @@ RECORD OPTIONS
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Be more verbose (show counter open errors, etc)
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--ldlat <n>::
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Specify desired latency for loads event. (x86 only)
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Specify desired latency for loads event. Supported on Intel and Arm64
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processors only. Ignored on other archs.
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In addition, for report all perf report options are valid, and for record
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all perf record options.
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@ -1,7 +1,9 @@
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// SPDX-License-Identifier: GPL-2.0
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#include "util/pmu.h"
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#include "util/env.h"
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#include "map_symbol.h"
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#include "mem-events.h"
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#include "linux/string.h"
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static char mem_loads_name[100];
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static bool mem_loads_name__init;
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@ -12,18 +14,43 @@ static char mem_stores_name[100];
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#define E(t, n, s) { .tag = t, .name = n, .sysfs_name = s }
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static struct perf_mem_event perf_mem_events[PERF_MEM_EVENTS__MAX] = {
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static struct perf_mem_event perf_mem_events_intel[PERF_MEM_EVENTS__MAX] = {
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E("ldlat-loads", "%s/mem-loads,ldlat=%u/P", "%s/events/mem-loads"),
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E("ldlat-stores", "%s/mem-stores/P", "%s/events/mem-stores"),
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E(NULL, NULL, NULL),
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};
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static struct perf_mem_event perf_mem_events_amd[PERF_MEM_EVENTS__MAX] = {
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E(NULL, NULL, NULL),
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E(NULL, NULL, NULL),
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E("mem-ldst", "ibs_op//", "ibs_op"),
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};
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static int perf_mem_is_amd_cpu(void)
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{
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struct perf_env env = { .total_mem = 0, };
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perf_env__cpuid(&env);
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if (env.cpuid && strstarts(env.cpuid, "AuthenticAMD"))
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return 1;
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return -1;
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}
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struct perf_mem_event *perf_mem_events__ptr(int i)
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{
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/* 0: Uninitialized, 1: Yes, -1: No */
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static int is_amd;
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if (i >= PERF_MEM_EVENTS__MAX)
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return NULL;
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return &perf_mem_events[i];
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if (!is_amd)
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is_amd = perf_mem_is_amd_cpu();
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if (is_amd == 1)
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return &perf_mem_events_amd[i];
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return &perf_mem_events_intel[i];
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}
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bool is_mem_loads_aux_event(struct evsel *leader)
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