soundwire: Add Master and Slave port programming
Master and Slave port registers need to be programmed for each port used in a stream. Add the helpers for port register programming. Signed-off-by: Sanyog Kale <sanyog.r.kale@intel.com> Signed-off-by: Shreyas NC <shreyas.nc@intel.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Sanyog Kale
Vinod Koul
Родитель
bbe7379d80
Коммит
f8101c74aa
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@ -106,6 +106,10 @@ struct sdw_master_runtime {
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struct list_head bus_node;
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};
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struct sdw_dpn_prop *sdw_get_slave_dpn_prop(struct sdw_slave *slave,
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enum sdw_data_direction direction,
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unsigned int port_num);
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int sdw_transfer(struct sdw_bus *bus, struct sdw_msg *msg);
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int sdw_transfer_defer(struct sdw_bus *bus, struct sdw_msg *msg,
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struct sdw_defer *defer);
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@ -11,9 +11,238 @@
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#include <linux/module.h>
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#include <linux/mod_devicetable.h>
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#include <linux/slab.h>
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#include <linux/soundwire/sdw_registers.h>
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#include <linux/soundwire/sdw.h>
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#include "bus.h"
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static int _sdw_program_slave_port_params(struct sdw_bus *bus,
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struct sdw_slave *slave,
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struct sdw_transport_params *t_params,
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enum sdw_dpn_type type)
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{
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u32 addr1, addr2, addr3, addr4;
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int ret;
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u16 wbuf;
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if (bus->params.next_bank) {
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addr1 = SDW_DPN_OFFSETCTRL2_B1(t_params->port_num);
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addr2 = SDW_DPN_BLOCKCTRL3_B1(t_params->port_num);
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addr3 = SDW_DPN_SAMPLECTRL2_B1(t_params->port_num);
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addr4 = SDW_DPN_HCTRL_B1(t_params->port_num);
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} else {
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addr1 = SDW_DPN_OFFSETCTRL2_B0(t_params->port_num);
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addr2 = SDW_DPN_BLOCKCTRL3_B0(t_params->port_num);
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addr3 = SDW_DPN_SAMPLECTRL2_B0(t_params->port_num);
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addr4 = SDW_DPN_HCTRL_B0(t_params->port_num);
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}
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/* Program DPN_OffsetCtrl2 registers */
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ret = sdw_write(slave, addr1, t_params->offset2);
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if (ret < 0) {
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dev_err(bus->dev, "DPN_OffsetCtrl2 register write failed");
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return ret;
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}
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/* Program DPN_BlockCtrl3 register */
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ret = sdw_write(slave, addr2, t_params->blk_pkg_mode);
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if (ret < 0) {
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dev_err(bus->dev, "DPN_BlockCtrl3 register write failed");
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return ret;
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}
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/*
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* Data ports are FULL, SIMPLE and REDUCED. This function handles
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* FULL and REDUCED only and and beyond this point only FULL is
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* handled, so bail out if we are not FULL data port type
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*/
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if (type != SDW_DPN_FULL)
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return ret;
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/* Program DPN_SampleCtrl2 register */
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wbuf = (t_params->sample_interval - 1);
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wbuf &= SDW_DPN_SAMPLECTRL_HIGH;
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wbuf >>= SDW_REG_SHIFT(SDW_DPN_SAMPLECTRL_HIGH);
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ret = sdw_write(slave, addr3, wbuf);
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if (ret < 0) {
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dev_err(bus->dev, "DPN_SampleCtrl2 register write failed");
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return ret;
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}
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/* Program DPN_HCtrl register */
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wbuf = t_params->hstart;
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wbuf <<= SDW_REG_SHIFT(SDW_DPN_HCTRL_HSTART);
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wbuf |= t_params->hstop;
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ret = sdw_write(slave, addr4, wbuf);
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if (ret < 0)
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dev_err(bus->dev, "DPN_HCtrl register write failed");
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return ret;
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}
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static int sdw_program_slave_port_params(struct sdw_bus *bus,
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struct sdw_slave_runtime *s_rt,
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struct sdw_port_runtime *p_rt)
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{
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struct sdw_transport_params *t_params = &p_rt->transport_params;
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struct sdw_port_params *p_params = &p_rt->port_params;
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struct sdw_slave_prop *slave_prop = &s_rt->slave->prop;
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u32 addr1, addr2, addr3, addr4, addr5, addr6;
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struct sdw_dpn_prop *dpn_prop;
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int ret;
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u8 wbuf;
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dpn_prop = sdw_get_slave_dpn_prop(s_rt->slave,
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s_rt->direction,
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t_params->port_num);
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if (!dpn_prop)
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return -EINVAL;
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addr1 = SDW_DPN_PORTCTRL(t_params->port_num);
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addr2 = SDW_DPN_BLOCKCTRL1(t_params->port_num);
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if (bus->params.next_bank) {
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addr3 = SDW_DPN_SAMPLECTRL1_B1(t_params->port_num);
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addr4 = SDW_DPN_OFFSETCTRL1_B1(t_params->port_num);
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addr5 = SDW_DPN_BLOCKCTRL2_B1(t_params->port_num);
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addr6 = SDW_DPN_LANECTRL_B1(t_params->port_num);
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} else {
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addr3 = SDW_DPN_SAMPLECTRL1_B0(t_params->port_num);
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addr4 = SDW_DPN_OFFSETCTRL1_B0(t_params->port_num);
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addr5 = SDW_DPN_BLOCKCTRL2_B0(t_params->port_num);
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addr6 = SDW_DPN_LANECTRL_B0(t_params->port_num);
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}
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/* Program DPN_PortCtrl register */
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wbuf = p_params->data_mode << SDW_REG_SHIFT(SDW_DPN_PORTCTRL_DATAMODE);
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wbuf |= p_params->flow_mode;
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ret = sdw_update(s_rt->slave, addr1, 0xF, wbuf);
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if (ret < 0) {
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dev_err(&s_rt->slave->dev,
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"DPN_PortCtrl register write failed for port %d",
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t_params->port_num);
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return ret;
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}
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/* Program DPN_BlockCtrl1 register */
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ret = sdw_write(s_rt->slave, addr2, (p_params->bps - 1));
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if (ret < 0) {
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dev_err(&s_rt->slave->dev,
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"DPN_BlockCtrl1 register write failed for port %d",
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t_params->port_num);
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return ret;
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}
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/* Program DPN_SampleCtrl1 register */
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wbuf = (t_params->sample_interval - 1) & SDW_DPN_SAMPLECTRL_LOW;
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ret = sdw_write(s_rt->slave, addr3, wbuf);
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if (ret < 0) {
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dev_err(&s_rt->slave->dev,
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"DPN_SampleCtrl1 register write failed for port %d",
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t_params->port_num);
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return ret;
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}
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/* Program DPN_OffsetCtrl1 registers */
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ret = sdw_write(s_rt->slave, addr4, t_params->offset1);
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if (ret < 0) {
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dev_err(&s_rt->slave->dev,
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"DPN_OffsetCtrl1 register write failed for port %d",
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t_params->port_num);
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return ret;
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}
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/* Program DPN_BlockCtrl2 register*/
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if (t_params->blk_grp_ctrl_valid) {
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ret = sdw_write(s_rt->slave, addr5, t_params->blk_grp_ctrl);
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if (ret < 0) {
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dev_err(&s_rt->slave->dev,
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"DPN_BlockCtrl2 reg write failed for port %d",
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t_params->port_num);
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return ret;
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}
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}
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/* program DPN_LaneCtrl register */
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if (slave_prop->lane_control_support) {
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ret = sdw_write(s_rt->slave, addr6, t_params->lane_ctrl);
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if (ret < 0) {
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dev_err(&s_rt->slave->dev,
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"DPN_LaneCtrl register write failed for port %d",
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t_params->port_num);
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return ret;
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}
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}
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if (dpn_prop->type != SDW_DPN_SIMPLE) {
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ret = _sdw_program_slave_port_params(bus, s_rt->slave,
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t_params, dpn_prop->type);
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if (ret < 0)
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dev_err(&s_rt->slave->dev,
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"Transport reg write failed for port: %d",
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t_params->port_num);
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}
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return ret;
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}
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static int sdw_program_master_port_params(struct sdw_bus *bus,
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struct sdw_port_runtime *p_rt)
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{
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int ret;
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/*
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* we need to set transport and port parameters for the port.
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* Transport parameters refers to the smaple interval, offsets and
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* hstart/stop etc of the data. Port parameters refers to word
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* length, flow mode etc of the port
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*/
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ret = bus->port_ops->dpn_set_port_transport_params(bus,
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&p_rt->transport_params,
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bus->params.next_bank);
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if (ret < 0)
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return ret;
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return bus->port_ops->dpn_set_port_params(bus,
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&p_rt->port_params,
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bus->params.next_bank);
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}
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/**
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* sdw_program_port_params() - Programs transport parameters of Master(s)
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* and Slave(s)
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*
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* @m_rt: Master stream runtime
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*/
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static int sdw_program_port_params(struct sdw_master_runtime *m_rt)
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{
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struct sdw_slave_runtime *s_rt = NULL;
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struct sdw_bus *bus = m_rt->bus;
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struct sdw_port_runtime *p_rt;
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int ret = 0;
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/* Program transport & port parameters for Slave(s) */
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list_for_each_entry(s_rt, &m_rt->slave_rt_list, m_rt_node) {
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list_for_each_entry(p_rt, &s_rt->port_list, port_node) {
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ret = sdw_program_slave_port_params(bus, s_rt, p_rt);
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if (ret < 0)
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return ret;
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}
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}
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/* Program transport & port parameters for Master(s) */
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list_for_each_entry(p_rt, &m_rt->port_list, port_node) {
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ret = sdw_program_master_port_params(bus, p_rt);
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if (ret < 0)
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return ret;
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}
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return 0;
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}
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/**
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* sdw_release_stream() - Free the assigned stream runtime
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*
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@ -498,3 +727,36 @@ error:
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return ret;
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}
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EXPORT_SYMBOL(sdw_stream_add_slave);
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/**
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* sdw_get_slave_dpn_prop() - Get Slave port capabilities
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*
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* @slave: Slave handle
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* @direction: Data direction.
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* @port_num: Port number
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*/
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struct sdw_dpn_prop *sdw_get_slave_dpn_prop(struct sdw_slave *slave,
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enum sdw_data_direction direction,
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unsigned int port_num)
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{
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struct sdw_dpn_prop *dpn_prop;
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u8 num_ports;
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int i;
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if (direction == SDW_DATA_DIR_TX) {
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num_ports = hweight32(slave->prop.source_ports);
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dpn_prop = slave->prop.src_dpn_prop;
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} else {
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num_ports = hweight32(slave->prop.sink_ports);
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dpn_prop = slave->prop.sink_dpn_prop;
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}
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for (i = 0; i < num_ports; i++) {
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dpn_prop = &dpn_prop[i];
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if (dpn_prop->num == port_num)
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return &dpn_prop[i];
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}
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return NULL;
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}
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@ -367,7 +367,30 @@ struct sdw_slave_intr_status {
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};
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/**
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* struct sdw_slave_ops - Slave driver callback ops
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* sdw_reg_bank - SoundWire register banks
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* @SDW_BANK0: Soundwire register bank 0
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* @SDW_BANK1: Soundwire register bank 1
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*/
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enum sdw_reg_bank {
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SDW_BANK0,
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SDW_BANK1,
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};
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/**
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* struct sdw_bus_params: Structure holding bus configuration
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*
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* @curr_bank: Current bank in use (BANK0/BANK1)
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* @next_bank: Next bank to use (BANK0/BANK1). next_bank will always be
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* set to !curr_bank
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*/
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struct sdw_bus_params {
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enum sdw_reg_bank curr_bank;
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enum sdw_reg_bank next_bank;
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};
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/**
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* struct sdw_slave_ops: Slave driver callback ops
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*
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* @read_prop: Read Slave properties
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* @interrupt_callback: Device interrupt notification (invoked in thread
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* context)
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@ -482,6 +505,24 @@ struct sdw_transport_params {
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unsigned int lane_ctrl;
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};
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/**
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* struct sdw_master_port_ops: Callback functions from bus to Master
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* driver to set Master Data ports.
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*
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* @dpn_set_port_params: Set the Port parameters for the Master Port.
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* Mandatory callback
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* @dpn_set_port_transport_params: Set transport parameters for the Master
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* Port. Mandatory callback
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*/
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struct sdw_master_port_ops {
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int (*dpn_set_port_params)(struct sdw_bus *bus,
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struct sdw_port_params *port_params,
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unsigned int bank);
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int (*dpn_set_port_transport_params)(struct sdw_bus *bus,
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struct sdw_transport_params *transport_params,
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enum sdw_reg_bank bank);
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};
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struct sdw_msg;
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/**
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@ -525,6 +566,8 @@ struct sdw_master_ops {
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* @bus_lock: bus lock
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* @msg_lock: message lock
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* @ops: Master callback ops
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* @port_ops: Master port callback ops
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* @params: Current bus parameters
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* @prop: Master properties
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* @m_rt_list: List of Master instance of all stream(s) running on Bus. This
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* is used to compute and program bus bandwidth, clock, frame shape,
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@ -540,6 +583,8 @@ struct sdw_bus {
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struct mutex bus_lock;
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struct mutex msg_lock;
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const struct sdw_master_ops *ops;
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const struct sdw_master_port_ops *port_ops;
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struct sdw_bus_params params;
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struct sdw_master_prop prop;
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struct list_head m_rt_list;
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struct sdw_defer defer_msg;
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