dw_dmac: allocate dma descriptors from DMA_COHERENT memory
Currently descriptors are allocated from normal cacheable memory and that slows down filling the descriptors, as we need to call cache_coherency routines afterwards. It would be better to allocate memory for these descriptors from DMA_COHERENT memory. This would make code much cleaner too. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Tested-by: Mika Westerberg <mika.westerberg@linux.intel.com> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
This commit is contained in:
Andy Shevchenko
Vinod Koul
Родитель
855372c013
Коммит
f8122a82d2
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@ -14,6 +14,7 @@
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#include <linux/delay.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmapool.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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@ -91,14 +92,6 @@ static inline unsigned int dwc_get_data_width(struct dma_chan *chan, int master)
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/*----------------------------------------------------------------------*/
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/*
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* Because we're not relying on writeback from the controller (it may not
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* even be configured into the core!) we don't need to use dma_pool. These
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* descriptors -- and associated data -- are cacheable. We do need to make
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* sure their dcache entries are written back before handing them off to
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* the controller, though.
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*/
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static struct device *chan2dev(struct dma_chan *chan)
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{
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return &chan->dev->device;
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@ -137,19 +130,6 @@ static struct dw_desc *dwc_desc_get(struct dw_dma_chan *dwc)
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return ret;
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}
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static void dwc_sync_desc_for_cpu(struct dw_dma_chan *dwc, struct dw_desc *desc)
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{
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struct dw_desc *child;
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list_for_each_entry(child, &desc->tx_list, desc_node)
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dma_sync_single_for_cpu(chan2parent(&dwc->chan),
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child->txd.phys, sizeof(child->lli),
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DMA_TO_DEVICE);
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dma_sync_single_for_cpu(chan2parent(&dwc->chan),
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desc->txd.phys, sizeof(desc->lli),
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DMA_TO_DEVICE);
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}
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/*
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* Move a descriptor, including any children, to the free list.
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* `desc' must not be on any lists.
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@ -161,8 +141,6 @@ static void dwc_desc_put(struct dw_dma_chan *dwc, struct dw_desc *desc)
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if (desc) {
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struct dw_desc *child;
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dwc_sync_desc_for_cpu(dwc, desc);
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spin_lock_irqsave(&dwc->lock, flags);
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list_for_each_entry(child, &desc->tx_list, desc_node)
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dev_vdbg(chan2dev(&dwc->chan),
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@ -335,8 +313,6 @@ dwc_descriptor_complete(struct dw_dma_chan *dwc, struct dw_desc *desc,
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param = txd->callback_param;
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}
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dwc_sync_desc_for_cpu(dwc, desc);
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/* async_tx_ack */
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list_for_each_entry(child, &desc->tx_list, desc_node)
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async_tx_ack(&child->txd);
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@ -770,25 +746,17 @@ dwc_prep_dma_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
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first = desc;
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} else {
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prev->lli.llp = desc->txd.phys;
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dma_sync_single_for_device(chan2parent(chan),
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prev->txd.phys, sizeof(prev->lli),
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DMA_TO_DEVICE);
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list_add_tail(&desc->desc_node,
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&first->tx_list);
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}
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prev = desc;
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}
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if (flags & DMA_PREP_INTERRUPT)
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/* Trigger interrupt after last block */
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prev->lli.ctllo |= DWC_CTLL_INT_EN;
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prev->lli.llp = 0;
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dma_sync_single_for_device(chan2parent(chan),
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prev->txd.phys, sizeof(prev->lli),
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DMA_TO_DEVICE);
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first->txd.flags = flags;
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first->len = len;
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@ -876,10 +844,6 @@ slave_sg_todev_fill_desc:
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first = desc;
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} else {
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prev->lli.llp = desc->txd.phys;
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dma_sync_single_for_device(chan2parent(chan),
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prev->txd.phys,
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sizeof(prev->lli),
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DMA_TO_DEVICE);
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list_add_tail(&desc->desc_node,
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&first->tx_list);
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}
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@ -938,10 +902,6 @@ slave_sg_fromdev_fill_desc:
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first = desc;
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} else {
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prev->lli.llp = desc->txd.phys;
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dma_sync_single_for_device(chan2parent(chan),
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prev->txd.phys,
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sizeof(prev->lli),
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DMA_TO_DEVICE);
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list_add_tail(&desc->desc_node,
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&first->tx_list);
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}
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@ -961,10 +921,6 @@ slave_sg_fromdev_fill_desc:
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prev->lli.ctllo |= DWC_CTLL_INT_EN;
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prev->lli.llp = 0;
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dma_sync_single_for_device(chan2parent(chan),
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prev->txd.phys, sizeof(prev->lli),
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DMA_TO_DEVICE);
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first->len = total_len;
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return &first->txd;
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@ -1118,7 +1074,6 @@ static int dwc_alloc_chan_resources(struct dma_chan *chan)
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struct dw_desc *desc;
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int i;
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unsigned long flags;
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int ret;
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dev_vdbg(chan2dev(chan), "%s\n", __func__);
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@ -1139,21 +1094,21 @@ static int dwc_alloc_chan_resources(struct dma_chan *chan)
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spin_lock_irqsave(&dwc->lock, flags);
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i = dwc->descs_allocated;
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while (dwc->descs_allocated < NR_DESCS_PER_CHANNEL) {
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dma_addr_t phys;
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spin_unlock_irqrestore(&dwc->lock, flags);
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desc = kzalloc(sizeof(struct dw_desc), GFP_KERNEL);
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desc = dma_pool_alloc(dw->desc_pool, GFP_ATOMIC, &phys);
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if (!desc)
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goto err_desc_alloc;
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memset(desc, 0, sizeof(struct dw_desc));
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INIT_LIST_HEAD(&desc->tx_list);
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dma_async_tx_descriptor_init(&desc->txd, chan);
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desc->txd.tx_submit = dwc_tx_submit;
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desc->txd.flags = DMA_CTRL_ACK;
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desc->txd.phys = dma_map_single(chan2parent(chan), &desc->lli,
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sizeof(desc->lli), DMA_TO_DEVICE);
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ret = dma_mapping_error(chan2parent(chan), desc->txd.phys);
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if (ret)
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goto err_desc_alloc;
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desc->txd.phys = phys;
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dwc_desc_put(dwc, desc);
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@ -1168,8 +1123,6 @@ static int dwc_alloc_chan_resources(struct dma_chan *chan)
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return i;
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err_desc_alloc:
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kfree(desc);
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dev_info(chan2dev(chan), "only allocated %d descriptors\n", i);
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return i;
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@ -1204,9 +1157,7 @@ static void dwc_free_chan_resources(struct dma_chan *chan)
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list_for_each_entry_safe(desc, _desc, &list, desc_node) {
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dev_vdbg(chan2dev(chan), " freeing descriptor %p\n", desc);
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dma_unmap_single(chan2parent(chan), desc->txd.phys,
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sizeof(desc->lli), DMA_TO_DEVICE);
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kfree(desc);
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dma_pool_free(dw->desc_pool, desc, desc->txd.phys);
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}
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dev_vdbg(chan2dev(chan), "%s: done\n", __func__);
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@ -1451,20 +1402,14 @@ struct dw_cyclic_desc *dw_dma_cyclic_prep(struct dma_chan *chan,
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desc->lli.ctlhi = (period_len >> reg_width);
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cdesc->desc[i] = desc;
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if (last) {
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if (last)
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last->lli.llp = desc->txd.phys;
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dma_sync_single_for_device(chan2parent(chan),
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last->txd.phys, sizeof(last->lli),
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DMA_TO_DEVICE);
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}
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last = desc;
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}
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/* lets make a cyclic list */
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last->lli.llp = cdesc->desc[0]->txd.phys;
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dma_sync_single_for_device(chan2parent(chan), last->txd.phys,
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sizeof(last->lli), DMA_TO_DEVICE);
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dev_dbg(chan2dev(&dwc->chan), "cyclic prepared buf 0x%llx len %zu "
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"period %zu periods %d\n", (unsigned long long)buf_addr,
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@ -1722,6 +1667,14 @@ static int dw_probe(struct platform_device *pdev)
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platform_set_drvdata(pdev, dw);
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/* create a pool of consistent memory blocks for hardware descriptors */
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dw->desc_pool = dmam_pool_create("dw_dmac_desc_pool", &pdev->dev,
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sizeof(struct dw_desc), 4, 0);
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if (!dw->desc_pool) {
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dev_err(&pdev->dev, "No memory for descriptors dma pool\n");
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return -ENOMEM;
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}
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tasklet_init(&dw->tasklet, dw_dma_tasklet, (unsigned long)dw);
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INIT_LIST_HEAD(&dw->dma.channels);
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@ -235,6 +235,7 @@ static inline struct dw_dma_chan *to_dw_dma_chan(struct dma_chan *chan)
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struct dw_dma {
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struct dma_device dma;
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void __iomem *regs;
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struct dma_pool *desc_pool;
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struct tasklet_struct tasklet;
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struct clk *clk;
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