net: mvpp2: initialize the GoP
The patch adds GoP (group of ports) initialization functions. The mvpp2 driver was relying on the firmware/bootloader initialization; this patch moves this setup to the mvpp2 driver. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Tested-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Antoine Ténart
David S. Miller
Родитель
76eb1b1de5
Коммит
f84bf386f3
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@ -18,6 +18,7 @@
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#include <linux/inetdevice.h>
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#include <linux/mbus.h>
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#include <linux/module.h>
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#include <linux/mfd/syscon.h>
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#include <linux/interrupt.h>
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#include <linux/cpumask.h>
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#include <linux/of.h>
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@ -30,6 +31,7 @@
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#include <linux/clk.h>
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#include <linux/hrtimer.h>
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#include <linux/ktime.h>
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#include <linux/regmap.h>
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#include <uapi/linux/ppp_defs.h>
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#include <net/ip.h>
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#include <net/ipv6.h>
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@ -388,6 +390,38 @@
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#define MVPP2_QUEUE_NEXT_DESC(q, index) \
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(((index) < (q)->last_desc) ? ((index) + 1) : 0)
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/* XPCS registers. PPv2.2 only */
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#define MVPP22_MPCS_BASE(port) (0x7000 + (port) * 0x1000)
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#define MVPP22_MPCS_CTRL 0x14
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#define MVPP22_MPCS_CTRL_FWD_ERR_CONN BIT(10)
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#define MVPP22_MPCS_CLK_RESET 0x14c
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#define MAC_CLK_RESET_SD_TX BIT(0)
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#define MAC_CLK_RESET_SD_RX BIT(1)
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#define MAC_CLK_RESET_MAC BIT(2)
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#define MVPP22_MPCS_CLK_RESET_DIV_RATIO(n) ((n) << 4)
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#define MVPP22_MPCS_CLK_RESET_DIV_SET BIT(11)
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/* XPCS registers. PPv2.2 only */
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#define MVPP22_XPCS_BASE(port) (0x7400 + (port) * 0x1000)
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#define MVPP22_XPCS_CFG0 0x0
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#define MVPP22_XPCS_CFG0_PCS_MODE(n) ((n) << 3)
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#define MVPP22_XPCS_CFG0_ACTIVE_LANE(n) ((n) << 5)
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/* System controller registers. Accessed through a regmap. */
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#define GENCONF_SOFT_RESET1 0x1108
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#define GENCONF_SOFT_RESET1_GOP BIT(6)
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#define GENCONF_PORT_CTRL0 0x1110
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#define GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT BIT(1)
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#define GENCONF_PORT_CTRL0_RX_DATA_SAMPLE BIT(29)
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#define GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR BIT(31)
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#define GENCONF_PORT_CTRL1 0x1114
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#define GENCONF_PORT_CTRL1_EN(p) BIT(p)
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#define GENCONF_PORT_CTRL1_RESET(p) (BIT(p) << 28)
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#define GENCONF_CTRL0 0x1120
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#define GENCONF_CTRL0_PORT0_RGMII BIT(0)
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#define GENCONF_CTRL0_PORT1_RGMII_MII BIT(1)
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#define GENCONF_CTRL0_PORT1_RGMII BIT(2)
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/* Various constants */
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/* Coalescing */
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@ -731,6 +765,11 @@ struct mvpp2 {
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*/
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void __iomem *swth_base[MVPP2_MAX_THREADS];
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/* On PPv2.2, some port control registers are located into the system
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* controller space. These registers are accessible through a regmap.
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*/
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struct regmap *sysctrl_base;
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/* Common clocks */
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struct clk *pp_clk;
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struct clk *gop_clk;
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@ -4259,6 +4298,123 @@ mvpp2_shared_interrupt_mask_unmask(struct mvpp2_port *port, bool mask)
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/* Port configuration routines */
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static void mvpp22_gop_init_rgmii(struct mvpp2_port *port)
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{
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struct mvpp2 *priv = port->priv;
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u32 val;
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regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
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val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT;
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regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
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regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);
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if (port->gop_id == 2)
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val |= GENCONF_CTRL0_PORT0_RGMII | GENCONF_CTRL0_PORT1_RGMII;
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else if (port->gop_id == 3)
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val |= GENCONF_CTRL0_PORT1_RGMII_MII;
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regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);
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}
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static void mvpp22_gop_init_sgmii(struct mvpp2_port *port)
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{
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struct mvpp2 *priv = port->priv;
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u32 val;
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regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
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val |= GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT |
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GENCONF_PORT_CTRL0_RX_DATA_SAMPLE;
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regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
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if (port->gop_id > 1) {
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regmap_read(priv->sysctrl_base, GENCONF_CTRL0, &val);
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if (port->gop_id == 2)
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val &= ~GENCONF_CTRL0_PORT0_RGMII;
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else if (port->gop_id == 3)
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val &= ~GENCONF_CTRL0_PORT1_RGMII_MII;
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regmap_write(priv->sysctrl_base, GENCONF_CTRL0, val);
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}
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}
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static void mvpp22_gop_init_10gkr(struct mvpp2_port *port)
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{
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struct mvpp2 *priv = port->priv;
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void __iomem *mpcs = priv->iface_base + MVPP22_MPCS_BASE(port->gop_id);
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void __iomem *xpcs = priv->iface_base + MVPP22_XPCS_BASE(port->gop_id);
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u32 val;
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/* XPCS */
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val = readl(xpcs + MVPP22_XPCS_CFG0);
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val &= ~(MVPP22_XPCS_CFG0_PCS_MODE(0x3) |
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MVPP22_XPCS_CFG0_ACTIVE_LANE(0x3));
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val |= MVPP22_XPCS_CFG0_ACTIVE_LANE(2);
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writel(val, xpcs + MVPP22_XPCS_CFG0);
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/* MPCS */
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val = readl(mpcs + MVPP22_MPCS_CTRL);
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val &= ~MVPP22_MPCS_CTRL_FWD_ERR_CONN;
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writel(val, mpcs + MVPP22_MPCS_CTRL);
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val = readl(mpcs + MVPP22_MPCS_CLK_RESET);
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val &= ~(MVPP22_MPCS_CLK_RESET_DIV_RATIO(0x7) | MAC_CLK_RESET_MAC |
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MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX);
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val |= MVPP22_MPCS_CLK_RESET_DIV_RATIO(1);
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writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
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val &= ~MVPP22_MPCS_CLK_RESET_DIV_SET;
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val |= MAC_CLK_RESET_MAC | MAC_CLK_RESET_SD_RX | MAC_CLK_RESET_SD_TX;
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writel(val, mpcs + MVPP22_MPCS_CLK_RESET);
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}
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static int mvpp22_gop_init(struct mvpp2_port *port)
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{
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struct mvpp2 *priv = port->priv;
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u32 val;
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if (!priv->sysctrl_base)
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return 0;
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switch (port->phy_interface) {
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_RGMII_RXID:
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case PHY_INTERFACE_MODE_RGMII_TXID:
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if (port->gop_id == 0)
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goto invalid_conf;
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mvpp22_gop_init_rgmii(port);
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break;
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case PHY_INTERFACE_MODE_SGMII:
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mvpp22_gop_init_sgmii(port);
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break;
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case PHY_INTERFACE_MODE_10GKR:
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if (port->gop_id != 0)
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goto invalid_conf;
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mvpp22_gop_init_10gkr(port);
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break;
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default:
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goto unsupported_conf;
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}
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regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL1, &val);
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val |= GENCONF_PORT_CTRL1_RESET(port->gop_id) |
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GENCONF_PORT_CTRL1_EN(port->gop_id);
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regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL1, val);
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regmap_read(priv->sysctrl_base, GENCONF_PORT_CTRL0, &val);
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val |= GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR;
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regmap_write(priv->sysctrl_base, GENCONF_PORT_CTRL0, val);
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regmap_read(priv->sysctrl_base, GENCONF_SOFT_RESET1, &val);
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val |= GENCONF_SOFT_RESET1_GOP;
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regmap_write(priv->sysctrl_base, GENCONF_SOFT_RESET1, val);
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unsupported_conf:
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return 0;
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invalid_conf:
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netdev_err(port->dev, "Invalid port configuration\n");
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return -EINVAL;
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}
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static void mvpp2_port_mii_gmac_configure_mode(struct mvpp2_port *port)
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{
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u32 val;
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@ -6105,6 +6261,9 @@ static void mvpp2_start_dev(struct mvpp2_port *port)
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/* Enable interrupts on all CPUs */
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mvpp2_interrupts_enable(port);
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if (port->priv->hw_version == MVPP22)
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mvpp22_gop_init(port);
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mvpp2_port_mii_set(port);
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mvpp2_port_enable(port);
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phy_start(ndev->phydev);
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@ -7350,6 +7509,17 @@ static int mvpp2_probe(struct platform_device *pdev)
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priv->iface_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(priv->iface_base))
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return PTR_ERR(priv->iface_base);
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priv->sysctrl_base =
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syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
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"marvell,system-controller");
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if (IS_ERR(priv->sysctrl_base))
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/* The system controller regmap is optional for dt
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* compatibility reasons. When not provided, the
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* configuration of the GoP relies on the
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* firmware/bootloader.
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*/
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priv->sysctrl_base = NULL;
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}
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for (i = 0; i < MVPP2_MAX_THREADS; i++) {
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