staging: comedi: ni_stc.h: tidy up AI_Trigger_Select_Register and bits
Rename the CamelCase. Use the BIT() macro to define the bits. Tidy up ni_ai_cmd() by using a local var to set the common bits and programming the register in the common code path. Signed-off-by: H Hartley Sweeten <hsweeten@visionengravers.com> Reviewed-by: Ian Abbott <abbotti@mev.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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3e9088929f
Коммит
f878071a44
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@ -358,7 +358,7 @@ static const struct mio_regmap m_series_stc_write_regmap[] = {
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[NISTC_AI_OUT_CTRL_REG] = { 0x178, 2 },
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[NISTC_ATRIG_ETC_REG] = { 0x17a, 2 },
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[NISTC_AI_START_STOP_REG] = { 0x17c, 2 },
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[AI_Trigger_Select_Register] = { 0x17e, 2 },
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[NISTC_AI_TRIG_SEL_REG] = { 0x17e, 2 },
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[AI_DIV_Load_A_Register] = { 0x180, 4 },
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[AO_Start_Select_Register] = { 0x184, 2 },
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[AO_Trigger_Select_Register] = { 0x186, 2 },
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@ -2248,6 +2248,7 @@ static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
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int start_stop_select = 0;
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unsigned int stop_count;
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int interrupt_a_enable = 0;
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unsigned ai_trig;
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if (dev->irq == 0) {
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dev_err(dev->class_dev, "cannot run command without an irq\n");
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@ -2265,29 +2266,25 @@ static int ni_ai_cmd(struct comedi_device *dev, struct comedi_subdevice *s)
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devpriv->an_trig_etc_reg &= ~NISTC_ATRIG_ETC_ENA;
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ni_stc_writew(dev, devpriv->an_trig_etc_reg, NISTC_ATRIG_ETC_REG);
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ai_trig = NISTC_AI_TRIG_START2_SEL(0) | NISTC_AI_TRIG_START1_SYNC;
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switch (cmd->start_src) {
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case TRIG_INT:
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case TRIG_NOW:
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ni_stc_writew(dev,
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AI_START2_Select(0) |
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AI_START1_Sync | AI_START1_Edge |
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AI_START1_Select(0),
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AI_Trigger_Select_Register);
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ai_trig |= NISTC_AI_TRIG_START1_EDGE |
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NISTC_AI_TRIG_START1_SEL(0),
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NISTC_AI_TRIG_SEL_REG;
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break;
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case TRIG_EXT:
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{
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int chan = CR_CHAN(cmd->start_arg);
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unsigned int bits = AI_START2_Select(0) |
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AI_START1_Sync | AI_START1_Select(chan + 1);
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ai_trig |= NISTC_AI_TRIG_START1_SEL(CR_CHAN(cmd->start_arg) +
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1);
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if (cmd->start_arg & CR_INVERT)
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bits |= AI_START1_Polarity;
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if (cmd->start_arg & CR_EDGE)
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bits |= AI_START1_Edge;
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ni_stc_writew(dev, bits, AI_Trigger_Select_Register);
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break;
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}
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if (cmd->start_arg & CR_INVERT)
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ai_trig |= NISTC_AI_TRIG_START1_POLARITY;
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if (cmd->start_arg & CR_EDGE)
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ai_trig |= NISTC_AI_TRIG_START1_EDGE;
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break;
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}
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ni_stc_writew(dev, ai_trig, NISTC_AI_TRIG_SEL_REG);
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mode2 &= ~NISTC_AI_MODE2_PRE_TRIGGER;
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mode2 &= ~NISTC_AI_MODE2_SC_INIT_LOAD_SRC;
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@ -326,6 +326,16 @@
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#define NISTC_AI_START_EDGE BIT(5)
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#define NISTC_AI_START_SEL(x) (((x) & 0x1f) << 0)
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#define NISTC_AI_TRIG_SEL_REG 63
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#define NISTC_AI_TRIG_START1_POLARITY BIT(15)
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#define NISTC_AI_TRIG_START2_POLARITY BIT(14)
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#define NISTC_AI_TRIG_START2_SYNC BIT(13)
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#define NISTC_AI_TRIG_START2_EDGE BIT(12)
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#define NISTC_AI_TRIG_START2_SEL(x) (((x) & 0x1f) << 7)
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#define NISTC_AI_TRIG_START1_SYNC BIT(6)
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#define NISTC_AI_TRIG_START1_EDGE BIT(5)
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#define NISTC_AI_TRIG_START1_SEL(x) (((x) & 0x1f) << 0)
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#define AI_Status_1_Register 2
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#define Interrupt_A_St 0x8000
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#define AI_FIFO_Full_St 0x4000
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@ -384,16 +394,6 @@ enum Joint_Status_2_Bits {
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#define AO_BC_Save_Registers 18
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#define AO_UC_Save_Registers 20
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#define AI_Trigger_Select_Register 63
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#define AI_START1_Polarity _bit15
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#define AI_START2_Polarity _bit14
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#define AI_START2_Sync _bit13
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#define AI_START2_Edge _bit12
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#define AI_START2_Select(a) (((a) & 0x1f) << 7)
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#define AI_START1_Sync _bit6
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#define AI_START1_Edge _bit5
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#define AI_START1_Select(a) ((a) & 0x1f)
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#define AI_DIV_Load_A_Register 64
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#define AO_Start_Select_Register 66
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