IXP4xx: move Coyote platform macros to the platform code.
Signed-off-by: Krzysztof Hałasa <khc@pm.waw.pl>
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Коммит
f89f44902a
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@ -18,13 +18,21 @@
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#include <linux/pci.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/irq.h>
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#include <asm/mach-types.h>
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#include <asm/mach-types.h>
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#include <mach/hardware.h>
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#include <mach/hardware.h>
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#include <asm/irq.h>
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#include <asm/irq.h>
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#include <asm/mach/pci.h>
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#include <asm/mach/pci.h>
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#define COYOTE_PCI_SLOT0_DEVID 14
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#define COYOTE_PCI_SLOT1_DEVID 15
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/* PCI controller GPIO to IRQ pin mappings */
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#define COYOTE_PCI_SLOT0_PIN 6
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#define COYOTE_PCI_SLOT1_PIN 11
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#define IRQ_COYOTE_PCI_SLOT0 IRQ_IXP4XX_GPIO6
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#define IRQ_COYOTE_PCI_SLOT1 IRQ_IXP4XX_GPIO11
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void __init coyote_pci_preinit(void)
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void __init coyote_pci_preinit(void)
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{
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{
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set_irq_type(IRQ_COYOTE_PCI_SLOT0, IRQ_TYPE_LEVEL_LOW);
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set_irq_type(IRQ_COYOTE_PCI_SLOT0, IRQ_TYPE_LEVEL_LOW);
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@ -25,6 +25,15 @@
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#include <asm/mach/arch.h>
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#include <asm/mach/arch.h>
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#include <asm/mach/flash.h>
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#include <asm/mach/flash.h>
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#define COYOTE_IDE_BASE_PHYS IXP4XX_EXP_BUS_BASE(3)
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#define COYOTE_IDE_BASE_VIRT 0xFFFE1000
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#define COYOTE_IDE_REGION_SIZE 0x1000
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#define COYOTE_IDE_DATA_PORT 0xFFFE10E0
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#define COYOTE_IDE_CTRL_PORT 0xFFFE10FC
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#define COYOTE_IDE_ERROR_PORT 0xFFFE10E2
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#define IRQ_COYOTE_IDE IRQ_IXP4XX_GPIO5
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static struct flash_platform_data coyote_flash_data = {
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static struct flash_platform_data coyote_flash_data = {
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.map_name = "cfi_probe",
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.map_name = "cfi_probe",
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.width = 2,
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.width = 2,
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@ -1,33 +0,0 @@
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/*
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* arch/arm/mach-ixp4xx/include/mach/coyote.h
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*
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* ADI Engineering platform specific definitions
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*
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* Author: Deepak Saxena <dsaxena@plexity.net>
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*
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* Copyright 2004 (c) MontaVista, Software, Inc.
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#ifndef __ASM_ARCH_HARDWARE_H__
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#error "Do not include this directly, instead #include <mach/hardware.h>"
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#endif
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/* PCI controller GPIO to IRQ pin mappings */
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#define COYOTE_PCI_SLOT0_PIN 6
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#define COYOTE_PCI_SLOT1_PIN 11
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#define COYOTE_PCI_SLOT0_DEVID 14
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#define COYOTE_PCI_SLOT1_DEVID 15
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#define COYOTE_IDE_BASE_PHYS IXP4XX_EXP_BUS_BASE(3)
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#define COYOTE_IDE_BASE_VIRT 0xFFFE1000
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#define COYOTE_IDE_REGION_SIZE 0x1000
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#define COYOTE_IDE_DATA_PORT 0xFFFE10E0
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#define COYOTE_IDE_CTRL_PORT 0xFFFE10FC
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#define COYOTE_IDE_ERROR_PORT 0xFFFE10E2
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@ -44,7 +44,6 @@
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#include "platform.h"
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#include "platform.h"
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/* Platform specific details */
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/* Platform specific details */
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#include "coyote.h"
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#include "prpmc1100.h"
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#include "prpmc1100.h"
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#include "nslu2.h"
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#include "nslu2.h"
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#include "nas100d.h"
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#include "nas100d.h"
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@ -78,13 +78,6 @@
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#define IRQ_PRPMC1100_PCI_INTC IRQ_IXP4XX_GPIO9
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#define IRQ_PRPMC1100_PCI_INTC IRQ_IXP4XX_GPIO9
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#define IRQ_PRPMC1100_PCI_INTD IRQ_IXP4XX_GPIO8
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#define IRQ_PRPMC1100_PCI_INTD IRQ_IXP4XX_GPIO8
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/*
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* ADI Coyote Board IRQs
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*/
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#define IRQ_COYOTE_PCI_SLOT0 IRQ_IXP4XX_GPIO6
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#define IRQ_COYOTE_PCI_SLOT1 IRQ_IXP4XX_GPIO11
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#define IRQ_COYOTE_IDE IRQ_IXP4XX_GPIO5
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/*
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/*
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* NSLU2 board IRQs
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* NSLU2 board IRQs
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*/
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*/
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