perf vendor events s390: Add cache metrics for z16
Add metrics for s390 z16 - Percentage sourced from Level 2 cache - Percentage sourced from Level 3 on same chip cache - Percentage sourced from Level 4 Local cache on same book - Percentage sourced from Level 4 Remote cache on different book - Percentage sourced from memory For details about the formulas see this documentation: https://www.ibm.com/support/pages/system/files/inline-files/CPU%20MF%20Formulas%20including%20z16%20-%20May%202022_1.pdf Output after: # ./perf stat -M l4rp -- dd if=/dev/zero of=/dev/null bs=10M count=10K .... dd output deleted Performance counter stats for 'dd if=/dev/zero of=/dev/null bs=10M count=10K': 0 IDCW_OFF_DRAWER_CHIP_HIT # 0.00 l4rp 431,866 L1I_DIR_WRITES 2,395 IDCW_OFF_DRAWER_IV 0 ICW_OFF_DRAWER 0 IDCW_OFF_DRAWER_DRAWER_HIT 1,437 DCW_OFF_DRAWER 425,960,793 L1D_DIR_WRITES 12.165030699 seconds time elapsed 0.001037000 seconds user 12.162140000 seconds sys # Signed-off-by: Thomas Richter <tmricht@linux.ibm.com> Acked-by: Ian Rogers <irogers@google.com> Acked-By: Sumanth Korikkar <sumanthk@linux.ibm.com> Cc: Heiko Carstens <hca@linux.ibm.com> Cc: Sven Schnelle <svens@linux.ibm.com> Cc: Vasily Gorbik <gor@linux.ibm.com> Link: https://lore.kernel.org/r/20230313080201.2440201-1-tmricht@linux.ibm.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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"BriefDescription": "Level One Miss per 100 Instructions",
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"BriefDescription": "Level One Miss per 100 Instructions",
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"MetricName": "l1mp",
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"MetricName": "l1mp",
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"MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100"
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"MetricExpr": "((L1I_DIR_WRITES + L1D_DIR_WRITES) / INSTRUCTIONS) * 100"
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},
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{
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"BriefDescription": "Percentage sourced from Level 2 cache",
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"MetricName": "l2p",
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"MetricExpr": "((DCW_REQ + DCW_REQ_IV + ICW_REQ + ICW_REQ_IV) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
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},
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{
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"BriefDescription": "Percentage sourced from Level 3 on same chip cache",
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"MetricName": "l3p",
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"MetricExpr": "((DCW_REQ_CHIP_HIT + DCW_ON_CHIP + DCW_ON_CHIP_IV + DCW_ON_CHIP_CHIP_HIT + ICW_REQ_CHIP_HIT + ICW_ON_CHIP + ICW_ON_CHIP_IV + ICW_ON_CHIP_CHIP_HIT) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
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},
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{
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"BriefDescription": "Percentage sourced from Level 4 Local cache on same book",
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"MetricName": "l4lp",
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"MetricExpr": "((DCW_REQ_DRAWER_HIT + DCW_ON_CHIP_DRAWER_HIT + DCW_ON_MODULE + DCW_ON_DRAWER + IDCW_ON_MODULE_IV + IDCW_ON_MODULE_CHIP_HIT + IDCW_ON_MODULE_DRAWER_HIT + IDCW_ON_DRAWER_IV + IDCW_ON_DRAWER_CHIP_HIT + IDCW_ON_DRAWER_DRAWER_HIT + ICW_REQ_DRAWER_HIT + ICW_ON_CHIP_DRAWER_HIT + ICW_ON_MODULE + ICW_ON_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
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},
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{
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"BriefDescription": "Percentage sourced from Level 4 Remote cache on different book",
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"MetricName": "l4rp",
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"MetricExpr": "((DCW_OFF_DRAWER + IDCW_OFF_DRAWER_IV + IDCW_OFF_DRAWER_CHIP_HIT + IDCW_OFF_DRAWER_DRAWER_HIT + ICW_OFF_DRAWER) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
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},
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{
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"BriefDescription": "Percentage sourced from memory",
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"MetricName": "memp",
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"MetricExpr": "((DCW_ON_CHIP_MEMORY + DCW_ON_MODULE_MEMORY + DCW_ON_DRAWER_MEMORY + DCW_OFF_DRAWER_MEMORY + ICW_ON_CHIP_MEMORY + ICW_ON_MODULE_MEMORY + ICW_ON_DRAWER_MEMORY + ICW_OFF_DRAWER_MEMORY) / (L1I_DIR_WRITES + L1D_DIR_WRITES)) * 100"
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}
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}
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]
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]
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