net/mlx5: Remove extra indirection while storing QPN
The FPGA, SW steering and IPoIB need to have only QPN from the mlx5_core_qp struct, so reduce memory footprint by storing QPN directly. Reviewed-by: Saeed Mahameed <saeedm@mellanox.com> Signed-off-by: Leon Romanovsky <leonro@mellanox.com>
This commit is contained in:
Leon Romanovsky
Родитель
a452e0e436
Коммит
f93f4f4f31
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@ -165,7 +165,7 @@ static void mlx5_fpga_conn_post_send(struct mlx5_fpga_conn *conn,
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ctrl->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
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ctrl->opmod_idx_opcode = cpu_to_be32(((conn->qp.sq.pc & 0xffff) << 8) |
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MLX5_OPCODE_SEND);
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ctrl->qpn_ds = cpu_to_be32(size | (conn->qp.mqp.qpn << 8));
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ctrl->qpn_ds = cpu_to_be32(size | (conn->qp.qpn << 8));
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conn->qp.sq.pc++;
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conn->qp.sq.bufs[ix] = buf;
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@ -588,8 +588,8 @@ static int mlx5_fpga_conn_create_qp(struct mlx5_fpga_conn *conn,
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if (err)
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goto err_sq_bufs;
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conn->qp.mqp.qpn = MLX5_GET(create_qp_out, out, qpn);
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mlx5_fpga_dbg(fdev, "Created QP #0x%x\n", conn->qp.mqp.qpn);
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conn->qp.qpn = MLX5_GET(create_qp_out, out, qpn);
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mlx5_fpga_dbg(fdev, "Created QP #0x%x\n", conn->qp.qpn);
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goto out;
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@ -644,10 +644,9 @@ static void mlx5_fpga_conn_destroy_qp(struct mlx5_fpga_conn *conn)
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{
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struct mlx5_core_dev *dev = conn->fdev->mdev;
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u32 in[MLX5_ST_SZ_DW(destroy_qp_in)] = {};
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struct mlx5_core_qp *qp = &conn->qp.mqp;
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MLX5_SET(destroy_qp_in, in, opcode, MLX5_CMD_OP_DESTROY_QP);
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MLX5_SET(destroy_qp_in, in, qpn, qp->qpn);
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MLX5_SET(destroy_qp_in, in, qpn, conn->qp.qpn);
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mlx5_cmd_exec_in(dev, destroy_qp, in);
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mlx5_fpga_conn_free_recv_bufs(conn);
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@ -662,10 +661,10 @@ static int mlx5_fpga_conn_reset_qp(struct mlx5_fpga_conn *conn)
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struct mlx5_core_dev *mdev = conn->fdev->mdev;
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u32 in[MLX5_ST_SZ_DW(qp_2rst_in)] = {};
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mlx5_fpga_dbg(conn->fdev, "Modifying QP %u to RST\n", conn->qp.mqp.qpn);
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mlx5_fpga_dbg(conn->fdev, "Modifying QP %u to RST\n", conn->qp.qpn);
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MLX5_SET(qp_2rst_in, in, opcode, MLX5_CMD_OP_2RST_QP);
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MLX5_SET(qp_2rst_in, in, qpn, conn->qp.mqp.qpn);
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MLX5_SET(qp_2rst_in, in, qpn, conn->qp.qpn);
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return mlx5_cmd_exec_in(mdev, qp_2rst, in);
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}
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@ -677,7 +676,7 @@ static int mlx5_fpga_conn_init_qp(struct mlx5_fpga_conn *conn)
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struct mlx5_core_dev *mdev = fdev->mdev;
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u32 *qpc;
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mlx5_fpga_dbg(conn->fdev, "Modifying QP %u to INIT\n", conn->qp.mqp.qpn);
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mlx5_fpga_dbg(conn->fdev, "Modifying QP %u to INIT\n", conn->qp.qpn);
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qpc = MLX5_ADDR_OF(rst2init_qp_in, in, qpc);
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@ -691,7 +690,7 @@ static int mlx5_fpga_conn_init_qp(struct mlx5_fpga_conn *conn)
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MLX5_SET64(qpc, qpc, dbr_addr, conn->qp.wq_ctrl.db.dma);
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MLX5_SET(rst2init_qp_in, in, opcode, MLX5_CMD_OP_RST2INIT_QP);
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MLX5_SET(rst2init_qp_in, in, qpn, conn->qp.mqp.qpn);
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MLX5_SET(rst2init_qp_in, in, qpn, conn->qp.qpn);
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return mlx5_cmd_exec_in(mdev, rst2init_qp, in);
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}
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@ -726,7 +725,7 @@ static int mlx5_fpga_conn_rtr_qp(struct mlx5_fpga_conn *conn)
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MLX5_FLD_SZ_BYTES(qpc, primary_address_path.rgid_rip));
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MLX5_SET(init2rtr_qp_in, in, opcode, MLX5_CMD_OP_INIT2RTR_QP);
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MLX5_SET(init2rtr_qp_in, in, qpn, conn->qp.mqp.qpn);
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MLX5_SET(init2rtr_qp_in, in, qpn, conn->qp.qpn);
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return mlx5_cmd_exec_in(mdev, init2rtr_qp, in);
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}
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@ -751,7 +750,7 @@ static int mlx5_fpga_conn_rts_qp(struct mlx5_fpga_conn *conn)
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MLX5_SET(qpc, qpc, rnr_retry, 7); /* Infinite retry if RNR NACK */
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MLX5_SET(rtr2rts_qp_in, in, opcode, MLX5_CMD_OP_RTR2RTS_QP);
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MLX5_SET(rtr2rts_qp_in, in, qpn, conn->qp.mqp.qpn);
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MLX5_SET(rtr2rts_qp_in, in, qpn, conn->qp.qpn);
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MLX5_SET(rtr2rts_qp_in, in, opt_param_mask, MLX5_QP_OPTPAR_RNR_TIMEOUT);
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return mlx5_cmd_exec_in(mdev, rtr2rts_qp, in);
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@ -894,7 +893,7 @@ struct mlx5_fpga_conn *mlx5_fpga_conn_create(struct mlx5_fpga_device *fdev,
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MLX5_SET(fpga_qpc, conn->fpga_qpc, next_rcv_psn, 1);
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MLX5_SET(fpga_qpc, conn->fpga_qpc, next_send_psn, 0);
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MLX5_SET(fpga_qpc, conn->fpga_qpc, pkey, MLX5_FPGA_PKEY);
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MLX5_SET(fpga_qpc, conn->fpga_qpc, remote_qpn, conn->qp.mqp.qpn);
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MLX5_SET(fpga_qpc, conn->fpga_qpc, remote_qpn, conn->qp.qpn);
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MLX5_SET(fpga_qpc, conn->fpga_qpc, rnr_retry, 7);
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MLX5_SET(fpga_qpc, conn->fpga_qpc, retry_count, 7);
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@ -65,7 +65,7 @@ struct mlx5_fpga_conn {
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int sgid_index;
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struct mlx5_wq_qp wq;
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struct mlx5_wq_ctrl wq_ctrl;
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struct mlx5_core_qp mqp;
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u32 qpn;
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struct {
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spinlock_t lock; /* Protects all SQ state */
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unsigned int pc;
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@ -160,7 +160,6 @@ int mlx5i_init_underlay_qp(struct mlx5e_priv *priv)
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{
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struct mlx5_core_dev *mdev = priv->mdev;
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struct mlx5i_priv *ipriv = priv->ppriv;
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struct mlx5_core_qp *qp = &ipriv->qp;
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int ret;
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{
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@ -176,7 +175,7 @@ int mlx5i_init_underlay_qp(struct mlx5e_priv *priv)
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MLX5_SET(qpc, qpc, q_key, IB_DEFAULT_Q_KEY);
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MLX5_SET(rst2init_qp_in, in, opcode, MLX5_CMD_OP_RST2INIT_QP);
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MLX5_SET(rst2init_qp_in, in, qpn, qp->qpn);
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MLX5_SET(rst2init_qp_in, in, qpn, ipriv->qpn);
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ret = mlx5_cmd_exec_in(mdev, rst2init_qp, in);
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if (ret)
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goto err_qp_modify_to_err;
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@ -185,7 +184,7 @@ int mlx5i_init_underlay_qp(struct mlx5e_priv *priv)
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u32 in[MLX5_ST_SZ_DW(init2rtr_qp_in)] = {};
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MLX5_SET(init2rtr_qp_in, in, opcode, MLX5_CMD_OP_INIT2RTR_QP);
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MLX5_SET(init2rtr_qp_in, in, qpn, qp->qpn);
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MLX5_SET(init2rtr_qp_in, in, qpn, ipriv->qpn);
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ret = mlx5_cmd_exec_in(mdev, init2rtr_qp, in);
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if (ret)
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goto err_qp_modify_to_err;
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@ -194,7 +193,7 @@ int mlx5i_init_underlay_qp(struct mlx5e_priv *priv)
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u32 in[MLX5_ST_SZ_DW(rtr2rts_qp_in)] = {};
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MLX5_SET(rtr2rts_qp_in, in, opcode, MLX5_CMD_OP_RTR2RTS_QP);
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MLX5_SET(rtr2rts_qp_in, in, qpn, qp->qpn);
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MLX5_SET(rtr2rts_qp_in, in, qpn, ipriv->qpn);
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ret = mlx5_cmd_exec_in(mdev, rtr2rts_qp, in);
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if (ret)
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goto err_qp_modify_to_err;
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@ -206,7 +205,7 @@ err_qp_modify_to_err:
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u32 in[MLX5_ST_SZ_DW(qp_2err_in)] = {};
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MLX5_SET(qp_2err_in, in, opcode, MLX5_CMD_OP_2ERR_QP);
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MLX5_SET(qp_2err_in, in, qpn, qp->qpn);
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MLX5_SET(qp_2err_in, in, qpn, ipriv->qpn);
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mlx5_cmd_exec_in(mdev, qp_2err, in);
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}
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return ret;
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@ -219,16 +218,17 @@ void mlx5i_uninit_underlay_qp(struct mlx5e_priv *priv)
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u32 in[MLX5_ST_SZ_DW(qp_2rst_in)] = {};
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MLX5_SET(qp_2rst_in, in, opcode, MLX5_CMD_OP_2RST_QP);
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MLX5_SET(qp_2rst_in, in, qpn, ipriv->qp.qpn);
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MLX5_SET(qp_2rst_in, in, qpn, ipriv->qpn);
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mlx5_cmd_exec_in(mdev, qp_2rst, in);
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}
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#define MLX5_QP_ENHANCED_ULP_STATELESS_MODE 2
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int mlx5i_create_underlay_qp(struct mlx5_core_dev *mdev, struct mlx5_core_qp *qp)
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int mlx5i_create_underlay_qp(struct mlx5e_priv *priv)
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{
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u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {};
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u32 in[MLX5_ST_SZ_DW(create_qp_in)] = {};
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struct mlx5i_priv *ipriv = priv->ppriv;
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void *addr_path;
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int ret = 0;
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void *qpc;
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@ -244,21 +244,21 @@ int mlx5i_create_underlay_qp(struct mlx5_core_dev *mdev, struct mlx5_core_qp *qp
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MLX5_SET(ads, addr_path, grh, 1);
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MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP);
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ret = mlx5_cmd_exec_inout(mdev, create_qp, in, out);
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ret = mlx5_cmd_exec_inout(priv->mdev, create_qp, in, out);
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if (ret)
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return ret;
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qp->qpn = MLX5_GET(create_qp_out, out, qpn);
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ipriv->qpn = MLX5_GET(create_qp_out, out, qpn);
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return 0;
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}
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void mlx5i_destroy_underlay_qp(struct mlx5_core_dev *mdev, struct mlx5_core_qp *qp)
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void mlx5i_destroy_underlay_qp(struct mlx5_core_dev *mdev, u32 qpn)
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{
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u32 in[MLX5_ST_SZ_DW(destroy_qp_in)] = {};
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MLX5_SET(destroy_qp_in, in, opcode, MLX5_CMD_OP_DESTROY_QP);
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MLX5_SET(destroy_qp_in, in, qpn, qp->qpn);
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MLX5_SET(destroy_qp_in, in, qpn, qpn);
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mlx5_cmd_exec_in(mdev, destroy_qp, in);
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}
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@ -279,13 +279,13 @@ static int mlx5i_init_tx(struct mlx5e_priv *priv)
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struct mlx5i_priv *ipriv = priv->ppriv;
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int err;
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err = mlx5i_create_underlay_qp(priv->mdev, &ipriv->qp);
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err = mlx5i_create_underlay_qp(priv);
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if (err) {
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mlx5_core_warn(priv->mdev, "create underlay QP failed, %d\n", err);
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return err;
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}
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err = mlx5i_create_tis(priv->mdev, ipriv->qp.qpn, &priv->tisn[0][0]);
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err = mlx5i_create_tis(priv->mdev, ipriv->qpn, &priv->tisn[0][0]);
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if (err) {
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mlx5_core_warn(priv->mdev, "create tis failed, %d\n", err);
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goto err_destroy_underlay_qp;
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@ -294,7 +294,7 @@ static int mlx5i_init_tx(struct mlx5e_priv *priv)
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return 0;
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err_destroy_underlay_qp:
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mlx5i_destroy_underlay_qp(priv->mdev, &ipriv->qp);
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mlx5i_destroy_underlay_qp(priv->mdev, ipriv->qpn);
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return err;
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}
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@ -303,7 +303,7 @@ static void mlx5i_cleanup_tx(struct mlx5e_priv *priv)
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struct mlx5i_priv *ipriv = priv->ppriv;
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mlx5e_destroy_tis(priv->mdev, priv->tisn[0][0]);
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mlx5i_destroy_underlay_qp(priv->mdev, &ipriv->qp);
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mlx5i_destroy_underlay_qp(priv->mdev, ipriv->qpn);
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}
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static int mlx5i_create_flow_steering(struct mlx5e_priv *priv)
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@ -506,12 +506,12 @@ int mlx5i_dev_init(struct net_device *dev)
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struct mlx5i_priv *ipriv = priv->ppriv;
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/* Set dev address using underlay QP */
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dev->dev_addr[1] = (ipriv->qp.qpn >> 16) & 0xff;
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dev->dev_addr[2] = (ipriv->qp.qpn >> 8) & 0xff;
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dev->dev_addr[3] = (ipriv->qp.qpn) & 0xff;
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dev->dev_addr[1] = (ipriv->qpn >> 16) & 0xff;
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dev->dev_addr[2] = (ipriv->qpn >> 8) & 0xff;
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dev->dev_addr[3] = (ipriv->qpn) & 0xff;
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/* Add QPN to net-device mapping to HT */
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mlx5i_pkey_add_qpn(dev ,ipriv->qp.qpn);
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mlx5i_pkey_add_qpn(dev, ipriv->qpn);
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return 0;
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}
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@ -538,7 +538,7 @@ void mlx5i_dev_cleanup(struct net_device *dev)
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mlx5i_uninit_underlay_qp(priv);
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/* Delete QPN to net-device mapping from HT */
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mlx5i_pkey_del_qpn(dev, ipriv->qp.qpn);
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mlx5i_pkey_del_qpn(dev, ipriv->qpn);
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}
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static int mlx5i_open(struct net_device *netdev)
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@ -558,7 +558,7 @@ static int mlx5i_open(struct net_device *netdev)
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goto err_clear_state_opened_flag;
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}
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err = mlx5_fs_add_rx_underlay_qpn(mdev, ipriv->qp.qpn);
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err = mlx5_fs_add_rx_underlay_qpn(mdev, ipriv->qpn);
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if (err) {
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mlx5_core_warn(mdev, "attach underlay qp to ft failed, %d\n", err);
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goto err_reset_qp;
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@ -575,7 +575,7 @@ static int mlx5i_open(struct net_device *netdev)
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return 0;
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err_remove_fs_underlay_qp:
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mlx5_fs_remove_rx_underlay_qpn(mdev, ipriv->qp.qpn);
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mlx5_fs_remove_rx_underlay_qpn(mdev, ipriv->qpn);
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err_reset_qp:
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mlx5i_uninit_underlay_qp(epriv);
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err_clear_state_opened_flag:
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@ -601,7 +601,7 @@ static int mlx5i_close(struct net_device *netdev)
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clear_bit(MLX5E_STATE_OPENED, &epriv->state);
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netif_carrier_off(epriv->netdev);
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mlx5_fs_remove_rx_underlay_qpn(mdev, ipriv->qp.qpn);
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mlx5_fs_remove_rx_underlay_qpn(mdev, ipriv->qpn);
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mlx5e_deactivate_priv_channels(epriv);
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mlx5e_close_channels(&epriv->channels);
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mlx5i_uninit_underlay_qp(epriv);
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@ -620,11 +620,12 @@ static int mlx5i_attach_mcast(struct net_device *netdev, struct ib_device *hca,
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struct mlx5i_priv *ipriv = epriv->ppriv;
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int err;
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mlx5_core_dbg(mdev, "attaching QPN 0x%x, MGID %pI6\n", ipriv->qp.qpn, gid->raw);
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err = mlx5_core_attach_mcg(mdev, gid, ipriv->qp.qpn);
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mlx5_core_dbg(mdev, "attaching QPN 0x%x, MGID %pI6\n", ipriv->qpn,
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gid->raw);
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err = mlx5_core_attach_mcg(mdev, gid, ipriv->qpn);
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if (err)
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mlx5_core_warn(mdev, "failed attaching QPN 0x%x, MGID %pI6\n",
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ipriv->qp.qpn, gid->raw);
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ipriv->qpn, gid->raw);
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if (set_qkey) {
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mlx5_core_dbg(mdev, "%s setting qkey 0x%x\n",
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@ -643,12 +644,13 @@ static int mlx5i_detach_mcast(struct net_device *netdev, struct ib_device *hca,
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struct mlx5i_priv *ipriv = epriv->ppriv;
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int err;
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mlx5_core_dbg(mdev, "detaching QPN 0x%x, MGID %pI6\n", ipriv->qp.qpn, gid->raw);
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mlx5_core_dbg(mdev, "detaching QPN 0x%x, MGID %pI6\n", ipriv->qpn,
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gid->raw);
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err = mlx5_core_detach_mcg(mdev, gid, ipriv->qp.qpn);
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err = mlx5_core_detach_mcg(mdev, gid, ipriv->qpn);
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if (err)
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mlx5_core_dbg(mdev, "failed detaching QPN 0x%x, MGID %pI6\n",
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ipriv->qp.qpn, gid->raw);
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ipriv->qpn, gid->raw);
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return err;
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||||
}
|
||||
|
|
|
|||
|
|
@ -51,7 +51,7 @@ extern const struct ethtool_ops mlx5i_pkey_ethtool_ops;
|
|||
/* ipoib rdma netdev's private data structure */
|
||||
struct mlx5i_priv {
|
||||
struct rdma_netdev rn; /* keep this first */
|
||||
struct mlx5_core_qp qp;
|
||||
u32 qpn;
|
||||
bool sub_interface;
|
||||
u32 qkey;
|
||||
u16 pkey_index;
|
||||
|
|
@ -62,8 +62,8 @@ struct mlx5i_priv {
|
|||
int mlx5i_create_tis(struct mlx5_core_dev *mdev, u32 underlay_qpn, u32 *tisn);
|
||||
|
||||
/* Underlay QP create/destroy functions */
|
||||
int mlx5i_create_underlay_qp(struct mlx5_core_dev *mdev, struct mlx5_core_qp *qp);
|
||||
void mlx5i_destroy_underlay_qp(struct mlx5_core_dev *mdev, struct mlx5_core_qp *qp);
|
||||
int mlx5i_create_underlay_qp(struct mlx5e_priv *priv);
|
||||
void mlx5i_destroy_underlay_qp(struct mlx5_core_dev *mdev, u32 qpn);
|
||||
|
||||
/* Underlay QP state modification init/uninit functions */
|
||||
int mlx5i_init_underlay_qp(struct mlx5e_priv *priv);
|
||||
|
|
|
|||
|
|
@ -204,13 +204,13 @@ static int mlx5i_pkey_open(struct net_device *netdev)
|
|||
goto err_release_lock;
|
||||
}
|
||||
|
||||
err = mlx5_fs_add_rx_underlay_qpn(mdev, ipriv->qp.qpn);
|
||||
err = mlx5_fs_add_rx_underlay_qpn(mdev, ipriv->qpn);
|
||||
if (err) {
|
||||
mlx5_core_warn(mdev, "attach child underlay qp to ft failed, %d\n", err);
|
||||
goto err_unint_underlay_qp;
|
||||
}
|
||||
|
||||
err = mlx5i_create_tis(mdev, ipriv->qp.qpn, &epriv->tisn[0][0]);
|
||||
err = mlx5i_create_tis(mdev, ipriv->qpn, &epriv->tisn[0][0]);
|
||||
if (err) {
|
||||
mlx5_core_warn(mdev, "create child tis failed, %d\n", err);
|
||||
goto err_remove_rx_uderlay_qp;
|
||||
|
|
@ -230,7 +230,7 @@ static int mlx5i_pkey_open(struct net_device *netdev)
|
|||
err_clear_state_opened_flag:
|
||||
mlx5e_destroy_tis(mdev, epriv->tisn[0][0]);
|
||||
err_remove_rx_uderlay_qp:
|
||||
mlx5_fs_remove_rx_underlay_qpn(mdev, ipriv->qp.qpn);
|
||||
mlx5_fs_remove_rx_underlay_qpn(mdev, ipriv->qpn);
|
||||
err_unint_underlay_qp:
|
||||
mlx5i_uninit_underlay_qp(epriv);
|
||||
err_release_lock:
|
||||
|
|
@ -253,7 +253,7 @@ static int mlx5i_pkey_close(struct net_device *netdev)
|
|||
clear_bit(MLX5E_STATE_OPENED, &priv->state);
|
||||
|
||||
netif_carrier_off(priv->netdev);
|
||||
mlx5_fs_remove_rx_underlay_qpn(mdev, ipriv->qp.qpn);
|
||||
mlx5_fs_remove_rx_underlay_qpn(mdev, ipriv->qpn);
|
||||
mlx5i_uninit_underlay_qp(priv);
|
||||
mlx5e_deactivate_priv_channels(priv);
|
||||
mlx5e_close_channels(&priv->channels);
|
||||
|
|
@ -307,23 +307,20 @@ static void mlx5i_pkey_cleanup(struct mlx5e_priv *priv)
|
|||
|
||||
static int mlx5i_pkey_init_tx(struct mlx5e_priv *priv)
|
||||
{
|
||||
struct mlx5i_priv *ipriv = priv->ppriv;
|
||||
int err;
|
||||
|
||||
err = mlx5i_create_underlay_qp(priv->mdev, &ipriv->qp);
|
||||
if (err) {
|
||||
err = mlx5i_create_underlay_qp(priv);
|
||||
if (err)
|
||||
mlx5_core_warn(priv->mdev, "create child underlay QP failed, %d\n", err);
|
||||
return err;
|
||||
}
|
||||
|
||||
return 0;
|
||||
return err;
|
||||
}
|
||||
|
||||
static void mlx5i_pkey_cleanup_tx(struct mlx5e_priv *priv)
|
||||
{
|
||||
struct mlx5i_priv *ipriv = priv->ppriv;
|
||||
|
||||
mlx5i_destroy_underlay_qp(priv->mdev, &ipriv->qp);
|
||||
mlx5i_destroy_underlay_qp(priv->mdev, ipriv->qpn);
|
||||
}
|
||||
|
||||
static int mlx5i_pkey_init_rx(struct mlx5e_priv *priv)
|
||||
|
|
|
|||
|
|
@ -178,7 +178,7 @@ static struct mlx5dr_qp *dr_create_rc_qp(struct mlx5_core_dev *mdev,
|
|||
|
||||
MLX5_SET(create_qp_in, in, opcode, MLX5_CMD_OP_CREATE_QP);
|
||||
err = mlx5_cmd_exec(mdev, in, inlen, out, sizeof(out));
|
||||
dr_qp->mqp.qpn = MLX5_GET(create_qp_out, out, qpn);
|
||||
dr_qp->qpn = MLX5_GET(create_qp_out, out, qpn);
|
||||
kfree(in);
|
||||
if (err)
|
||||
goto err_in;
|
||||
|
|
@ -199,10 +199,9 @@ static void dr_destroy_qp(struct mlx5_core_dev *mdev,
|
|||
struct mlx5dr_qp *dr_qp)
|
||||
{
|
||||
u32 in[MLX5_ST_SZ_DW(destroy_qp_in)] = {};
|
||||
struct mlx5_core_qp *qp = &dr_qp->mqp;
|
||||
|
||||
MLX5_SET(destroy_qp_in, in, opcode, MLX5_CMD_OP_DESTROY_QP);
|
||||
MLX5_SET(destroy_qp_in, in, qpn, qp->qpn);
|
||||
MLX5_SET(destroy_qp_in, in, qpn, dr_qp->qpn);
|
||||
mlx5_cmd_exec_in(mdev, destroy_qp, in);
|
||||
|
||||
kfree(dr_qp->sq.wqe_head);
|
||||
|
|
@ -242,7 +241,7 @@ static void dr_rdma_segments(struct mlx5dr_qp *dr_qp, u64 remote_addr,
|
|||
MLX5_WQE_CTRL_CQ_UPDATE : 0;
|
||||
wq_ctrl->opmod_idx_opcode = cpu_to_be32(((dr_qp->sq.pc & 0xffff) << 8) |
|
||||
opcode);
|
||||
wq_ctrl->qpn_ds = cpu_to_be32(size | dr_qp->mqp.qpn << 8);
|
||||
wq_ctrl->qpn_ds = cpu_to_be32(size | dr_qp->qpn << 8);
|
||||
wq_raddr = (void *)(wq_ctrl + 1);
|
||||
wq_raddr->raddr = cpu_to_be64(remote_addr);
|
||||
wq_raddr->rkey = cpu_to_be32(rkey);
|
||||
|
|
@ -586,7 +585,7 @@ static int dr_modify_qp_rst2init(struct mlx5_core_dev *mdev,
|
|||
MLX5_SET(qpc, qpc, rwe, 1);
|
||||
|
||||
MLX5_SET(rst2init_qp_in, in, opcode, MLX5_CMD_OP_RST2INIT_QP);
|
||||
MLX5_SET(rst2init_qp_in, in, qpn, dr_qp->mqp.qpn);
|
||||
MLX5_SET(rst2init_qp_in, in, qpn, dr_qp->qpn);
|
||||
|
||||
return mlx5_cmd_exec_in(mdev, rst2init_qp, in);
|
||||
}
|
||||
|
|
@ -600,13 +599,13 @@ static int dr_cmd_modify_qp_rtr2rts(struct mlx5_core_dev *mdev,
|
|||
|
||||
qpc = MLX5_ADDR_OF(rtr2rts_qp_in, in, qpc);
|
||||
|
||||
MLX5_SET(rtr2rts_qp_in, in, qpn, dr_qp->mqp.qpn);
|
||||
MLX5_SET(rtr2rts_qp_in, in, qpn, dr_qp->qpn);
|
||||
|
||||
MLX5_SET(qpc, qpc, retry_count, attr->retry_cnt);
|
||||
MLX5_SET(qpc, qpc, rnr_retry, attr->rnr_retry);
|
||||
|
||||
MLX5_SET(rtr2rts_qp_in, in, opcode, MLX5_CMD_OP_RTR2RTS_QP);
|
||||
MLX5_SET(rtr2rts_qp_in, in, qpn, dr_qp->mqp.qpn);
|
||||
MLX5_SET(rtr2rts_qp_in, in, qpn, dr_qp->qpn);
|
||||
|
||||
return mlx5_cmd_exec_in(mdev, rtr2rts_qp, in);
|
||||
}
|
||||
|
|
@ -620,7 +619,7 @@ static int dr_cmd_modify_qp_init2rtr(struct mlx5_core_dev *mdev,
|
|||
|
||||
qpc = MLX5_ADDR_OF(init2rtr_qp_in, in, qpc);
|
||||
|
||||
MLX5_SET(init2rtr_qp_in, in, qpn, dr_qp->mqp.qpn);
|
||||
MLX5_SET(init2rtr_qp_in, in, qpn, dr_qp->qpn);
|
||||
|
||||
MLX5_SET(qpc, qpc, mtu, attr->mtu);
|
||||
MLX5_SET(qpc, qpc, log_msg_max, DR_CHUNK_SIZE_MAX - 1);
|
||||
|
|
@ -640,7 +639,7 @@ static int dr_cmd_modify_qp_init2rtr(struct mlx5_core_dev *mdev,
|
|||
MLX5_SET(qpc, qpc, min_rnr_nak, 1);
|
||||
|
||||
MLX5_SET(init2rtr_qp_in, in, opcode, MLX5_CMD_OP_INIT2RTR_QP);
|
||||
MLX5_SET(init2rtr_qp_in, in, qpn, dr_qp->mqp.qpn);
|
||||
MLX5_SET(init2rtr_qp_in, in, qpn, dr_qp->qpn);
|
||||
|
||||
return mlx5_cmd_exec_in(mdev, init2rtr_qp, in);
|
||||
}
|
||||
|
|
@ -668,7 +667,7 @@ static int dr_prepare_qp_to_rts(struct mlx5dr_domain *dmn)
|
|||
return ret;
|
||||
|
||||
rtr_attr.mtu = mtu;
|
||||
rtr_attr.qp_num = dr_qp->mqp.qpn;
|
||||
rtr_attr.qp_num = dr_qp->qpn;
|
||||
rtr_attr.min_rnr_timer = 12;
|
||||
rtr_attr.port_num = port;
|
||||
rtr_attr.sgid_index = gid_index;
|
||||
|
|
|
|||
|
|
@ -990,7 +990,7 @@ struct mlx5dr_qp {
|
|||
struct mlx5_wq_qp wq;
|
||||
struct mlx5_uars_page *uar;
|
||||
struct mlx5_wq_ctrl wq_ctrl;
|
||||
struct mlx5_core_qp mqp;
|
||||
u32 qpn;
|
||||
struct {
|
||||
unsigned int pc;
|
||||
unsigned int cc;
|
||||
|
|
|
|||
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