spi: switch to use modern name
Merge series from Yang Yingliang <yangyingliang@huawei.com>: After introducing devm_spi_alloc_host/spi_alloc_host(), the legacy named function devm_spi_alloc_master/spi_alloc_master() can be replaced. And also change other legacy name master/slave to modern name host/target or controller.
This commit is contained in:
Коммит
f9a798867b
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@ -215,9 +215,9 @@ static int amd_spi_execute_opcode(struct amd_spi *amd_spi)
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}
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}
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static int amd_spi_master_setup(struct spi_device *spi)
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static int amd_spi_host_setup(struct spi_device *spi)
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{
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struct amd_spi *amd_spi = spi_master_get_devdata(spi->master);
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struct amd_spi *amd_spi = spi_controller_get_devdata(spi->controller);
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amd_spi_clear_fifo_ptr(amd_spi);
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@ -272,7 +272,7 @@ static int amd_set_spi_freq(struct amd_spi *amd_spi, u32 speed_hz)
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}
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static inline int amd_spi_fifo_xfer(struct amd_spi *amd_spi,
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struct spi_master *master,
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struct spi_controller *host,
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struct spi_message *message)
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{
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struct spi_transfer *xfer = NULL;
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@ -353,15 +353,15 @@ fin_msg:
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return -ENODEV;
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}
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spi_finalize_current_message(master);
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spi_finalize_current_message(host);
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return message->status;
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}
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static int amd_spi_master_transfer(struct spi_master *master,
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static int amd_spi_host_transfer(struct spi_controller *host,
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struct spi_message *msg)
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{
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struct amd_spi *amd_spi = spi_master_get_devdata(master);
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struct amd_spi *amd_spi = spi_controller_get_devdata(host);
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struct spi_device *spi = msg->spi;
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amd_spi_select_chip(amd_spi, spi_get_chipselect(spi, 0));
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@ -370,7 +370,7 @@ static int amd_spi_master_transfer(struct spi_master *master,
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* Extract spi_transfers from the spi message and
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* program the controller.
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*/
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return amd_spi_fifo_xfer(amd_spi, master, msg);
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return amd_spi_fifo_xfer(amd_spi, host, msg);
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}
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static size_t amd_spi_max_transfer_size(struct spi_device *spi)
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@ -381,16 +381,16 @@ static size_t amd_spi_max_transfer_size(struct spi_device *spi)
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static int amd_spi_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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struct spi_master *master;
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struct spi_controller *host;
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struct amd_spi *amd_spi;
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int err;
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/* Allocate storage for spi_master and driver private data */
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master = devm_spi_alloc_master(dev, sizeof(struct amd_spi));
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if (!master)
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return dev_err_probe(dev, -ENOMEM, "Error allocating SPI master\n");
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/* Allocate storage for host and driver private data */
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host = devm_spi_alloc_host(dev, sizeof(struct amd_spi));
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if (!host)
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return dev_err_probe(dev, -ENOMEM, "Error allocating SPI host\n");
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amd_spi = spi_master_get_devdata(master);
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amd_spi = spi_controller_get_devdata(host);
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amd_spi->io_remap_addr = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(amd_spi->io_remap_addr))
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return dev_err_probe(dev, PTR_ERR(amd_spi->io_remap_addr),
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@ -400,20 +400,20 @@ static int amd_spi_probe(struct platform_device *pdev)
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amd_spi->version = (enum amd_spi_versions) device_get_match_data(dev);
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/* Initialize the spi_master fields */
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master->bus_num = 0;
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master->num_chipselect = 4;
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master->mode_bits = 0;
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master->flags = SPI_CONTROLLER_HALF_DUPLEX;
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master->max_speed_hz = AMD_SPI_MAX_HZ;
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master->min_speed_hz = AMD_SPI_MIN_HZ;
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master->setup = amd_spi_master_setup;
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master->transfer_one_message = amd_spi_master_transfer;
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master->max_transfer_size = amd_spi_max_transfer_size;
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master->max_message_size = amd_spi_max_transfer_size;
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/* Initialize the spi_controller fields */
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host->bus_num = 0;
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host->num_chipselect = 4;
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host->mode_bits = 0;
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host->flags = SPI_CONTROLLER_HALF_DUPLEX;
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host->max_speed_hz = AMD_SPI_MAX_HZ;
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host->min_speed_hz = AMD_SPI_MIN_HZ;
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host->setup = amd_spi_host_setup;
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host->transfer_one_message = amd_spi_host_transfer;
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host->max_transfer_size = amd_spi_max_transfer_size;
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host->max_message_size = amd_spi_max_transfer_size;
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/* Register the controller with SPI framework */
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err = devm_spi_register_master(dev, master);
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err = devm_spi_register_controller(dev, host);
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if (err)
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return dev_err_probe(dev, err, "error registering SPI controller\n");
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@ -295,7 +295,7 @@ static const struct aspeed_spi_data ast2400_spi_data;
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static int do_aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
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{
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struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->master);
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struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->controller);
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struct aspeed_spi_chip *chip = &aspi->chips[spi_get_chipselect(mem->spi, 0)];
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u32 addr_mode, addr_mode_backup;
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u32 ctl_val;
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@ -374,7 +374,7 @@ static int aspeed_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
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static const char *aspeed_spi_get_name(struct spi_mem *mem)
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{
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struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->master);
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struct aspeed_spi *aspi = spi_controller_get_devdata(mem->spi->controller);
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struct device *dev = aspi->dev;
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return devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev),
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@ -553,7 +553,7 @@ static int aspeed_spi_do_calibration(struct aspeed_spi_chip *chip);
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static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
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{
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struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
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struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->controller);
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struct aspeed_spi_chip *chip = &aspi->chips[spi_get_chipselect(desc->mem->spi, 0)];
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struct spi_mem_op *op = &desc->info.op_tmpl;
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u32 ctl_val;
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@ -620,7 +620,7 @@ static int aspeed_spi_dirmap_create(struct spi_mem_dirmap_desc *desc)
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static ssize_t aspeed_spi_dirmap_read(struct spi_mem_dirmap_desc *desc,
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u64 offset, size_t len, void *buf)
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{
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struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->master);
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struct aspeed_spi *aspi = spi_controller_get_devdata(desc->mem->spi->controller);
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struct aspeed_spi_chip *chip = &aspi->chips[spi_get_chipselect(desc->mem->spi, 0)];
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/* Switch to USER command mode if mapping window is too small */
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@ -669,7 +669,7 @@ static void aspeed_spi_chip_enable(struct aspeed_spi *aspi, unsigned int cs, boo
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static int aspeed_spi_setup(struct spi_device *spi)
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{
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struct aspeed_spi *aspi = spi_controller_get_devdata(spi->master);
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struct aspeed_spi *aspi = spi_controller_get_devdata(spi->controller);
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const struct aspeed_spi_data *data = aspi->data;
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unsigned int cs = spi_get_chipselect(spi, 0);
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struct aspeed_spi_chip *chip = &aspi->chips[cs];
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@ -697,7 +697,7 @@ static int aspeed_spi_setup(struct spi_device *spi)
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static void aspeed_spi_cleanup(struct spi_device *spi)
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{
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struct aspeed_spi *aspi = spi_controller_get_devdata(spi->master);
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struct aspeed_spi *aspi = spi_controller_get_devdata(spi->controller);
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unsigned int cs = spi_get_chipselect(spi, 0);
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aspeed_spi_chip_enable(aspi, cs, false);
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@ -726,7 +726,7 @@ static int aspeed_spi_probe(struct platform_device *pdev)
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if (!data)
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return -ENODEV;
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ctlr = devm_spi_alloc_master(dev, sizeof(*aspi));
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ctlr = devm_spi_alloc_host(dev, sizeof(*aspi));
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if (!ctlr)
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return -ENOMEM;
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@ -356,8 +356,8 @@ static bool spi_engine_read_rx_fifo(struct spi_engine *spi_engine)
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static irqreturn_t spi_engine_irq(int irq, void *devid)
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{
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struct spi_master *master = devid;
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struct spi_engine *spi_engine = spi_master_get_devdata(master);
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struct spi_controller *host = devid;
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struct spi_engine *spi_engine = spi_controller_get_devdata(host);
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unsigned int disable_int = 0;
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unsigned int pending;
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@ -396,7 +396,7 @@ static irqreturn_t spi_engine_irq(int irq, void *devid)
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msg->status = 0;
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msg->actual_length = msg->frame_length;
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spi_engine->msg = NULL;
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spi_finalize_current_message(master);
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spi_finalize_current_message(host);
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disable_int |= SPI_ENGINE_INT_SYNC;
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}
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}
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@ -412,11 +412,11 @@ static irqreturn_t spi_engine_irq(int irq, void *devid)
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return IRQ_HANDLED;
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}
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static int spi_engine_transfer_one_message(struct spi_master *master,
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static int spi_engine_transfer_one_message(struct spi_controller *host,
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struct spi_message *msg)
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{
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struct spi_engine_program p_dry, *p;
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struct spi_engine *spi_engine = spi_master_get_devdata(master);
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struct spi_engine *spi_engine = spi_controller_get_devdata(host);
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unsigned int int_enable = 0;
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unsigned long flags;
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size_t size;
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@ -464,7 +464,7 @@ static int spi_engine_transfer_one_message(struct spi_master *master,
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static int spi_engine_probe(struct platform_device *pdev)
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{
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struct spi_engine *spi_engine;
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struct spi_master *master;
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struct spi_controller *host;
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unsigned int version;
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int irq;
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int ret;
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@ -477,29 +477,29 @@ static int spi_engine_probe(struct platform_device *pdev)
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if (!spi_engine)
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return -ENOMEM;
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master = spi_alloc_master(&pdev->dev, 0);
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if (!master)
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host = spi_alloc_host(&pdev->dev, 0);
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if (!host)
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return -ENOMEM;
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spi_master_set_devdata(master, spi_engine);
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spi_controller_set_devdata(host, spi_engine);
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spin_lock_init(&spi_engine->lock);
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spi_engine->clk = devm_clk_get(&pdev->dev, "s_axi_aclk");
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if (IS_ERR(spi_engine->clk)) {
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ret = PTR_ERR(spi_engine->clk);
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goto err_put_master;
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goto err_put_host;
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}
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spi_engine->ref_clk = devm_clk_get(&pdev->dev, "spi_clk");
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if (IS_ERR(spi_engine->ref_clk)) {
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ret = PTR_ERR(spi_engine->ref_clk);
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goto err_put_master;
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goto err_put_host;
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}
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ret = clk_prepare_enable(spi_engine->clk);
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if (ret)
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goto err_put_master;
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goto err_put_host;
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ret = clk_prepare_enable(spi_engine->ref_clk);
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if (ret)
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@ -525,46 +525,46 @@ static int spi_engine_probe(struct platform_device *pdev)
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writel_relaxed(0xff, spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
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writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);
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ret = request_irq(irq, spi_engine_irq, 0, pdev->name, master);
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ret = request_irq(irq, spi_engine_irq, 0, pdev->name, host);
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if (ret)
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goto err_ref_clk_disable;
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master->dev.of_node = pdev->dev.of_node;
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master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_3WIRE;
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master->bits_per_word_mask = SPI_BPW_MASK(8);
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master->max_speed_hz = clk_get_rate(spi_engine->ref_clk) / 2;
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master->transfer_one_message = spi_engine_transfer_one_message;
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master->num_chipselect = 8;
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host->dev.of_node = pdev->dev.of_node;
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host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_3WIRE;
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host->bits_per_word_mask = SPI_BPW_MASK(8);
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host->max_speed_hz = clk_get_rate(spi_engine->ref_clk) / 2;
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host->transfer_one_message = spi_engine_transfer_one_message;
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host->num_chipselect = 8;
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ret = spi_register_master(master);
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ret = spi_register_controller(host);
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if (ret)
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goto err_free_irq;
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platform_set_drvdata(pdev, master);
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platform_set_drvdata(pdev, host);
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return 0;
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err_free_irq:
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free_irq(irq, master);
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free_irq(irq, host);
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err_ref_clk_disable:
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clk_disable_unprepare(spi_engine->ref_clk);
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err_clk_disable:
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clk_disable_unprepare(spi_engine->clk);
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err_put_master:
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spi_master_put(master);
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err_put_host:
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spi_controller_put(host);
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return ret;
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}
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static void spi_engine_remove(struct platform_device *pdev)
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{
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struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
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struct spi_engine *spi_engine = spi_master_get_devdata(master);
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struct spi_controller *host = spi_controller_get(platform_get_drvdata(pdev));
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struct spi_engine *spi_engine = spi_controller_get_devdata(host);
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int irq = platform_get_irq(pdev, 0);
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spi_unregister_master(master);
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spi_unregister_controller(host);
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free_irq(irq, master);
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free_irq(irq, host);
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spi_master_put(master);
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spi_controller_put(host);
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writel_relaxed(0xff, spi_engine->base + SPI_ENGINE_REG_INT_PENDING);
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writel_relaxed(0x00, spi_engine->base + SPI_ENGINE_REG_INT_ENABLE);
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@ -220,7 +220,7 @@ struct qspi_trans {
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struct bcm_qspi {
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struct platform_device *pdev;
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struct spi_master *master;
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struct spi_controller *host;
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struct clk *clk;
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u32 base_clk;
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u32 max_speed_hz;
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@ -732,7 +732,7 @@ static bool bcm_qspi_mspi_transfer_is_last(struct bcm_qspi *qspi,
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struct qspi_trans *qt)
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{
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if (qt->mspi_last_trans &&
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spi_transfer_is_last(qspi->master, qt->trans))
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spi_transfer_is_last(qspi->host, qt->trans))
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return true;
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else
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return false;
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@ -979,7 +979,7 @@ static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi)
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mspi_cdram |= ((tp.trans->bits_per_word <= 8) ? 0 :
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MSPI_CDRAM_BITSE_BIT);
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/* set 3wrire halfduplex mode data from master to slave */
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/* set 3wrire halfduplex mode data from host to target */
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if ((spi->mode & SPI_3WIRE) && tp.trans->tx_buf)
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mspi_cdram |= MSPI_CDRAM_OUTP;
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@ -1035,7 +1035,7 @@ done:
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static int bcm_qspi_bspi_exec_mem_op(struct spi_device *spi,
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const struct spi_mem_op *op)
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{
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struct bcm_qspi *qspi = spi_master_get_devdata(spi->master);
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struct bcm_qspi *qspi = spi_controller_get_devdata(spi->controller);
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u32 addr = 0, len, rdlen, len_words, from = 0;
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int ret = 0;
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unsigned long timeo = msecs_to_jiffies(100);
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@ -1118,11 +1118,11 @@ static int bcm_qspi_bspi_exec_mem_op(struct spi_device *spi,
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return ret;
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}
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static int bcm_qspi_transfer_one(struct spi_master *master,
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static int bcm_qspi_transfer_one(struct spi_controller *host,
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struct spi_device *spi,
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struct spi_transfer *trans)
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{
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struct bcm_qspi *qspi = spi_master_get_devdata(master);
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struct bcm_qspi *qspi = spi_controller_get_devdata(host);
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int slots;
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unsigned long timeo = msecs_to_jiffies(100);
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@ -1150,8 +1150,8 @@ static int bcm_qspi_transfer_one(struct spi_master *master,
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static int bcm_qspi_mspi_exec_mem_op(struct spi_device *spi,
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const struct spi_mem_op *op)
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{
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struct spi_master *master = spi->master;
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struct bcm_qspi *qspi = spi_master_get_devdata(master);
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struct spi_controller *host = spi->controller;
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struct bcm_qspi *qspi = spi_controller_get_devdata(host);
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struct spi_transfer t[2];
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u8 cmd[6] = { };
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int ret, i;
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@ -1171,7 +1171,7 @@ static int bcm_qspi_mspi_exec_mem_op(struct spi_device *spi,
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t[0].tx_nbits = op->cmd.buswidth;
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/* lets mspi know that this is not last transfer */
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qspi->trans_pos.mspi_last_trans = false;
|
||||
ret = bcm_qspi_transfer_one(master, spi, &t[0]);
|
||||
ret = bcm_qspi_transfer_one(host, spi, &t[0]);
|
||||
|
||||
/* rx */
|
||||
qspi->trans_pos.mspi_last_trans = true;
|
||||
|
@ -1181,7 +1181,7 @@ static int bcm_qspi_mspi_exec_mem_op(struct spi_device *spi,
|
|||
t[1].len = op->data.nbytes;
|
||||
t[1].rx_nbits = op->data.buswidth;
|
||||
t[1].bits_per_word = spi->bits_per_word;
|
||||
ret = bcm_qspi_transfer_one(master, spi, &t[1]);
|
||||
ret = bcm_qspi_transfer_one(host, spi, &t[1]);
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
@ -1191,7 +1191,7 @@ static int bcm_qspi_exec_mem_op(struct spi_mem *mem,
|
|||
const struct spi_mem_op *op)
|
||||
{
|
||||
struct spi_device *spi = mem->spi;
|
||||
struct bcm_qspi *qspi = spi_master_get_devdata(spi->master);
|
||||
struct bcm_qspi *qspi = spi_controller_get_devdata(spi->controller);
|
||||
int ret = 0;
|
||||
bool mspi_read = false;
|
||||
u32 addr = 0, len;
|
||||
|
@ -1486,7 +1486,7 @@ int bcm_qspi_probe(struct platform_device *pdev,
|
|||
const struct bcm_qspi_data *data;
|
||||
struct device *dev = &pdev->dev;
|
||||
struct bcm_qspi *qspi;
|
||||
struct spi_master *master;
|
||||
struct spi_controller *host;
|
||||
struct resource *res;
|
||||
int irq, ret = 0, num_ints = 0;
|
||||
u32 val;
|
||||
|
@ -1504,13 +1504,13 @@ int bcm_qspi_probe(struct platform_device *pdev,
|
|||
|
||||
data = of_id->data;
|
||||
|
||||
master = devm_spi_alloc_master(dev, sizeof(struct bcm_qspi));
|
||||
if (!master) {
|
||||
dev_err(dev, "error allocating spi_master\n");
|
||||
host = devm_spi_alloc_host(dev, sizeof(struct bcm_qspi));
|
||||
if (!host) {
|
||||
dev_err(dev, "error allocating spi_controller\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
qspi = spi_master_get_devdata(master);
|
||||
qspi = spi_controller_get_devdata(host);
|
||||
|
||||
qspi->clk = devm_clk_get_optional(&pdev->dev, NULL);
|
||||
if (IS_ERR(qspi->clk))
|
||||
|
@ -1520,23 +1520,23 @@ int bcm_qspi_probe(struct platform_device *pdev,
|
|||
qspi->trans_pos.trans = NULL;
|
||||
qspi->trans_pos.byte = 0;
|
||||
qspi->trans_pos.mspi_last_trans = true;
|
||||
qspi->master = master;
|
||||
qspi->host = host;
|
||||
|
||||
master->bus_num = -1;
|
||||
master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_RX_DUAL | SPI_RX_QUAD |
|
||||
host->bus_num = -1;
|
||||
host->mode_bits = SPI_CPHA | SPI_CPOL | SPI_RX_DUAL | SPI_RX_QUAD |
|
||||
SPI_3WIRE;
|
||||
master->setup = bcm_qspi_setup;
|
||||
master->transfer_one = bcm_qspi_transfer_one;
|
||||
master->mem_ops = &bcm_qspi_mem_ops;
|
||||
master->cleanup = bcm_qspi_cleanup;
|
||||
master->dev.of_node = dev->of_node;
|
||||
master->num_chipselect = NUM_CHIPSELECT;
|
||||
master->use_gpio_descriptors = true;
|
||||
host->setup = bcm_qspi_setup;
|
||||
host->transfer_one = bcm_qspi_transfer_one;
|
||||
host->mem_ops = &bcm_qspi_mem_ops;
|
||||
host->cleanup = bcm_qspi_cleanup;
|
||||
host->dev.of_node = dev->of_node;
|
||||
host->num_chipselect = NUM_CHIPSELECT;
|
||||
host->use_gpio_descriptors = true;
|
||||
|
||||
qspi->big_endian = of_device_is_big_endian(dev->of_node);
|
||||
|
||||
if (!of_property_read_u32(dev->of_node, "num-cs", &val))
|
||||
master->num_chipselect = val;
|
||||
host->num_chipselect = val;
|
||||
|
||||
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hif_mspi");
|
||||
if (!res)
|
||||
|
@ -1659,9 +1659,9 @@ int bcm_qspi_probe(struct platform_device *pdev,
|
|||
qspi->xfer_mode.addrlen = -1;
|
||||
qspi->xfer_mode.hp = -1;
|
||||
|
||||
ret = spi_register_master(master);
|
||||
ret = spi_register_controller(host);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "can't register master\n");
|
||||
dev_err(dev, "can't register host\n");
|
||||
goto qspi_reg_err;
|
||||
}
|
||||
|
||||
|
@ -1682,7 +1682,7 @@ void bcm_qspi_remove(struct platform_device *pdev)
|
|||
{
|
||||
struct bcm_qspi *qspi = platform_get_drvdata(pdev);
|
||||
|
||||
spi_unregister_master(qspi->master);
|
||||
spi_unregister_controller(qspi->host);
|
||||
bcm_qspi_hw_uninit(qspi);
|
||||
clk_disable_unprepare(qspi->clk);
|
||||
kfree(qspi->dev_ids);
|
||||
|
@ -1700,7 +1700,7 @@ static int __maybe_unused bcm_qspi_suspend(struct device *dev)
|
|||
qspi->s3_strap_override_ctrl =
|
||||
bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
|
||||
|
||||
spi_master_suspend(qspi->master);
|
||||
spi_controller_suspend(qspi->host);
|
||||
clk_disable_unprepare(qspi->clk);
|
||||
bcm_qspi_hw_uninit(qspi);
|
||||
|
||||
|
@ -1721,7 +1721,7 @@ static int __maybe_unused bcm_qspi_resume(struct device *dev)
|
|||
|
||||
ret = clk_prepare_enable(qspi->clk);
|
||||
if (!ret)
|
||||
spi_master_resume(qspi->master);
|
||||
spi_controller_resume(qspi->host);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
@ -105,7 +105,7 @@ MODULE_PARM_DESC(polling_limit_us,
|
|||
* These are counted as well in @count_transfer_polling and
|
||||
* @count_transfer_irq
|
||||
* @count_transfer_dma: count how often dma mode is used
|
||||
* @slv: SPI slave currently selected
|
||||
* @target: SPI target currently selected
|
||||
* (used by bcm2835_spi_dma_tx_done() to write @clear_rx_cs)
|
||||
* @tx_dma_active: whether a TX DMA descriptor is in progress
|
||||
* @rx_dma_active: whether a RX DMA descriptor is in progress
|
||||
|
@ -135,7 +135,7 @@ struct bcm2835_spi {
|
|||
u64 count_transfer_irq_after_polling;
|
||||
u64 count_transfer_dma;
|
||||
|
||||
struct bcm2835_spidev *slv;
|
||||
struct bcm2835_spidev *target;
|
||||
unsigned int tx_dma_active;
|
||||
unsigned int rx_dma_active;
|
||||
struct dma_async_tx_descriptor *fill_tx_desc;
|
||||
|
@ -143,14 +143,14 @@ struct bcm2835_spi {
|
|||
};
|
||||
|
||||
/**
|
||||
* struct bcm2835_spidev - BCM2835 SPI slave
|
||||
* struct bcm2835_spidev - BCM2835 SPI target
|
||||
* @prepare_cs: precalculated CS register value for ->prepare_message()
|
||||
* (uses slave-specific clock polarity and phase settings)
|
||||
* (uses target-specific clock polarity and phase settings)
|
||||
* @clear_rx_desc: preallocated RX DMA descriptor used for TX-only transfers
|
||||
* (cyclically clears RX FIFO by writing @clear_rx_cs to CS register)
|
||||
* @clear_rx_addr: bus address of @clear_rx_cs
|
||||
* @clear_rx_cs: precalculated CS register value to clear RX FIFO
|
||||
* (uses slave-specific clock polarity and phase settings)
|
||||
* (uses target-specific clock polarity and phase settings)
|
||||
*/
|
||||
struct bcm2835_spidev {
|
||||
u32 prepare_cs;
|
||||
|
@ -434,7 +434,7 @@ static int bcm2835_spi_transfer_one_irq(struct spi_controller *ctlr,
|
|||
|
||||
/**
|
||||
* bcm2835_spi_transfer_prologue() - transfer first few bytes without DMA
|
||||
* @ctlr: SPI master controller
|
||||
* @ctlr: SPI host controller
|
||||
* @tfr: SPI transfer
|
||||
* @bs: BCM2835 SPI controller
|
||||
* @cs: CS register
|
||||
|
@ -596,7 +596,7 @@ out:
|
|||
|
||||
/**
|
||||
* bcm2835_spi_dma_rx_done() - callback for DMA RX channel
|
||||
* @data: SPI master controller
|
||||
* @data: SPI host controller
|
||||
*
|
||||
* Used for bidirectional and RX-only transfers.
|
||||
*/
|
||||
|
@ -624,7 +624,7 @@ static void bcm2835_spi_dma_rx_done(void *data)
|
|||
|
||||
/**
|
||||
* bcm2835_spi_dma_tx_done() - callback for DMA TX channel
|
||||
* @data: SPI master controller
|
||||
* @data: SPI host controller
|
||||
*
|
||||
* Used for TX-only transfers.
|
||||
*/
|
||||
|
@ -635,7 +635,7 @@ static void bcm2835_spi_dma_tx_done(void *data)
|
|||
|
||||
/* busy-wait for TX FIFO to empty */
|
||||
while (!(bcm2835_rd(bs, BCM2835_SPI_CS) & BCM2835_SPI_CS_DONE))
|
||||
bcm2835_wr(bs, BCM2835_SPI_CS, bs->slv->clear_rx_cs);
|
||||
bcm2835_wr(bs, BCM2835_SPI_CS, bs->target->clear_rx_cs);
|
||||
|
||||
bs->tx_dma_active = false;
|
||||
smp_wmb();
|
||||
|
@ -655,10 +655,10 @@ static void bcm2835_spi_dma_tx_done(void *data)
|
|||
|
||||
/**
|
||||
* bcm2835_spi_prepare_sg() - prepare and submit DMA descriptor for sglist
|
||||
* @ctlr: SPI master controller
|
||||
* @ctlr: SPI host controller
|
||||
* @tfr: SPI transfer
|
||||
* @bs: BCM2835 SPI controller
|
||||
* @slv: BCM2835 SPI slave
|
||||
* @target: BCM2835 SPI target
|
||||
* @is_tx: whether to submit DMA descriptor for TX or RX sglist
|
||||
*
|
||||
* Prepare and submit a DMA descriptor for the TX or RX sglist of @tfr.
|
||||
|
@ -667,7 +667,7 @@ static void bcm2835_spi_dma_tx_done(void *data)
|
|||
static int bcm2835_spi_prepare_sg(struct spi_controller *ctlr,
|
||||
struct spi_transfer *tfr,
|
||||
struct bcm2835_spi *bs,
|
||||
struct bcm2835_spidev *slv,
|
||||
struct bcm2835_spidev *target,
|
||||
bool is_tx)
|
||||
{
|
||||
struct dma_chan *chan;
|
||||
|
@ -707,7 +707,7 @@ static int bcm2835_spi_prepare_sg(struct spi_controller *ctlr,
|
|||
} else if (!tfr->rx_buf) {
|
||||
desc->callback = bcm2835_spi_dma_tx_done;
|
||||
desc->callback_param = ctlr;
|
||||
bs->slv = slv;
|
||||
bs->target = target;
|
||||
}
|
||||
|
||||
/* submit it to DMA-engine */
|
||||
|
@ -718,9 +718,9 @@ static int bcm2835_spi_prepare_sg(struct spi_controller *ctlr,
|
|||
|
||||
/**
|
||||
* bcm2835_spi_transfer_one_dma() - perform SPI transfer using DMA engine
|
||||
* @ctlr: SPI master controller
|
||||
* @ctlr: SPI host controller
|
||||
* @tfr: SPI transfer
|
||||
* @slv: BCM2835 SPI slave
|
||||
* @target: BCM2835 SPI target
|
||||
* @cs: CS register
|
||||
*
|
||||
* For *bidirectional* transfers (both tx_buf and rx_buf are non-%NULL), set up
|
||||
|
@ -732,7 +732,7 @@ static int bcm2835_spi_prepare_sg(struct spi_controller *ctlr,
|
|||
* clear the RX FIFO by setting the CLEAR_RX bit in the CS register.
|
||||
*
|
||||
* The CS register value is precalculated in bcm2835_spi_setup(). Normally
|
||||
* this is called only once, on slave registration. A DMA descriptor to write
|
||||
* this is called only once, on target registration. A DMA descriptor to write
|
||||
* this value is preallocated in bcm2835_dma_init(). All that's left to do
|
||||
* when performing a TX-only transfer is to submit this descriptor to the RX
|
||||
* DMA channel. Latency is thereby minimized. The descriptor does not
|
||||
|
@ -765,7 +765,7 @@ static int bcm2835_spi_prepare_sg(struct spi_controller *ctlr,
|
|||
*/
|
||||
static int bcm2835_spi_transfer_one_dma(struct spi_controller *ctlr,
|
||||
struct spi_transfer *tfr,
|
||||
struct bcm2835_spidev *slv,
|
||||
struct bcm2835_spidev *target,
|
||||
u32 cs)
|
||||
{
|
||||
struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
|
||||
|
@ -783,7 +783,7 @@ static int bcm2835_spi_transfer_one_dma(struct spi_controller *ctlr,
|
|||
|
||||
/* setup tx-DMA */
|
||||
if (bs->tx_buf) {
|
||||
ret = bcm2835_spi_prepare_sg(ctlr, tfr, bs, slv, true);
|
||||
ret = bcm2835_spi_prepare_sg(ctlr, tfr, bs, target, true);
|
||||
} else {
|
||||
cookie = dmaengine_submit(bs->fill_tx_desc);
|
||||
ret = dma_submit_error(cookie);
|
||||
|
@ -809,9 +809,9 @@ static int bcm2835_spi_transfer_one_dma(struct spi_controller *ctlr,
|
|||
* this saves 10us or more.
|
||||
*/
|
||||
if (bs->rx_buf) {
|
||||
ret = bcm2835_spi_prepare_sg(ctlr, tfr, bs, slv, false);
|
||||
ret = bcm2835_spi_prepare_sg(ctlr, tfr, bs, target, false);
|
||||
} else {
|
||||
cookie = dmaengine_submit(slv->clear_rx_desc);
|
||||
cookie = dmaengine_submit(target->clear_rx_desc);
|
||||
ret = dma_submit_error(cookie);
|
||||
}
|
||||
if (ret) {
|
||||
|
@ -1050,10 +1050,10 @@ static int bcm2835_spi_transfer_one(struct spi_controller *ctlr,
|
|||
struct spi_transfer *tfr)
|
||||
{
|
||||
struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
|
||||
struct bcm2835_spidev *slv = spi_get_ctldata(spi);
|
||||
struct bcm2835_spidev *target = spi_get_ctldata(spi);
|
||||
unsigned long spi_hz, cdiv;
|
||||
unsigned long hz_per_byte, byte_limit;
|
||||
u32 cs = slv->prepare_cs;
|
||||
u32 cs = target->prepare_cs;
|
||||
|
||||
/* set clock */
|
||||
spi_hz = tfr->speed_hz;
|
||||
|
@ -1101,7 +1101,7 @@ static int bcm2835_spi_transfer_one(struct spi_controller *ctlr,
|
|||
* this 1 idle clock cycle pattern but runs the spi clock without gaps
|
||||
*/
|
||||
if (ctlr->can_dma && bcm2835_spi_can_dma(ctlr, spi, tfr))
|
||||
return bcm2835_spi_transfer_one_dma(ctlr, tfr, slv, cs);
|
||||
return bcm2835_spi_transfer_one_dma(ctlr, tfr, target, cs);
|
||||
|
||||
/* run in interrupt-mode */
|
||||
return bcm2835_spi_transfer_one_irq(ctlr, spi, tfr, cs, true);
|
||||
|
@ -1112,7 +1112,7 @@ static int bcm2835_spi_prepare_message(struct spi_controller *ctlr,
|
|||
{
|
||||
struct spi_device *spi = msg->spi;
|
||||
struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
|
||||
struct bcm2835_spidev *slv = spi_get_ctldata(spi);
|
||||
struct bcm2835_spidev *target = spi_get_ctldata(spi);
|
||||
int ret;
|
||||
|
||||
if (ctlr->can_dma) {
|
||||
|
@ -1131,7 +1131,7 @@ static int bcm2835_spi_prepare_message(struct spi_controller *ctlr,
|
|||
* Set up clock polarity before spi_transfer_one_message() asserts
|
||||
* chip select to avoid a gratuitous clock signal edge.
|
||||
*/
|
||||
bcm2835_wr(bs, BCM2835_SPI_CS, slv->prepare_cs);
|
||||
bcm2835_wr(bs, BCM2835_SPI_CS, target->prepare_cs);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -1163,51 +1163,51 @@ static int chip_match_name(struct gpio_chip *chip, void *data)
|
|||
|
||||
static void bcm2835_spi_cleanup(struct spi_device *spi)
|
||||
{
|
||||
struct bcm2835_spidev *slv = spi_get_ctldata(spi);
|
||||
struct bcm2835_spidev *target = spi_get_ctldata(spi);
|
||||
struct spi_controller *ctlr = spi->controller;
|
||||
|
||||
if (slv->clear_rx_desc)
|
||||
dmaengine_desc_free(slv->clear_rx_desc);
|
||||
if (target->clear_rx_desc)
|
||||
dmaengine_desc_free(target->clear_rx_desc);
|
||||
|
||||
if (slv->clear_rx_addr)
|
||||
if (target->clear_rx_addr)
|
||||
dma_unmap_single(ctlr->dma_rx->device->dev,
|
||||
slv->clear_rx_addr,
|
||||
target->clear_rx_addr,
|
||||
sizeof(u32),
|
||||
DMA_TO_DEVICE);
|
||||
|
||||
kfree(slv);
|
||||
kfree(target);
|
||||
}
|
||||
|
||||
static int bcm2835_spi_setup_dma(struct spi_controller *ctlr,
|
||||
struct spi_device *spi,
|
||||
struct bcm2835_spi *bs,
|
||||
struct bcm2835_spidev *slv)
|
||||
struct bcm2835_spidev *target)
|
||||
{
|
||||
int ret;
|
||||
|
||||
if (!ctlr->dma_rx)
|
||||
return 0;
|
||||
|
||||
slv->clear_rx_addr = dma_map_single(ctlr->dma_rx->device->dev,
|
||||
&slv->clear_rx_cs,
|
||||
sizeof(u32),
|
||||
DMA_TO_DEVICE);
|
||||
if (dma_mapping_error(ctlr->dma_rx->device->dev, slv->clear_rx_addr)) {
|
||||
target->clear_rx_addr = dma_map_single(ctlr->dma_rx->device->dev,
|
||||
&target->clear_rx_cs,
|
||||
sizeof(u32),
|
||||
DMA_TO_DEVICE);
|
||||
if (dma_mapping_error(ctlr->dma_rx->device->dev, target->clear_rx_addr)) {
|
||||
dev_err(&spi->dev, "cannot map clear_rx_cs\n");
|
||||
slv->clear_rx_addr = 0;
|
||||
target->clear_rx_addr = 0;
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
slv->clear_rx_desc = dmaengine_prep_dma_cyclic(ctlr->dma_rx,
|
||||
slv->clear_rx_addr,
|
||||
sizeof(u32), 0,
|
||||
DMA_MEM_TO_DEV, 0);
|
||||
if (!slv->clear_rx_desc) {
|
||||
target->clear_rx_desc = dmaengine_prep_dma_cyclic(ctlr->dma_rx,
|
||||
target->clear_rx_addr,
|
||||
sizeof(u32), 0,
|
||||
DMA_MEM_TO_DEV, 0);
|
||||
if (!target->clear_rx_desc) {
|
||||
dev_err(&spi->dev, "cannot prepare clear_rx_desc\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
ret = dmaengine_desc_set_reuse(slv->clear_rx_desc);
|
||||
ret = dmaengine_desc_set_reuse(target->clear_rx_desc);
|
||||
if (ret) {
|
||||
dev_err(&spi->dev, "cannot reuse clear_rx_desc\n");
|
||||
return ret;
|
||||
|
@ -1220,26 +1220,26 @@ static int bcm2835_spi_setup(struct spi_device *spi)
|
|||
{
|
||||
struct spi_controller *ctlr = spi->controller;
|
||||
struct bcm2835_spi *bs = spi_controller_get_devdata(ctlr);
|
||||
struct bcm2835_spidev *slv = spi_get_ctldata(spi);
|
||||
struct bcm2835_spidev *target = spi_get_ctldata(spi);
|
||||
struct gpio_chip *chip;
|
||||
int ret;
|
||||
u32 cs;
|
||||
|
||||
if (!slv) {
|
||||
slv = kzalloc(ALIGN(sizeof(*slv), dma_get_cache_alignment()),
|
||||
if (!target) {
|
||||
target = kzalloc(ALIGN(sizeof(*target), dma_get_cache_alignment()),
|
||||
GFP_KERNEL);
|
||||
if (!slv)
|
||||
if (!target)
|
||||
return -ENOMEM;
|
||||
|
||||
spi_set_ctldata(spi, slv);
|
||||
spi_set_ctldata(spi, target);
|
||||
|
||||
ret = bcm2835_spi_setup_dma(ctlr, spi, bs, slv);
|
||||
ret = bcm2835_spi_setup_dma(ctlr, spi, bs, target);
|
||||
if (ret)
|
||||
goto err_cleanup;
|
||||
}
|
||||
|
||||
/*
|
||||
* Precalculate SPI slave's CS register value for ->prepare_message():
|
||||
* Precalculate SPI target's CS register value for ->prepare_message():
|
||||
* The driver always uses software-controlled GPIO chip select, hence
|
||||
* set the hardware-controlled native chip select to an invalid value
|
||||
* to prevent it from interfering.
|
||||
|
@ -1249,18 +1249,18 @@ static int bcm2835_spi_setup(struct spi_device *spi)
|
|||
cs |= BCM2835_SPI_CS_CPOL;
|
||||
if (spi->mode & SPI_CPHA)
|
||||
cs |= BCM2835_SPI_CS_CPHA;
|
||||
slv->prepare_cs = cs;
|
||||
target->prepare_cs = cs;
|
||||
|
||||
/*
|
||||
* Precalculate SPI slave's CS register value to clear RX FIFO
|
||||
* Precalculate SPI target's CS register value to clear RX FIFO
|
||||
* in case of a TX-only DMA transfer.
|
||||
*/
|
||||
if (ctlr->dma_rx) {
|
||||
slv->clear_rx_cs = cs | BCM2835_SPI_CS_TA |
|
||||
target->clear_rx_cs = cs | BCM2835_SPI_CS_TA |
|
||||
BCM2835_SPI_CS_DMAEN |
|
||||
BCM2835_SPI_CS_CLEAR_RX;
|
||||
dma_sync_single_for_device(ctlr->dma_rx->device->dev,
|
||||
slv->clear_rx_addr,
|
||||
target->clear_rx_addr,
|
||||
sizeof(u32),
|
||||
DMA_TO_DEVICE);
|
||||
}
|
||||
|
@ -1328,7 +1328,7 @@ static int bcm2835_spi_probe(struct platform_device *pdev)
|
|||
struct bcm2835_spi *bs;
|
||||
int err;
|
||||
|
||||
ctlr = devm_spi_alloc_master(&pdev->dev, sizeof(*bs));
|
||||
ctlr = devm_spi_alloc_host(&pdev->dev, sizeof(*bs));
|
||||
if (!ctlr)
|
||||
return -ENOMEM;
|
||||
|
||||
|
|
|
@ -231,8 +231,8 @@ static void bcm2835aux_spi_transfer_helper(struct bcm2835aux_spi *bs)
|
|||
|
||||
static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
struct spi_master *master = dev_id;
|
||||
struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
|
||||
struct spi_controller *host = dev_id;
|
||||
struct bcm2835aux_spi *bs = spi_controller_get_devdata(host);
|
||||
|
||||
/* IRQ may be shared, so return if our interrupts are disabled */
|
||||
if (!(bcm2835aux_rd(bs, BCM2835_AUX_SPI_CNTL1) &
|
||||
|
@ -251,17 +251,17 @@ static irqreturn_t bcm2835aux_spi_interrupt(int irq, void *dev_id)
|
|||
/* and if rx_len is 0 then disable interrupts and wake up completion */
|
||||
if (!bs->rx_len) {
|
||||
bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1]);
|
||||
spi_finalize_current_transfer(master);
|
||||
spi_finalize_current_transfer(host);
|
||||
}
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int __bcm2835aux_spi_transfer_one_irq(struct spi_master *master,
|
||||
static int __bcm2835aux_spi_transfer_one_irq(struct spi_controller *host,
|
||||
struct spi_device *spi,
|
||||
struct spi_transfer *tfr)
|
||||
{
|
||||
struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
|
||||
struct bcm2835aux_spi *bs = spi_controller_get_devdata(host);
|
||||
|
||||
/* enable interrupts */
|
||||
bcm2835aux_wr(bs, BCM2835_AUX_SPI_CNTL1, bs->cntl[1] |
|
||||
|
@ -272,11 +272,11 @@ static int __bcm2835aux_spi_transfer_one_irq(struct spi_master *master,
|
|||
return 1;
|
||||
}
|
||||
|
||||
static int bcm2835aux_spi_transfer_one_irq(struct spi_master *master,
|
||||
static int bcm2835aux_spi_transfer_one_irq(struct spi_controller *host,
|
||||
struct spi_device *spi,
|
||||
struct spi_transfer *tfr)
|
||||
{
|
||||
struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
|
||||
struct bcm2835aux_spi *bs = spi_controller_get_devdata(host);
|
||||
|
||||
/* update statistics */
|
||||
bs->count_transfer_irq++;
|
||||
|
@ -294,14 +294,14 @@ static int bcm2835aux_spi_transfer_one_irq(struct spi_master *master,
|
|||
}
|
||||
|
||||
/* now run the interrupt mode */
|
||||
return __bcm2835aux_spi_transfer_one_irq(master, spi, tfr);
|
||||
return __bcm2835aux_spi_transfer_one_irq(host, spi, tfr);
|
||||
}
|
||||
|
||||
static int bcm2835aux_spi_transfer_one_poll(struct spi_master *master,
|
||||
static int bcm2835aux_spi_transfer_one_poll(struct spi_controller *host,
|
||||
struct spi_device *spi,
|
||||
struct spi_transfer *tfr)
|
||||
{
|
||||
struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
|
||||
struct bcm2835aux_spi *bs = spi_controller_get_devdata(host);
|
||||
unsigned long timeout;
|
||||
|
||||
/* update statistics */
|
||||
|
@ -328,7 +328,7 @@ static int bcm2835aux_spi_transfer_one_poll(struct spi_master *master,
|
|||
bs->tx_len, bs->rx_len);
|
||||
/* forward to interrupt handler */
|
||||
bs->count_transfer_irq_after_poll++;
|
||||
return __bcm2835aux_spi_transfer_one_irq(master,
|
||||
return __bcm2835aux_spi_transfer_one_irq(host,
|
||||
spi, tfr);
|
||||
}
|
||||
}
|
||||
|
@ -337,11 +337,11 @@ static int bcm2835aux_spi_transfer_one_poll(struct spi_master *master,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int bcm2835aux_spi_transfer_one(struct spi_master *master,
|
||||
static int bcm2835aux_spi_transfer_one(struct spi_controller *host,
|
||||
struct spi_device *spi,
|
||||
struct spi_transfer *tfr)
|
||||
{
|
||||
struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
|
||||
struct bcm2835aux_spi *bs = spi_controller_get_devdata(host);
|
||||
unsigned long spi_hz, clk_hz, speed;
|
||||
unsigned long hz_per_byte, byte_limit;
|
||||
|
||||
|
@ -392,17 +392,17 @@ static int bcm2835aux_spi_transfer_one(struct spi_master *master,
|
|||
|
||||
/* run in polling mode for short transfers */
|
||||
if (tfr->len < byte_limit)
|
||||
return bcm2835aux_spi_transfer_one_poll(master, spi, tfr);
|
||||
return bcm2835aux_spi_transfer_one_poll(host, spi, tfr);
|
||||
|
||||
/* run in interrupt mode for all others */
|
||||
return bcm2835aux_spi_transfer_one_irq(master, spi, tfr);
|
||||
return bcm2835aux_spi_transfer_one_irq(host, spi, tfr);
|
||||
}
|
||||
|
||||
static int bcm2835aux_spi_prepare_message(struct spi_master *master,
|
||||
static int bcm2835aux_spi_prepare_message(struct spi_controller *host,
|
||||
struct spi_message *msg)
|
||||
{
|
||||
struct spi_device *spi = msg->spi;
|
||||
struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
|
||||
struct bcm2835aux_spi *bs = spi_controller_get_devdata(host);
|
||||
|
||||
bs->cntl[0] = BCM2835_AUX_SPI_CNTL0_ENABLE |
|
||||
BCM2835_AUX_SPI_CNTL0_VAR_WIDTH |
|
||||
|
@ -422,20 +422,20 @@ static int bcm2835aux_spi_prepare_message(struct spi_master *master,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int bcm2835aux_spi_unprepare_message(struct spi_master *master,
|
||||
static int bcm2835aux_spi_unprepare_message(struct spi_controller *host,
|
||||
struct spi_message *msg)
|
||||
{
|
||||
struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
|
||||
struct bcm2835aux_spi *bs = spi_controller_get_devdata(host);
|
||||
|
||||
bcm2835aux_spi_reset_hw(bs);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void bcm2835aux_spi_handle_err(struct spi_master *master,
|
||||
static void bcm2835aux_spi_handle_err(struct spi_controller *host,
|
||||
struct spi_message *msg)
|
||||
{
|
||||
struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
|
||||
struct bcm2835aux_spi *bs = spi_controller_get_devdata(host);
|
||||
|
||||
bcm2835aux_spi_reset_hw(bs);
|
||||
}
|
||||
|
@ -473,18 +473,18 @@ static int bcm2835aux_spi_setup(struct spi_device *spi)
|
|||
|
||||
static int bcm2835aux_spi_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct spi_master *master;
|
||||
struct spi_controller *host;
|
||||
struct bcm2835aux_spi *bs;
|
||||
unsigned long clk_hz;
|
||||
int err;
|
||||
|
||||
master = devm_spi_alloc_master(&pdev->dev, sizeof(*bs));
|
||||
if (!master)
|
||||
host = devm_spi_alloc_host(&pdev->dev, sizeof(*bs));
|
||||
if (!host)
|
||||
return -ENOMEM;
|
||||
|
||||
platform_set_drvdata(pdev, master);
|
||||
master->mode_bits = (SPI_CPOL | SPI_CS_HIGH | SPI_NO_CS);
|
||||
master->bits_per_word_mask = SPI_BPW_MASK(8);
|
||||
platform_set_drvdata(pdev, host);
|
||||
host->mode_bits = (SPI_CPOL | SPI_CS_HIGH | SPI_NO_CS);
|
||||
host->bits_per_word_mask = SPI_BPW_MASK(8);
|
||||
/* even though the driver never officially supported native CS
|
||||
* allow a single native CS for legacy DT support purposes when
|
||||
* no cs-gpio is configured.
|
||||
|
@ -496,16 +496,16 @@ static int bcm2835aux_spi_probe(struct platform_device *pdev)
|
|||
* * cs_delay_usec: cs is always deasserted one SCK cycle after
|
||||
* a spi_transfer
|
||||
*/
|
||||
master->num_chipselect = 1;
|
||||
master->setup = bcm2835aux_spi_setup;
|
||||
master->transfer_one = bcm2835aux_spi_transfer_one;
|
||||
master->handle_err = bcm2835aux_spi_handle_err;
|
||||
master->prepare_message = bcm2835aux_spi_prepare_message;
|
||||
master->unprepare_message = bcm2835aux_spi_unprepare_message;
|
||||
master->dev.of_node = pdev->dev.of_node;
|
||||
master->use_gpio_descriptors = true;
|
||||
host->num_chipselect = 1;
|
||||
host->setup = bcm2835aux_spi_setup;
|
||||
host->transfer_one = bcm2835aux_spi_transfer_one;
|
||||
host->handle_err = bcm2835aux_spi_handle_err;
|
||||
host->prepare_message = bcm2835aux_spi_prepare_message;
|
||||
host->unprepare_message = bcm2835aux_spi_unprepare_message;
|
||||
host->dev.of_node = pdev->dev.of_node;
|
||||
host->use_gpio_descriptors = true;
|
||||
|
||||
bs = spi_master_get_devdata(master);
|
||||
bs = spi_controller_get_devdata(host);
|
||||
|
||||
/* the main area */
|
||||
bs->regs = devm_platform_ioremap_resource(pdev, 0);
|
||||
|
@ -544,15 +544,15 @@ static int bcm2835aux_spi_probe(struct platform_device *pdev)
|
|||
err = devm_request_irq(&pdev->dev, bs->irq,
|
||||
bcm2835aux_spi_interrupt,
|
||||
IRQF_SHARED,
|
||||
dev_name(&pdev->dev), master);
|
||||
dev_name(&pdev->dev), host);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "could not request IRQ: %d\n", err);
|
||||
goto out_clk_disable;
|
||||
}
|
||||
|
||||
err = spi_register_master(master);
|
||||
err = spi_register_controller(host);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "could not register SPI master: %d\n", err);
|
||||
dev_err(&pdev->dev, "could not register SPI host: %d\n", err);
|
||||
goto out_clk_disable;
|
||||
}
|
||||
|
||||
|
@ -567,12 +567,12 @@ out_clk_disable:
|
|||
|
||||
static void bcm2835aux_spi_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct spi_master *master = platform_get_drvdata(pdev);
|
||||
struct bcm2835aux_spi *bs = spi_master_get_devdata(master);
|
||||
struct spi_controller *host = platform_get_drvdata(pdev);
|
||||
struct bcm2835aux_spi *bs = spi_controller_get_devdata(host);
|
||||
|
||||
bcm2835aux_debugfs_remove(bs);
|
||||
|
||||
spi_unregister_master(master);
|
||||
spi_unregister_controller(host);
|
||||
|
||||
bcm2835aux_spi_reset_hw(bs);
|
||||
|
||||
|
|
|
@ -149,7 +149,7 @@ static ssize_t wait_mode_show(struct device *dev, struct device_attribute *attr,
|
|||
char *buf)
|
||||
{
|
||||
struct spi_controller *ctrl = dev_get_drvdata(dev);
|
||||
struct bcm63xx_hsspi *bs = spi_master_get_devdata(ctrl);
|
||||
struct bcm63xx_hsspi *bs = spi_controller_get_devdata(ctrl);
|
||||
|
||||
return sprintf(buf, "%d\n", bs->wait_mode);
|
||||
}
|
||||
|
@ -158,7 +158,7 @@ static ssize_t wait_mode_store(struct device *dev, struct device_attribute *attr
|
|||
const char *buf, size_t count)
|
||||
{
|
||||
struct spi_controller *ctrl = dev_get_drvdata(dev);
|
||||
struct bcm63xx_hsspi *bs = spi_master_get_devdata(ctrl);
|
||||
struct bcm63xx_hsspi *bs = spi_controller_get_devdata(ctrl);
|
||||
u32 val;
|
||||
|
||||
if (kstrtou32(buf, 10, &val))
|
||||
|
@ -185,7 +185,7 @@ static ssize_t xfer_mode_show(struct device *dev, struct device_attribute *attr,
|
|||
char *buf)
|
||||
{
|
||||
struct spi_controller *ctrl = dev_get_drvdata(dev);
|
||||
struct bcm63xx_hsspi *bs = spi_master_get_devdata(ctrl);
|
||||
struct bcm63xx_hsspi *bs = spi_controller_get_devdata(ctrl);
|
||||
|
||||
return sprintf(buf, "%d\n", bs->xfer_mode);
|
||||
}
|
||||
|
@ -194,7 +194,7 @@ static ssize_t xfer_mode_store(struct device *dev, struct device_attribute *attr
|
|||
const char *buf, size_t count)
|
||||
{
|
||||
struct spi_controller *ctrl = dev_get_drvdata(dev);
|
||||
struct bcm63xx_hsspi *bs = spi_master_get_devdata(ctrl);
|
||||
struct bcm63xx_hsspi *bs = spi_controller_get_devdata(ctrl);
|
||||
u32 val;
|
||||
|
||||
if (kstrtou32(buf, 10, &val))
|
||||
|
@ -262,12 +262,12 @@ static int bcm63xx_hsspi_wait_cmd(struct bcm63xx_hsspi *bs)
|
|||
return rc;
|
||||
}
|
||||
|
||||
static bool bcm63xx_prepare_prepend_transfer(struct spi_master *master,
|
||||
static bool bcm63xx_prepare_prepend_transfer(struct spi_controller *host,
|
||||
struct spi_message *msg,
|
||||
struct spi_transfer *t_prepend)
|
||||
{
|
||||
|
||||
struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
|
||||
struct bcm63xx_hsspi *bs = spi_controller_get_devdata(host);
|
||||
bool tx_only = false;
|
||||
struct spi_transfer *t;
|
||||
|
||||
|
@ -348,7 +348,7 @@ static bool bcm63xx_prepare_prepend_transfer(struct spi_master *master,
|
|||
static int bcm63xx_hsspi_do_prepend_txrx(struct spi_device *spi,
|
||||
struct spi_transfer *t)
|
||||
{
|
||||
struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
|
||||
struct bcm63xx_hsspi *bs = spi_controller_get_devdata(spi->controller);
|
||||
unsigned int chip_select = spi_get_chipselect(spi, 0);
|
||||
u16 opcode = 0, val;
|
||||
const u8 *tx = t->tx_buf;
|
||||
|
@ -467,7 +467,7 @@ static void bcm63xx_hsspi_set_clk(struct bcm63xx_hsspi *bs,
|
|||
|
||||
static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t)
|
||||
{
|
||||
struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
|
||||
struct bcm63xx_hsspi *bs = spi_controller_get_devdata(spi->controller);
|
||||
unsigned int chip_select = spi_get_chipselect(spi, 0);
|
||||
u16 opcode = 0, val;
|
||||
int pending = t->len;
|
||||
|
@ -541,7 +541,7 @@ static int bcm63xx_hsspi_do_txrx(struct spi_device *spi, struct spi_transfer *t)
|
|||
|
||||
static int bcm63xx_hsspi_setup(struct spi_device *spi)
|
||||
{
|
||||
struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
|
||||
struct bcm63xx_hsspi *bs = spi_controller_get_devdata(spi->controller);
|
||||
u32 reg;
|
||||
|
||||
reg = __raw_readl(bs->regs +
|
||||
|
@ -579,7 +579,7 @@ static int bcm63xx_hsspi_setup(struct spi_device *spi)
|
|||
static int bcm63xx_hsspi_do_dummy_cs_txrx(struct spi_device *spi,
|
||||
struct spi_message *msg)
|
||||
{
|
||||
struct bcm63xx_hsspi *bs = spi_master_get_devdata(spi->master);
|
||||
struct bcm63xx_hsspi *bs = spi_controller_get_devdata(spi->controller);
|
||||
int status = -EINVAL;
|
||||
int dummy_cs;
|
||||
bool keep_cs = false;
|
||||
|
@ -653,10 +653,10 @@ static int bcm63xx_hsspi_do_dummy_cs_txrx(struct spi_device *spi,
|
|||
return status;
|
||||
}
|
||||
|
||||
static int bcm63xx_hsspi_transfer_one(struct spi_master *master,
|
||||
static int bcm63xx_hsspi_transfer_one(struct spi_controller *host,
|
||||
struct spi_message *msg)
|
||||
{
|
||||
struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
|
||||
struct bcm63xx_hsspi *bs = spi_controller_get_devdata(host);
|
||||
struct spi_device *spi = msg->spi;
|
||||
int status = -EINVAL;
|
||||
bool prependable = false;
|
||||
|
@ -665,7 +665,7 @@ static int bcm63xx_hsspi_transfer_one(struct spi_master *master,
|
|||
mutex_lock(&bs->msg_mutex);
|
||||
|
||||
if (bs->xfer_mode != HSSPI_XFER_MODE_DUMMYCS)
|
||||
prependable = bcm63xx_prepare_prepend_transfer(master, msg, &t_prepend);
|
||||
prependable = bcm63xx_prepare_prepend_transfer(host, msg, &t_prepend);
|
||||
|
||||
if (prependable) {
|
||||
status = bcm63xx_hsspi_do_prepend_txrx(spi, &t_prepend);
|
||||
|
@ -681,7 +681,7 @@ static int bcm63xx_hsspi_transfer_one(struct spi_master *master,
|
|||
|
||||
mutex_unlock(&bs->msg_mutex);
|
||||
msg->status = status;
|
||||
spi_finalize_current_message(master);
|
||||
spi_finalize_current_message(host);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
@ -723,7 +723,7 @@ static irqreturn_t bcm63xx_hsspi_interrupt(int irq, void *dev_id)
|
|||
|
||||
static int bcm63xx_hsspi_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct spi_master *master;
|
||||
struct spi_controller *host;
|
||||
struct bcm63xx_hsspi *bs;
|
||||
void __iomem *regs;
|
||||
struct device *dev = &pdev->dev;
|
||||
|
@ -779,13 +779,13 @@ static int bcm63xx_hsspi_probe(struct platform_device *pdev)
|
|||
}
|
||||
}
|
||||
|
||||
master = spi_alloc_master(&pdev->dev, sizeof(*bs));
|
||||
if (!master) {
|
||||
host = spi_alloc_host(&pdev->dev, sizeof(*bs));
|
||||
if (!host) {
|
||||
ret = -ENOMEM;
|
||||
goto out_disable_pll_clk;
|
||||
}
|
||||
|
||||
bs = spi_master_get_devdata(master);
|
||||
bs = spi_controller_get_devdata(host);
|
||||
bs->pdev = pdev;
|
||||
bs->clk = clk;
|
||||
bs->pll_clk = pll_clk;
|
||||
|
@ -796,17 +796,17 @@ static int bcm63xx_hsspi_probe(struct platform_device *pdev)
|
|||
bs->prepend_buf = devm_kzalloc(dev, HSSPI_BUFFER_LEN, GFP_KERNEL);
|
||||
if (!bs->prepend_buf) {
|
||||
ret = -ENOMEM;
|
||||
goto out_put_master;
|
||||
goto out_put_host;
|
||||
}
|
||||
|
||||
mutex_init(&bs->bus_mutex);
|
||||
mutex_init(&bs->msg_mutex);
|
||||
init_completion(&bs->done);
|
||||
|
||||
master->mem_ops = &bcm63xx_hsspi_mem_ops;
|
||||
master->dev.of_node = dev->of_node;
|
||||
host->mem_ops = &bcm63xx_hsspi_mem_ops;
|
||||
host->dev.of_node = dev->of_node;
|
||||
if (!dev->of_node)
|
||||
master->bus_num = HSSPI_BUS_NUM;
|
||||
host->bus_num = HSSPI_BUS_NUM;
|
||||
|
||||
of_property_read_u32(dev->of_node, "num-cs", &num_cs);
|
||||
if (num_cs > 8) {
|
||||
|
@ -814,18 +814,18 @@ static int bcm63xx_hsspi_probe(struct platform_device *pdev)
|
|||
num_cs);
|
||||
num_cs = HSSPI_SPI_MAX_CS;
|
||||
}
|
||||
master->num_chipselect = num_cs;
|
||||
master->setup = bcm63xx_hsspi_setup;
|
||||
master->transfer_one_message = bcm63xx_hsspi_transfer_one;
|
||||
master->max_transfer_size = bcm63xx_hsspi_max_message_size;
|
||||
master->max_message_size = bcm63xx_hsspi_max_message_size;
|
||||
host->num_chipselect = num_cs;
|
||||
host->setup = bcm63xx_hsspi_setup;
|
||||
host->transfer_one_message = bcm63xx_hsspi_transfer_one;
|
||||
host->max_transfer_size = bcm63xx_hsspi_max_message_size;
|
||||
host->max_message_size = bcm63xx_hsspi_max_message_size;
|
||||
|
||||
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH |
|
||||
host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH |
|
||||
SPI_RX_DUAL | SPI_TX_DUAL;
|
||||
master->bits_per_word_mask = SPI_BPW_MASK(8);
|
||||
master->auto_runtime_pm = true;
|
||||
host->bits_per_word_mask = SPI_BPW_MASK(8);
|
||||
host->auto_runtime_pm = true;
|
||||
|
||||
platform_set_drvdata(pdev, master);
|
||||
platform_set_drvdata(pdev, host);
|
||||
|
||||
/* Initialize the hardware */
|
||||
__raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
|
||||
|
@ -844,7 +844,7 @@ static int bcm63xx_hsspi_probe(struct platform_device *pdev)
|
|||
pdev->name, bs);
|
||||
|
||||
if (ret)
|
||||
goto out_put_master;
|
||||
goto out_put_host;
|
||||
}
|
||||
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
|
@ -856,7 +856,7 @@ static int bcm63xx_hsspi_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
/* register and we are done */
|
||||
ret = devm_spi_register_master(dev, master);
|
||||
ret = devm_spi_register_controller(dev, host);
|
||||
if (ret)
|
||||
goto out_sysgroup_disable;
|
||||
|
||||
|
@ -868,8 +868,8 @@ out_sysgroup_disable:
|
|||
sysfs_remove_group(&pdev->dev.kobj, &bcm63xx_hsspi_group);
|
||||
out_pm_disable:
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
out_put_master:
|
||||
spi_master_put(master);
|
||||
out_put_host:
|
||||
spi_controller_put(host);
|
||||
out_disable_pll_clk:
|
||||
clk_disable_unprepare(pll_clk);
|
||||
out_disable_clk:
|
||||
|
@ -880,8 +880,8 @@ out_disable_clk:
|
|||
|
||||
static void bcm63xx_hsspi_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct spi_master *master = platform_get_drvdata(pdev);
|
||||
struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
|
||||
struct spi_controller *host = platform_get_drvdata(pdev);
|
||||
struct bcm63xx_hsspi *bs = spi_controller_get_devdata(host);
|
||||
|
||||
/* reset the hardware and block queue progress */
|
||||
__raw_writel(0, bs->regs + HSSPI_INT_MASK_REG);
|
||||
|
@ -893,10 +893,10 @@ static void bcm63xx_hsspi_remove(struct platform_device *pdev)
|
|||
#ifdef CONFIG_PM_SLEEP
|
||||
static int bcm63xx_hsspi_suspend(struct device *dev)
|
||||
{
|
||||
struct spi_master *master = dev_get_drvdata(dev);
|
||||
struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
|
||||
struct spi_controller *host = dev_get_drvdata(dev);
|
||||
struct bcm63xx_hsspi *bs = spi_controller_get_devdata(host);
|
||||
|
||||
spi_master_suspend(master);
|
||||
spi_controller_suspend(host);
|
||||
clk_disable_unprepare(bs->pll_clk);
|
||||
clk_disable_unprepare(bs->clk);
|
||||
|
||||
|
@ -905,8 +905,8 @@ static int bcm63xx_hsspi_suspend(struct device *dev)
|
|||
|
||||
static int bcm63xx_hsspi_resume(struct device *dev)
|
||||
{
|
||||
struct spi_master *master = dev_get_drvdata(dev);
|
||||
struct bcm63xx_hsspi *bs = spi_master_get_devdata(master);
|
||||
struct spi_controller *host = dev_get_drvdata(dev);
|
||||
struct bcm63xx_hsspi *bs = spi_controller_get_devdata(host);
|
||||
int ret;
|
||||
|
||||
ret = clk_prepare_enable(bs->clk);
|
||||
|
@ -921,7 +921,7 @@ static int bcm63xx_hsspi_resume(struct device *dev)
|
|||
}
|
||||
}
|
||||
|
||||
spi_master_resume(master);
|
||||
spi_controller_resume(host);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -186,7 +186,7 @@ static const unsigned int bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
|
|||
static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
|
||||
struct spi_transfer *t)
|
||||
{
|
||||
struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
|
||||
struct bcm63xx_spi *bs = spi_controller_get_devdata(spi->controller);
|
||||
u8 clk_cfg, reg;
|
||||
int i;
|
||||
|
||||
|
@ -217,7 +217,7 @@ static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
|
|||
static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first,
|
||||
unsigned int num_transfers)
|
||||
{
|
||||
struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
|
||||
struct bcm63xx_spi *bs = spi_controller_get_devdata(spi->controller);
|
||||
u16 msg_ctl;
|
||||
u16 cmd;
|
||||
unsigned int i, timeout = 0, prepend_len = 0, len = 0;
|
||||
|
@ -312,10 +312,10 @@ static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int bcm63xx_spi_transfer_one(struct spi_master *master,
|
||||
static int bcm63xx_spi_transfer_one(struct spi_controller *host,
|
||||
struct spi_message *m)
|
||||
{
|
||||
struct bcm63xx_spi *bs = spi_master_get_devdata(master);
|
||||
struct bcm63xx_spi *bs = spi_controller_get_devdata(host);
|
||||
struct spi_transfer *t, *first = NULL;
|
||||
struct spi_device *spi = m->spi;
|
||||
int status = 0;
|
||||
|
@ -385,18 +385,18 @@ static int bcm63xx_spi_transfer_one(struct spi_master *master,
|
|||
}
|
||||
exit:
|
||||
m->status = status;
|
||||
spi_finalize_current_message(master);
|
||||
spi_finalize_current_message(host);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/* This driver supports single master mode only. Hence
|
||||
/* This driver supports single host mode only. Hence
|
||||
* CMD_DONE is the only interrupt we care about
|
||||
*/
|
||||
static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
struct spi_master *master = (struct spi_master *)dev_id;
|
||||
struct bcm63xx_spi *bs = spi_master_get_devdata(master);
|
||||
struct spi_controller *host = (struct spi_controller *)dev_id;
|
||||
struct bcm63xx_spi *bs = spi_controller_get_devdata(host);
|
||||
u8 intr;
|
||||
|
||||
/* Read interupts and clear them immediately */
|
||||
|
@ -413,7 +413,7 @@ static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
|
|||
|
||||
static size_t bcm63xx_spi_max_length(struct spi_device *spi)
|
||||
{
|
||||
struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
|
||||
struct bcm63xx_spi *bs = spi_controller_get_devdata(spi->controller);
|
||||
|
||||
return bs->fifo_size;
|
||||
}
|
||||
|
@ -479,7 +479,7 @@ static int bcm63xx_spi_probe(struct platform_device *pdev)
|
|||
const unsigned long *bcm63xx_spireg;
|
||||
struct device *dev = &pdev->dev;
|
||||
int irq, bus_num;
|
||||
struct spi_master *master;
|
||||
struct spi_controller *host;
|
||||
struct clk *clk;
|
||||
struct bcm63xx_spi *bs;
|
||||
int ret;
|
||||
|
@ -525,16 +525,16 @@ static int bcm63xx_spi_probe(struct platform_device *pdev)
|
|||
if (IS_ERR(reset))
|
||||
return PTR_ERR(reset);
|
||||
|
||||
master = spi_alloc_master(dev, sizeof(*bs));
|
||||
if (!master) {
|
||||
host = spi_alloc_host(dev, sizeof(*bs));
|
||||
if (!host) {
|
||||
dev_err(dev, "out of memory\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
bs = spi_master_get_devdata(master);
|
||||
bs = spi_controller_get_devdata(host);
|
||||
init_completion(&bs->done);
|
||||
|
||||
platform_set_drvdata(pdev, master);
|
||||
platform_set_drvdata(pdev, host);
|
||||
bs->pdev = pdev;
|
||||
|
||||
bs->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &r);
|
||||
|
@ -549,21 +549,21 @@ static int bcm63xx_spi_probe(struct platform_device *pdev)
|
|||
bs->fifo_size = bs->reg_offsets[SPI_MSG_DATA_SIZE];
|
||||
|
||||
ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
|
||||
pdev->name, master);
|
||||
pdev->name, host);
|
||||
if (ret) {
|
||||
dev_err(dev, "unable to request irq\n");
|
||||
goto out_err;
|
||||
}
|
||||
|
||||
master->dev.of_node = dev->of_node;
|
||||
master->bus_num = bus_num;
|
||||
master->num_chipselect = num_cs;
|
||||
master->transfer_one_message = bcm63xx_spi_transfer_one;
|
||||
master->mode_bits = MODEBITS;
|
||||
master->bits_per_word_mask = SPI_BPW_MASK(8);
|
||||
master->max_transfer_size = bcm63xx_spi_max_length;
|
||||
master->max_message_size = bcm63xx_spi_max_length;
|
||||
master->auto_runtime_pm = true;
|
||||
host->dev.of_node = dev->of_node;
|
||||
host->bus_num = bus_num;
|
||||
host->num_chipselect = num_cs;
|
||||
host->transfer_one_message = bcm63xx_spi_transfer_one;
|
||||
host->mode_bits = MODEBITS;
|
||||
host->bits_per_word_mask = SPI_BPW_MASK(8);
|
||||
host->max_transfer_size = bcm63xx_spi_max_length;
|
||||
host->max_message_size = bcm63xx_spi_max_length;
|
||||
host->auto_runtime_pm = true;
|
||||
bs->msg_type_shift = bs->reg_offsets[SPI_MSG_TYPE_SHIFT];
|
||||
bs->msg_ctl_width = bs->reg_offsets[SPI_MSG_CTL_WIDTH];
|
||||
bs->tx_io = (u8 *)(bs->regs + bs->reg_offsets[SPI_MSG_DATA]);
|
||||
|
@ -585,7 +585,7 @@ static int bcm63xx_spi_probe(struct platform_device *pdev)
|
|||
pm_runtime_enable(&pdev->dev);
|
||||
|
||||
/* register and we are done */
|
||||
ret = devm_spi_register_master(dev, master);
|
||||
ret = devm_spi_register_controller(dev, host);
|
||||
if (ret) {
|
||||
dev_err(dev, "spi register failed\n");
|
||||
goto out_pm_disable;
|
||||
|
@ -601,14 +601,14 @@ out_pm_disable:
|
|||
out_clk_disable:
|
||||
clk_disable_unprepare(clk);
|
||||
out_err:
|
||||
spi_master_put(master);
|
||||
spi_controller_put(host);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void bcm63xx_spi_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct spi_master *master = platform_get_drvdata(pdev);
|
||||
struct bcm63xx_spi *bs = spi_master_get_devdata(master);
|
||||
struct spi_controller *host = platform_get_drvdata(pdev);
|
||||
struct bcm63xx_spi *bs = spi_controller_get_devdata(host);
|
||||
|
||||
/* reset spi block */
|
||||
bcm_spi_writeb(bs, 0, SPI_INT_MASK);
|
||||
|
@ -619,10 +619,10 @@ static void bcm63xx_spi_remove(struct platform_device *pdev)
|
|||
|
||||
static int bcm63xx_spi_suspend(struct device *dev)
|
||||
{
|
||||
struct spi_master *master = dev_get_drvdata(dev);
|
||||
struct bcm63xx_spi *bs = spi_master_get_devdata(master);
|
||||
struct spi_controller *host = dev_get_drvdata(dev);
|
||||
struct bcm63xx_spi *bs = spi_controller_get_devdata(host);
|
||||
|
||||
spi_master_suspend(master);
|
||||
spi_controller_suspend(host);
|
||||
|
||||
clk_disable_unprepare(bs->clk);
|
||||
|
||||
|
@ -631,15 +631,15 @@ static int bcm63xx_spi_suspend(struct device *dev)
|
|||
|
||||
static int bcm63xx_spi_resume(struct device *dev)
|
||||
{
|
||||
struct spi_master *master = dev_get_drvdata(dev);
|
||||
struct bcm63xx_spi *bs = spi_master_get_devdata(master);
|
||||
struct spi_controller *host = dev_get_drvdata(dev);
|
||||
struct bcm63xx_spi *bs = spi_controller_get_devdata(host);
|
||||
int ret;
|
||||
|
||||
ret = clk_prepare_enable(bs->clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
spi_master_resume(master);
|
||||
spi_controller_resume(host);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -178,7 +178,7 @@ static void butterfly_attach(struct parport *p)
|
|||
struct pardevice *pd;
|
||||
int status;
|
||||
struct butterfly *pp;
|
||||
struct spi_master *master;
|
||||
struct spi_controller *host;
|
||||
struct device *dev = p->physport->dev;
|
||||
struct pardev_cb butterfly_cb;
|
||||
|
||||
|
@ -189,12 +189,12 @@ static void butterfly_attach(struct parport *p)
|
|||
* and no way to be selective about what it binds to.
|
||||
*/
|
||||
|
||||
master = spi_alloc_master(dev, sizeof(*pp));
|
||||
if (!master) {
|
||||
host = spi_alloc_host(dev, sizeof(*pp));
|
||||
if (!host) {
|
||||
status = -ENOMEM;
|
||||
goto done;
|
||||
}
|
||||
pp = spi_master_get_devdata(master);
|
||||
pp = spi_controller_get_devdata(host);
|
||||
|
||||
/*
|
||||
* SPI and bitbang hookup
|
||||
|
@ -202,10 +202,10 @@ static void butterfly_attach(struct parport *p)
|
|||
* use default setup(), cleanup(), and transfer() methods; and
|
||||
* only bother implementing mode 0. Start it later.
|
||||
*/
|
||||
master->bus_num = 42;
|
||||
master->num_chipselect = 2;
|
||||
host->bus_num = 42;
|
||||
host->num_chipselect = 2;
|
||||
|
||||
pp->bitbang.master = master;
|
||||
pp->bitbang.master = host;
|
||||
pp->bitbang.chipselect = butterfly_chipselect;
|
||||
pp->bitbang.txrx_word[SPI_MODE_0] = butterfly_txrx_word_mode0;
|
||||
|
||||
|
@ -280,7 +280,7 @@ clean2:
|
|||
clean1:
|
||||
parport_unregister_device(pd);
|
||||
clean0:
|
||||
spi_master_put(pp->bitbang.master);
|
||||
spi_controller_put(host);
|
||||
done:
|
||||
pr_debug("%s: butterfly probe, fail %d\n", p->name, status);
|
||||
}
|
||||
|
@ -308,7 +308,7 @@ static void butterfly_detach(struct parport *p)
|
|||
parport_release(pp->pd);
|
||||
parport_unregister_device(pp->pd);
|
||||
|
||||
spi_master_put(pp->bitbang.master);
|
||||
spi_controller_put(pp->bitbang.master);
|
||||
}
|
||||
|
||||
static struct parport_driver butterfly_driver = {
|
||||
|
|
|
@ -419,7 +419,7 @@ static int cdns_xspi_mem_op_execute(struct spi_mem *mem,
|
|||
const struct spi_mem_op *op)
|
||||
{
|
||||
struct cdns_xspi_dev *cdns_xspi =
|
||||
spi_master_get_devdata(mem->spi->master);
|
||||
spi_controller_get_devdata(mem->spi->controller);
|
||||
int ret = 0;
|
||||
|
||||
ret = cdns_xspi_mem_op(cdns_xspi, mem, op);
|
||||
|
@ -430,7 +430,7 @@ static int cdns_xspi_mem_op_execute(struct spi_mem *mem,
|
|||
static int cdns_xspi_adjust_mem_op_size(struct spi_mem *mem, struct spi_mem_op *op)
|
||||
{
|
||||
struct cdns_xspi_dev *cdns_xspi =
|
||||
spi_master_get_devdata(mem->spi->master);
|
||||
spi_controller_get_devdata(mem->spi->controller);
|
||||
|
||||
op->data.nbytes = clamp_val(op->data.nbytes, 0, cdns_xspi->sdmasize);
|
||||
|
||||
|
@ -527,26 +527,26 @@ static void cdns_xspi_print_phy_config(struct cdns_xspi_dev *cdns_xspi)
|
|||
static int cdns_xspi_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct spi_master *master = NULL;
|
||||
struct spi_controller *host = NULL;
|
||||
struct cdns_xspi_dev *cdns_xspi = NULL;
|
||||
struct resource *res;
|
||||
int ret;
|
||||
|
||||
master = devm_spi_alloc_master(dev, sizeof(*cdns_xspi));
|
||||
if (!master)
|
||||
host = devm_spi_alloc_host(dev, sizeof(*cdns_xspi));
|
||||
if (!host)
|
||||
return -ENOMEM;
|
||||
|
||||
master->mode_bits = SPI_3WIRE | SPI_TX_DUAL | SPI_TX_QUAD |
|
||||
host->mode_bits = SPI_3WIRE | SPI_TX_DUAL | SPI_TX_QUAD |
|
||||
SPI_RX_DUAL | SPI_RX_QUAD | SPI_TX_OCTAL | SPI_RX_OCTAL |
|
||||
SPI_MODE_0 | SPI_MODE_3;
|
||||
|
||||
master->mem_ops = &cadence_xspi_mem_ops;
|
||||
master->dev.of_node = pdev->dev.of_node;
|
||||
master->bus_num = -1;
|
||||
host->mem_ops = &cadence_xspi_mem_ops;
|
||||
host->dev.of_node = pdev->dev.of_node;
|
||||
host->bus_num = -1;
|
||||
|
||||
platform_set_drvdata(pdev, master);
|
||||
platform_set_drvdata(pdev, host);
|
||||
|
||||
cdns_xspi = spi_master_get_devdata(master);
|
||||
cdns_xspi = spi_controller_get_devdata(host);
|
||||
cdns_xspi->pdev = pdev;
|
||||
cdns_xspi->dev = &pdev->dev;
|
||||
cdns_xspi->cur_cs = 0;
|
||||
|
@ -596,15 +596,15 @@ static int cdns_xspi_probe(struct platform_device *pdev)
|
|||
return ret;
|
||||
}
|
||||
|
||||
master->num_chipselect = 1 << cdns_xspi->hw_num_banks;
|
||||
host->num_chipselect = 1 << cdns_xspi->hw_num_banks;
|
||||
|
||||
ret = devm_spi_register_master(dev, master);
|
||||
ret = devm_spi_register_controller(dev, host);
|
||||
if (ret) {
|
||||
dev_err(dev, "Failed to register SPI master\n");
|
||||
dev_err(dev, "Failed to register SPI host\n");
|
||||
return ret;
|
||||
}
|
||||
|
||||
dev_info(dev, "Successfully registered SPI master\n");
|
||||
dev_info(dev, "Successfully registered SPI host\n");
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
@ -1,6 +1,6 @@
|
|||
// SPDX-License-Identifier: GPL-2.0-or-later
|
||||
/*
|
||||
* Cadence SPI controller driver (master and slave mode)
|
||||
* Cadence SPI controller driver (host and target mode)
|
||||
*
|
||||
* Copyright (C) 2008 - 2014 Xilinx, Inc.
|
||||
*
|
||||
|
@ -59,10 +59,10 @@
|
|||
CDNS_SPI_CR_BAUD_DIV_4)
|
||||
|
||||
/*
|
||||
* SPI Configuration Register - Baud rate and slave select
|
||||
* SPI Configuration Register - Baud rate and target select
|
||||
*
|
||||
* These are the values used in the calculation of baud rate divisor and
|
||||
* setting the slave select.
|
||||
* setting the target select.
|
||||
*/
|
||||
|
||||
#define CDNS_SPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */
|
||||
|
@ -141,20 +141,20 @@ static inline void cdns_spi_write(struct cdns_spi *xspi, u32 offset, u32 val)
|
|||
/**
|
||||
* cdns_spi_init_hw - Initialize the hardware and configure the SPI controller
|
||||
* @xspi: Pointer to the cdns_spi structure
|
||||
* @is_slave: Flag to indicate slave or master mode
|
||||
* * On reset the SPI controller is configured to slave or master mode.
|
||||
* In master mode baud rate divisor is set to 4, threshold value for TX FIFO
|
||||
* @is_target: Flag to indicate target or host mode
|
||||
* * On reset the SPI controller is configured to target or host mode.
|
||||
* In host mode baud rate divisor is set to 4, threshold value for TX FIFO
|
||||
* not full interrupt is set to 1 and size of the word to be transferred as 8 bit.
|
||||
*
|
||||
* This function initializes the SPI controller to disable and clear all the
|
||||
* interrupts, enable manual slave select and manual start, deselect all the
|
||||
* interrupts, enable manual target select and manual start, deselect all the
|
||||
* chip select lines, and enable the SPI controller.
|
||||
*/
|
||||
static void cdns_spi_init_hw(struct cdns_spi *xspi, bool is_slave)
|
||||
static void cdns_spi_init_hw(struct cdns_spi *xspi, bool is_target)
|
||||
{
|
||||
u32 ctrl_reg = 0;
|
||||
|
||||
if (!is_slave)
|
||||
if (!is_target)
|
||||
ctrl_reg |= CDNS_SPI_CR_DEFAULT;
|
||||
|
||||
if (xspi->is_decoded_cs)
|
||||
|
@ -185,10 +185,10 @@ static void cdns_spi_chipselect(struct spi_device *spi, bool is_high)
|
|||
ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
|
||||
|
||||
if (is_high) {
|
||||
/* Deselect the slave */
|
||||
/* Deselect the target */
|
||||
ctrl_reg |= CDNS_SPI_CR_SSCTRL;
|
||||
} else {
|
||||
/* Select the slave */
|
||||
/* Select the target */
|
||||
ctrl_reg &= ~CDNS_SPI_CR_SSCTRL;
|
||||
if (!(xspi->is_decoded_cs))
|
||||
ctrl_reg |= ((~(CDNS_SPI_SS0 << spi_get_chipselect(spi, 0))) <<
|
||||
|
@ -227,7 +227,7 @@ static void cdns_spi_config_clock_mode(struct spi_device *spi)
|
|||
/*
|
||||
* Just writing the CR register does not seem to apply the clock
|
||||
* setting changes. This is problematic when changing the clock
|
||||
* polarity as it will cause the SPI slave to see spurious clock
|
||||
* polarity as it will cause the SPI target to see spurious clock
|
||||
* transitions. To workaround the issue toggle the ER register.
|
||||
*/
|
||||
cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
|
||||
|
@ -406,7 +406,7 @@ static irqreturn_t cdns_spi_irq(int irq, void *dev_id)
|
|||
static int cdns_prepare_message(struct spi_controller *ctlr,
|
||||
struct spi_message *msg)
|
||||
{
|
||||
if (!spi_controller_is_slave(ctlr))
|
||||
if (!spi_controller_is_target(ctlr))
|
||||
cdns_spi_config_clock_mode(msg->spi);
|
||||
return 0;
|
||||
}
|
||||
|
@ -418,9 +418,9 @@ static int cdns_prepare_message(struct spi_controller *ctlr,
|
|||
* @transfer: Pointer to the spi_transfer structure which provides
|
||||
* information about next transfer parameters
|
||||
*
|
||||
* This function in master mode fills the TX FIFO, starts the SPI transfer and
|
||||
* This function in host mode fills the TX FIFO, starts the SPI transfer and
|
||||
* returns a positive transfer count so that core will wait for completion.
|
||||
* This function in slave mode fills the TX FIFO and wait for transfer trigger.
|
||||
* This function in target mode fills the TX FIFO and wait for transfer trigger.
|
||||
*
|
||||
* Return: Number of bytes transferred in the last transfer
|
||||
*/
|
||||
|
@ -435,7 +435,7 @@ static int cdns_transfer_one(struct spi_controller *ctlr,
|
|||
xspi->tx_bytes = transfer->len;
|
||||
xspi->rx_bytes = transfer->len;
|
||||
|
||||
if (!spi_controller_is_slave(ctlr)) {
|
||||
if (!spi_controller_is_target(ctlr)) {
|
||||
cdns_spi_setup_transfer(spi, transfer);
|
||||
} else {
|
||||
/* Set TX empty threshold to half of FIFO depth
|
||||
|
@ -457,7 +457,7 @@ static int cdns_transfer_one(struct spi_controller *ctlr,
|
|||
* @ctlr: Pointer to the spi_controller structure which provides
|
||||
* information about the controller.
|
||||
*
|
||||
* This function enables SPI master controller.
|
||||
* This function enables SPI host controller.
|
||||
*
|
||||
* Return: 0 always
|
||||
*/
|
||||
|
@ -475,7 +475,7 @@ static int cdns_prepare_transfer_hardware(struct spi_controller *ctlr)
|
|||
* @ctlr: Pointer to the spi_controller structure which provides
|
||||
* information about the controller.
|
||||
*
|
||||
* This function disables the SPI master controller when no slave selected.
|
||||
* This function disables the SPI host controller when no target selected.
|
||||
* This function flush out if any pending data in FIFO.
|
||||
*
|
||||
* Return: 0 always
|
||||
|
@ -486,15 +486,15 @@ static int cdns_unprepare_transfer_hardware(struct spi_controller *ctlr)
|
|||
u32 ctrl_reg;
|
||||
unsigned int cnt = xspi->tx_fifo_depth;
|
||||
|
||||
if (spi_controller_is_slave(ctlr)) {
|
||||
if (spi_controller_is_target(ctlr)) {
|
||||
while (cnt--)
|
||||
cdns_spi_read(xspi, CDNS_SPI_RXD);
|
||||
}
|
||||
|
||||
/* Disable the SPI if slave is deselected */
|
||||
/* Disable the SPI if target is deselected */
|
||||
ctrl_reg = cdns_spi_read(xspi, CDNS_SPI_CR);
|
||||
ctrl_reg = (ctrl_reg & CDNS_SPI_CR_SSCTRL) >> CDNS_SPI_SS_SHIFT;
|
||||
if (ctrl_reg == CDNS_SPI_NOSS || spi_controller_is_slave(ctlr))
|
||||
if (ctrl_reg == CDNS_SPI_NOSS || spi_controller_is_target(ctlr))
|
||||
cdns_spi_write(xspi, CDNS_SPI_ER, CDNS_SPI_ER_DISABLE);
|
||||
|
||||
/* Reset to default */
|
||||
|
@ -521,14 +521,14 @@ static void cdns_spi_detect_fifo_depth(struct cdns_spi *xspi)
|
|||
}
|
||||
|
||||
/**
|
||||
* cdns_slave_abort - Abort slave transfer
|
||||
* cdns_target_abort - Abort target transfer
|
||||
* @ctlr: Pointer to the spi_controller structure
|
||||
*
|
||||
* This function abort slave transfer if there any transfer timeout.
|
||||
* This function abort target transfer if there any transfer timeout.
|
||||
*
|
||||
* Return: 0 always
|
||||
*/
|
||||
static int cdns_slave_abort(struct spi_controller *ctlr)
|
||||
static int cdns_target_abort(struct spi_controller *ctlr)
|
||||
{
|
||||
struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
|
||||
u32 intr_status;
|
||||
|
@ -555,13 +555,13 @@ static int cdns_spi_probe(struct platform_device *pdev)
|
|||
struct spi_controller *ctlr;
|
||||
struct cdns_spi *xspi;
|
||||
u32 num_cs;
|
||||
bool slave;
|
||||
bool target;
|
||||
|
||||
slave = of_property_read_bool(pdev->dev.of_node, "spi-slave");
|
||||
if (slave)
|
||||
ctlr = spi_alloc_slave(&pdev->dev, sizeof(*xspi));
|
||||
target = of_property_read_bool(pdev->dev.of_node, "spi-slave");
|
||||
if (target)
|
||||
ctlr = spi_alloc_target(&pdev->dev, sizeof(*xspi));
|
||||
else
|
||||
ctlr = spi_alloc_master(&pdev->dev, sizeof(*xspi));
|
||||
ctlr = spi_alloc_host(&pdev->dev, sizeof(*xspi));
|
||||
|
||||
if (!ctlr)
|
||||
return -ENOMEM;
|
||||
|
@ -589,7 +589,7 @@ static int cdns_spi_probe(struct platform_device *pdev)
|
|||
goto remove_ctlr;
|
||||
}
|
||||
|
||||
if (!spi_controller_is_slave(ctlr)) {
|
||||
if (!spi_controller_is_target(ctlr)) {
|
||||
xspi->ref_clk = devm_clk_get(&pdev->dev, "ref_clk");
|
||||
if (IS_ERR(xspi->ref_clk)) {
|
||||
dev_err(&pdev->dev, "ref_clk clock not found.\n");
|
||||
|
@ -624,7 +624,7 @@ static int cdns_spi_probe(struct platform_device *pdev)
|
|||
cdns_spi_detect_fifo_depth(xspi);
|
||||
|
||||
/* SPI controller initializations */
|
||||
cdns_spi_init_hw(xspi, spi_controller_is_slave(ctlr));
|
||||
cdns_spi_init_hw(xspi, spi_controller_is_target(ctlr));
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0) {
|
||||
|
@ -648,7 +648,7 @@ static int cdns_spi_probe(struct platform_device *pdev)
|
|||
ctlr->mode_bits = SPI_CPOL | SPI_CPHA;
|
||||
ctlr->bits_per_word_mask = SPI_BPW_MASK(8);
|
||||
|
||||
if (!spi_controller_is_slave(ctlr)) {
|
||||
if (!spi_controller_is_target(ctlr)) {
|
||||
ctlr->mode_bits |= SPI_CS_HIGH;
|
||||
ctlr->set_cs = cdns_spi_chipselect;
|
||||
ctlr->auto_runtime_pm = true;
|
||||
|
@ -660,7 +660,7 @@ static int cdns_spi_probe(struct platform_device *pdev)
|
|||
pm_runtime_put_autosuspend(&pdev->dev);
|
||||
} else {
|
||||
ctlr->mode_bits |= SPI_NO_CS;
|
||||
ctlr->slave_abort = cdns_slave_abort;
|
||||
ctlr->target_abort = cdns_target_abort;
|
||||
}
|
||||
ret = spi_register_controller(ctlr);
|
||||
if (ret) {
|
||||
|
@ -671,7 +671,7 @@ static int cdns_spi_probe(struct platform_device *pdev)
|
|||
return ret;
|
||||
|
||||
clk_dis_all:
|
||||
if (!spi_controller_is_slave(ctlr)) {
|
||||
if (!spi_controller_is_target(ctlr)) {
|
||||
pm_runtime_set_suspended(&pdev->dev);
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
clk_disable_unprepare(xspi->ref_clk);
|
||||
|
@ -735,7 +735,7 @@ static int __maybe_unused cdns_spi_resume(struct device *dev)
|
|||
struct spi_controller *ctlr = dev_get_drvdata(dev);
|
||||
struct cdns_spi *xspi = spi_controller_get_devdata(ctlr);
|
||||
|
||||
cdns_spi_init_hw(xspi, spi_controller_is_slave(ctlr));
|
||||
cdns_spi_init_hw(xspi, spi_controller_is_target(ctlr));
|
||||
return spi_controller_resume(ctlr);
|
||||
}
|
||||
|
||||
|
|
|
@ -19,15 +19,15 @@
|
|||
static int octeon_spi_probe(struct platform_device *pdev)
|
||||
{
|
||||
void __iomem *reg_base;
|
||||
struct spi_master *master;
|
||||
struct spi_controller *host;
|
||||
struct octeon_spi *p;
|
||||
int err = -ENOENT;
|
||||
|
||||
master = spi_alloc_master(&pdev->dev, sizeof(struct octeon_spi));
|
||||
if (!master)
|
||||
host = spi_alloc_host(&pdev->dev, sizeof(struct octeon_spi));
|
||||
if (!host)
|
||||
return -ENOMEM;
|
||||
p = spi_master_get_devdata(master);
|
||||
platform_set_drvdata(pdev, master);
|
||||
p = spi_controller_get_devdata(host);
|
||||
platform_set_drvdata(pdev, host);
|
||||
|
||||
reg_base = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(reg_base)) {
|
||||
|
@ -43,21 +43,21 @@ static int octeon_spi_probe(struct platform_device *pdev)
|
|||
p->regs.tx = 0x10;
|
||||
p->regs.data = 0x80;
|
||||
|
||||
master->num_chipselect = 4;
|
||||
master->mode_bits = SPI_CPHA |
|
||||
host->num_chipselect = 4;
|
||||
host->mode_bits = SPI_CPHA |
|
||||
SPI_CPOL |
|
||||
SPI_CS_HIGH |
|
||||
SPI_LSB_FIRST |
|
||||
SPI_3WIRE;
|
||||
|
||||
master->transfer_one_message = octeon_spi_transfer_one_message;
|
||||
master->bits_per_word_mask = SPI_BPW_MASK(8);
|
||||
master->max_speed_hz = OCTEON_SPI_MAX_CLOCK_HZ;
|
||||
host->transfer_one_message = octeon_spi_transfer_one_message;
|
||||
host->bits_per_word_mask = SPI_BPW_MASK(8);
|
||||
host->max_speed_hz = OCTEON_SPI_MAX_CLOCK_HZ;
|
||||
|
||||
master->dev.of_node = pdev->dev.of_node;
|
||||
err = devm_spi_register_master(&pdev->dev, master);
|
||||
host->dev.of_node = pdev->dev.of_node;
|
||||
err = devm_spi_register_controller(&pdev->dev, host);
|
||||
if (err) {
|
||||
dev_err(&pdev->dev, "register master failed: %d\n", err);
|
||||
dev_err(&pdev->dev, "register host failed: %d\n", err);
|
||||
goto fail;
|
||||
}
|
||||
|
||||
|
@ -65,14 +65,14 @@ static int octeon_spi_probe(struct platform_device *pdev)
|
|||
|
||||
return 0;
|
||||
fail:
|
||||
spi_master_put(master);
|
||||
spi_controller_put(host);
|
||||
return err;
|
||||
}
|
||||
|
||||
static void octeon_spi_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct spi_master *master = platform_get_drvdata(pdev);
|
||||
struct octeon_spi *p = spi_master_get_devdata(master);
|
||||
struct spi_controller *host = platform_get_drvdata(pdev);
|
||||
struct octeon_spi *p = spi_controller_get_devdata(host);
|
||||
|
||||
/* Clear the CSENA* and put everything in a known state. */
|
||||
writeq(0, p->register_base + OCTEON_SPI_CFG(p));
|
||||
|
|
|
@ -20,15 +20,15 @@ static int thunderx_spi_probe(struct pci_dev *pdev,
|
|||
const struct pci_device_id *ent)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct spi_master *master;
|
||||
struct spi_controller *host;
|
||||
struct octeon_spi *p;
|
||||
int ret;
|
||||
|
||||
master = spi_alloc_master(dev, sizeof(struct octeon_spi));
|
||||
if (!master)
|
||||
host = spi_alloc_host(dev, sizeof(struct octeon_spi));
|
||||
if (!host)
|
||||
return -ENOMEM;
|
||||
|
||||
p = spi_master_get_devdata(master);
|
||||
p = spi_controller_get_devdata(host);
|
||||
|
||||
ret = pcim_enable_device(pdev);
|
||||
if (ret)
|
||||
|
@ -64,18 +64,18 @@ static int thunderx_spi_probe(struct pci_dev *pdev,
|
|||
p->sys_freq = SYS_FREQ_DEFAULT;
|
||||
dev_info(dev, "Set system clock to %u\n", p->sys_freq);
|
||||
|
||||
master->flags = SPI_CONTROLLER_HALF_DUPLEX;
|
||||
master->num_chipselect = 4;
|
||||
master->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH |
|
||||
host->flags = SPI_CONTROLLER_HALF_DUPLEX;
|
||||
host->num_chipselect = 4;
|
||||
host->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH |
|
||||
SPI_LSB_FIRST | SPI_3WIRE;
|
||||
master->transfer_one_message = octeon_spi_transfer_one_message;
|
||||
master->bits_per_word_mask = SPI_BPW_MASK(8);
|
||||
master->max_speed_hz = OCTEON_SPI_MAX_CLOCK_HZ;
|
||||
master->dev.of_node = pdev->dev.of_node;
|
||||
host->transfer_one_message = octeon_spi_transfer_one_message;
|
||||
host->bits_per_word_mask = SPI_BPW_MASK(8);
|
||||
host->max_speed_hz = OCTEON_SPI_MAX_CLOCK_HZ;
|
||||
host->dev.of_node = pdev->dev.of_node;
|
||||
|
||||
pci_set_drvdata(pdev, master);
|
||||
pci_set_drvdata(pdev, host);
|
||||
|
||||
ret = devm_spi_register_master(dev, master);
|
||||
ret = devm_spi_register_controller(dev, host);
|
||||
if (ret)
|
||||
goto error;
|
||||
|
||||
|
@ -84,16 +84,16 @@ static int thunderx_spi_probe(struct pci_dev *pdev,
|
|||
error:
|
||||
clk_disable_unprepare(p->clk);
|
||||
pci_release_regions(pdev);
|
||||
spi_master_put(master);
|
||||
spi_controller_put(host);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void thunderx_spi_remove(struct pci_dev *pdev)
|
||||
{
|
||||
struct spi_master *master = pci_get_drvdata(pdev);
|
||||
struct spi_controller *host = pci_get_drvdata(pdev);
|
||||
struct octeon_spi *p;
|
||||
|
||||
p = spi_master_get_devdata(master);
|
||||
p = spi_controller_get_devdata(host);
|
||||
if (!p)
|
||||
return;
|
||||
|
||||
|
|
|
@ -33,10 +33,10 @@ struct spi_clps711x_data {
|
|||
int len;
|
||||
};
|
||||
|
||||
static int spi_clps711x_prepare_message(struct spi_master *master,
|
||||
static int spi_clps711x_prepare_message(struct spi_controller *host,
|
||||
struct spi_message *msg)
|
||||
{
|
||||
struct spi_clps711x_data *hw = spi_master_get_devdata(master);
|
||||
struct spi_clps711x_data *hw = spi_controller_get_devdata(host);
|
||||
struct spi_device *spi = msg->spi;
|
||||
|
||||
/* Setup mode for transfer */
|
||||
|
@ -45,11 +45,11 @@ static int spi_clps711x_prepare_message(struct spi_master *master,
|
|||
SYSCON3_ADCCKNSEN : 0);
|
||||
}
|
||||
|
||||
static int spi_clps711x_transfer_one(struct spi_master *master,
|
||||
static int spi_clps711x_transfer_one(struct spi_controller *host,
|
||||
struct spi_device *spi,
|
||||
struct spi_transfer *xfer)
|
||||
{
|
||||
struct spi_clps711x_data *hw = spi_master_get_devdata(master);
|
||||
struct spi_clps711x_data *hw = spi_controller_get_devdata(host);
|
||||
u8 data;
|
||||
|
||||
clk_set_rate(hw->spi_clk, xfer->speed_hz ? : spi->max_speed_hz);
|
||||
|
@ -68,8 +68,8 @@ static int spi_clps711x_transfer_one(struct spi_master *master,
|
|||
|
||||
static irqreturn_t spi_clps711x_isr(int irq, void *dev_id)
|
||||
{
|
||||
struct spi_master *master = dev_id;
|
||||
struct spi_clps711x_data *hw = spi_master_get_devdata(master);
|
||||
struct spi_controller *host = dev_id;
|
||||
struct spi_clps711x_data *hw = spi_controller_get_devdata(host);
|
||||
u8 data;
|
||||
|
||||
/* Handle RX */
|
||||
|
@ -83,7 +83,7 @@ static irqreturn_t spi_clps711x_isr(int irq, void *dev_id)
|
|||
writel(data | SYNCIO_FRMLEN(hw->bpw) | SYNCIO_TXFRMEN,
|
||||
hw->syncio);
|
||||
} else
|
||||
spi_finalize_current_transfer(master);
|
||||
spi_finalize_current_transfer(host);
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
@ -92,26 +92,26 @@ static int spi_clps711x_probe(struct platform_device *pdev)
|
|||
{
|
||||
struct device_node *np = pdev->dev.of_node;
|
||||
struct spi_clps711x_data *hw;
|
||||
struct spi_master *master;
|
||||
struct spi_controller *host;
|
||||
int irq, ret;
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0)
|
||||
return irq;
|
||||
|
||||
master = spi_alloc_master(&pdev->dev, sizeof(*hw));
|
||||
if (!master)
|
||||
host = spi_alloc_host(&pdev->dev, sizeof(*hw));
|
||||
if (!host)
|
||||
return -ENOMEM;
|
||||
|
||||
master->use_gpio_descriptors = true;
|
||||
master->bus_num = -1;
|
||||
master->mode_bits = SPI_CPHA | SPI_CS_HIGH;
|
||||
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 8);
|
||||
master->dev.of_node = pdev->dev.of_node;
|
||||
master->prepare_message = spi_clps711x_prepare_message;
|
||||
master->transfer_one = spi_clps711x_transfer_one;
|
||||
host->use_gpio_descriptors = true;
|
||||
host->bus_num = -1;
|
||||
host->mode_bits = SPI_CPHA | SPI_CS_HIGH;
|
||||
host->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 8);
|
||||
host->dev.of_node = pdev->dev.of_node;
|
||||
host->prepare_message = spi_clps711x_prepare_message;
|
||||
host->transfer_one = spi_clps711x_transfer_one;
|
||||
|
||||
hw = spi_master_get_devdata(master);
|
||||
hw = spi_controller_get_devdata(host);
|
||||
|
||||
hw->spi_clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(hw->spi_clk)) {
|
||||
|
@ -138,16 +138,16 @@ static int spi_clps711x_probe(struct platform_device *pdev)
|
|||
readl(hw->syncio);
|
||||
|
||||
ret = devm_request_irq(&pdev->dev, irq, spi_clps711x_isr, 0,
|
||||
dev_name(&pdev->dev), master);
|
||||
dev_name(&pdev->dev), host);
|
||||
if (ret)
|
||||
goto err_out;
|
||||
|
||||
ret = devm_spi_register_master(&pdev->dev, master);
|
||||
ret = devm_spi_register_controller(&pdev->dev, host);
|
||||
if (!ret)
|
||||
return 0;
|
||||
|
||||
err_out:
|
||||
spi_master_put(master);
|
||||
spi_controller_put(host);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
|
|
@ -286,7 +286,7 @@ static void mcfqspi_transfer_msg16(struct mcfqspi *mcfqspi, unsigned count,
|
|||
|
||||
static void mcfqspi_set_cs(struct spi_device *spi, bool enable)
|
||||
{
|
||||
struct mcfqspi *mcfqspi = spi_master_get_devdata(spi->master);
|
||||
struct mcfqspi *mcfqspi = spi_controller_get_devdata(spi->controller);
|
||||
bool cs_high = spi->mode & SPI_CS_HIGH;
|
||||
|
||||
if (enable)
|
||||
|
@ -295,11 +295,11 @@ static void mcfqspi_set_cs(struct spi_device *spi, bool enable)
|
|||
mcfqspi_cs_deselect(mcfqspi, spi_get_chipselect(spi, 0), cs_high);
|
||||
}
|
||||
|
||||
static int mcfqspi_transfer_one(struct spi_master *master,
|
||||
static int mcfqspi_transfer_one(struct spi_controller *host,
|
||||
struct spi_device *spi,
|
||||
struct spi_transfer *t)
|
||||
{
|
||||
struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
|
||||
struct mcfqspi *mcfqspi = spi_controller_get_devdata(host);
|
||||
u16 qmr = MCFQSPI_QMR_MSTR;
|
||||
|
||||
qmr |= t->bits_per_word << 10;
|
||||
|
@ -323,7 +323,7 @@ static int mcfqspi_transfer_one(struct spi_master *master,
|
|||
|
||||
static int mcfqspi_setup(struct spi_device *spi)
|
||||
{
|
||||
mcfqspi_cs_deselect(spi_master_get_devdata(spi->master),
|
||||
mcfqspi_cs_deselect(spi_controller_get_devdata(spi->controller),
|
||||
spi_get_chipselect(spi, 0), spi->mode & SPI_CS_HIGH);
|
||||
|
||||
dev_dbg(&spi->dev,
|
||||
|
@ -337,7 +337,7 @@ static int mcfqspi_setup(struct spi_device *spi)
|
|||
|
||||
static int mcfqspi_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct spi_master *master;
|
||||
struct spi_controller *host;
|
||||
struct mcfqspi *mcfqspi;
|
||||
struct mcfqspi_platform_data *pdata;
|
||||
int status;
|
||||
|
@ -353,13 +353,13 @@ static int mcfqspi_probe(struct platform_device *pdev)
|
|||
return -EINVAL;
|
||||
}
|
||||
|
||||
master = spi_alloc_master(&pdev->dev, sizeof(*mcfqspi));
|
||||
if (master == NULL) {
|
||||
dev_dbg(&pdev->dev, "spi_alloc_master failed\n");
|
||||
host = spi_alloc_host(&pdev->dev, sizeof(*mcfqspi));
|
||||
if (host == NULL) {
|
||||
dev_dbg(&pdev->dev, "spi_alloc_host failed\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
mcfqspi = spi_master_get_devdata(master);
|
||||
mcfqspi = spi_controller_get_devdata(host);
|
||||
|
||||
mcfqspi->iobase = devm_platform_ioremap_resource(pdev, 0);
|
||||
if (IS_ERR(mcfqspi->iobase)) {
|
||||
|
@ -388,8 +388,8 @@ static int mcfqspi_probe(struct platform_device *pdev)
|
|||
goto fail0;
|
||||
}
|
||||
|
||||
master->bus_num = pdata->bus_num;
|
||||
master->num_chipselect = pdata->num_chipselect;
|
||||
host->bus_num = pdata->bus_num;
|
||||
host->num_chipselect = pdata->num_chipselect;
|
||||
|
||||
mcfqspi->cs_control = pdata->cs_control;
|
||||
status = mcfqspi_cs_setup(mcfqspi);
|
||||
|
@ -400,19 +400,19 @@ static int mcfqspi_probe(struct platform_device *pdev)
|
|||
|
||||
init_waitqueue_head(&mcfqspi->waitq);
|
||||
|
||||
master->mode_bits = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA;
|
||||
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
|
||||
master->setup = mcfqspi_setup;
|
||||
master->set_cs = mcfqspi_set_cs;
|
||||
master->transfer_one = mcfqspi_transfer_one;
|
||||
master->auto_runtime_pm = true;
|
||||
host->mode_bits = SPI_CS_HIGH | SPI_CPOL | SPI_CPHA;
|
||||
host->bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 16);
|
||||
host->setup = mcfqspi_setup;
|
||||
host->set_cs = mcfqspi_set_cs;
|
||||
host->transfer_one = mcfqspi_transfer_one;
|
||||
host->auto_runtime_pm = true;
|
||||
|
||||
platform_set_drvdata(pdev, master);
|
||||
platform_set_drvdata(pdev, host);
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
|
||||
status = devm_spi_register_master(&pdev->dev, master);
|
||||
status = devm_spi_register_controller(&pdev->dev, host);
|
||||
if (status) {
|
||||
dev_dbg(&pdev->dev, "spi_register_master failed\n");
|
||||
dev_dbg(&pdev->dev, "devm_spi_register_controller failed\n");
|
||||
goto fail1;
|
||||
}
|
||||
|
||||
|
@ -424,7 +424,7 @@ fail1:
|
|||
pm_runtime_disable(&pdev->dev);
|
||||
mcfqspi_cs_teardown(mcfqspi);
|
||||
fail0:
|
||||
spi_master_put(master);
|
||||
spi_controller_put(host);
|
||||
|
||||
dev_dbg(&pdev->dev, "Coldfire QSPI probe failed\n");
|
||||
|
||||
|
@ -433,8 +433,8 @@ fail0:
|
|||
|
||||
static void mcfqspi_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct spi_master *master = platform_get_drvdata(pdev);
|
||||
struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
|
||||
struct spi_controller *host = platform_get_drvdata(pdev);
|
||||
struct mcfqspi *mcfqspi = spi_controller_get_devdata(host);
|
||||
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
/* disable the hardware (set the baud rate to 0) */
|
||||
|
@ -447,11 +447,11 @@ static void mcfqspi_remove(struct platform_device *pdev)
|
|||
#ifdef CONFIG_PM_SLEEP
|
||||
static int mcfqspi_suspend(struct device *dev)
|
||||
{
|
||||
struct spi_master *master = dev_get_drvdata(dev);
|
||||
struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
|
||||
struct spi_controller *host = dev_get_drvdata(dev);
|
||||
struct mcfqspi *mcfqspi = spi_controller_get_devdata(host);
|
||||
int ret;
|
||||
|
||||
ret = spi_master_suspend(master);
|
||||
ret = spi_controller_suspend(host);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
@ -462,20 +462,20 @@ static int mcfqspi_suspend(struct device *dev)
|
|||
|
||||
static int mcfqspi_resume(struct device *dev)
|
||||
{
|
||||
struct spi_master *master = dev_get_drvdata(dev);
|
||||
struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
|
||||
struct spi_controller *host = dev_get_drvdata(dev);
|
||||
struct mcfqspi *mcfqspi = spi_controller_get_devdata(host);
|
||||
|
||||
clk_enable(mcfqspi->clk);
|
||||
|
||||
return spi_master_resume(master);
|
||||
return spi_controller_resume(host);
|
||||
}
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int mcfqspi_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct spi_master *master = dev_get_drvdata(dev);
|
||||
struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
|
||||
struct spi_controller *host = dev_get_drvdata(dev);
|
||||
struct mcfqspi *mcfqspi = spi_controller_get_devdata(host);
|
||||
|
||||
clk_disable(mcfqspi->clk);
|
||||
|
||||
|
@ -484,8 +484,8 @@ static int mcfqspi_runtime_suspend(struct device *dev)
|
|||
|
||||
static int mcfqspi_runtime_resume(struct device *dev)
|
||||
{
|
||||
struct spi_master *master = dev_get_drvdata(dev);
|
||||
struct mcfqspi *mcfqspi = spi_master_get_devdata(master);
|
||||
struct spi_controller *host = dev_get_drvdata(dev);
|
||||
struct mcfqspi *mcfqspi = spi_controller_get_devdata(host);
|
||||
|
||||
clk_enable(mcfqspi->clk);
|
||||
|
||||
|
|
|
@ -201,7 +201,7 @@ static void davinci_spi_chipselect(struct spi_device *spi, int value)
|
|||
u8 chip_sel = spi_get_chipselect(spi, 0);
|
||||
u16 spidat1 = CS_DEFAULT;
|
||||
|
||||
dspi = spi_master_get_devdata(spi->master);
|
||||
dspi = spi_controller_get_devdata(spi->controller);
|
||||
|
||||
/* program delay transfers if tx_delay is non zero */
|
||||
if (spicfg && spicfg->wdelay)
|
||||
|
@ -271,7 +271,7 @@ static int davinci_spi_setup_transfer(struct spi_device *spi,
|
|||
u32 hz = 0, spifmt = 0;
|
||||
int prescale;
|
||||
|
||||
dspi = spi_master_get_devdata(spi->master);
|
||||
dspi = spi_controller_get_devdata(spi->controller);
|
||||
spicfg = spi->controller_data;
|
||||
if (!spicfg)
|
||||
spicfg = &davinci_spi_default_cfg;
|
||||
|
@ -379,7 +379,7 @@ static int davinci_spi_of_setup(struct spi_device *spi)
|
|||
{
|
||||
struct davinci_spi_config *spicfg = spi->controller_data;
|
||||
struct device_node *np = spi->dev.of_node;
|
||||
struct davinci_spi *dspi = spi_master_get_devdata(spi->master);
|
||||
struct davinci_spi *dspi = spi_controller_get_devdata(spi->controller);
|
||||
u32 prop;
|
||||
|
||||
if (spicfg == NULL && np) {
|
||||
|
@ -411,7 +411,7 @@ static int davinci_spi_setup(struct spi_device *spi)
|
|||
struct device_node *np = spi->dev.of_node;
|
||||
bool internal_cs = true;
|
||||
|
||||
dspi = spi_master_get_devdata(spi->master);
|
||||
dspi = spi_controller_get_devdata(spi->controller);
|
||||
|
||||
if (!(spi->mode & SPI_NO_CS)) {
|
||||
if (np && spi_get_csgpiod(spi, 0))
|
||||
|
@ -441,7 +441,7 @@ static void davinci_spi_cleanup(struct spi_device *spi)
|
|||
kfree(spicfg);
|
||||
}
|
||||
|
||||
static bool davinci_spi_can_dma(struct spi_master *master,
|
||||
static bool davinci_spi_can_dma(struct spi_controller *host,
|
||||
struct spi_device *spi,
|
||||
struct spi_transfer *xfer)
|
||||
{
|
||||
|
@ -571,7 +571,7 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
|
|||
struct davinci_spi_config *spicfg;
|
||||
struct davinci_spi_platform_data *pdata;
|
||||
|
||||
dspi = spi_master_get_devdata(spi->master);
|
||||
dspi = spi_controller_get_devdata(spi->controller);
|
||||
pdata = &dspi->pdata;
|
||||
spicfg = (struct davinci_spi_config *)spi->controller_data;
|
||||
if (!spicfg)
|
||||
|
@ -592,7 +592,7 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
|
|||
|
||||
reinit_completion(&dspi->done);
|
||||
|
||||
if (!davinci_spi_can_dma(spi->master, spi, t)) {
|
||||
if (!davinci_spi_can_dma(spi->controller, spi, t)) {
|
||||
if (spicfg->io_type != SPI_IO_TYPE_POLL)
|
||||
set_io_bits(dspi->base + SPIINT, SPIINT_MASKINT);
|
||||
/* start the transfer */
|
||||
|
@ -673,7 +673,7 @@ static int davinci_spi_bufs(struct spi_device *spi, struct spi_transfer *t)
|
|||
}
|
||||
|
||||
clear_io_bits(dspi->base + SPIINT, SPIINT_MASKALL);
|
||||
if (davinci_spi_can_dma(spi->master, spi, t))
|
||||
if (davinci_spi_can_dma(spi->controller, spi, t))
|
||||
clear_io_bits(dspi->base + SPIINT, SPIINT_DMA_REQ_EN);
|
||||
|
||||
clear_io_bits(dspi->base + SPIGCR1, SPIGCR1_SPIENA_MASK);
|
||||
|
@ -855,22 +855,22 @@ static int spi_davinci_get_pdata(struct platform_device *pdev,
|
|||
*/
|
||||
static int davinci_spi_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct spi_master *master;
|
||||
struct spi_controller *host;
|
||||
struct davinci_spi *dspi;
|
||||
struct davinci_spi_platform_data *pdata;
|
||||
struct resource *r;
|
||||
int ret = 0;
|
||||
u32 spipc0;
|
||||
|
||||
master = spi_alloc_master(&pdev->dev, sizeof(struct davinci_spi));
|
||||
if (master == NULL) {
|
||||
host = spi_alloc_host(&pdev->dev, sizeof(struct davinci_spi));
|
||||
if (host == NULL) {
|
||||
ret = -ENOMEM;
|
||||
goto err;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, master);
|
||||
platform_set_drvdata(pdev, host);
|
||||
|
||||
dspi = spi_master_get_devdata(master);
|
||||
dspi = spi_controller_get_devdata(host);
|
||||
|
||||
if (dev_get_platdata(&pdev->dev)) {
|
||||
pdata = dev_get_platdata(&pdev->dev);
|
||||
|
@ -879,7 +879,7 @@ static int davinci_spi_probe(struct platform_device *pdev)
|
|||
/* update dspi pdata with that from the DT */
|
||||
ret = spi_davinci_get_pdata(pdev, dspi);
|
||||
if (ret < 0)
|
||||
goto free_master;
|
||||
goto free_host;
|
||||
}
|
||||
|
||||
/* pdata in dspi is now updated and point pdata to that */
|
||||
|
@ -891,13 +891,13 @@ static int davinci_spi_probe(struct platform_device *pdev)
|
|||
GFP_KERNEL);
|
||||
if (dspi->bytes_per_word == NULL) {
|
||||
ret = -ENOMEM;
|
||||
goto free_master;
|
||||
goto free_host;
|
||||
}
|
||||
|
||||
dspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &r);
|
||||
if (IS_ERR(dspi->base)) {
|
||||
ret = PTR_ERR(dspi->base);
|
||||
goto free_master;
|
||||
goto free_host;
|
||||
}
|
||||
dspi->pbase = r->start;
|
||||
|
||||
|
@ -905,34 +905,34 @@ static int davinci_spi_probe(struct platform_device *pdev)
|
|||
|
||||
ret = platform_get_irq(pdev, 0);
|
||||
if (ret < 0)
|
||||
goto free_master;
|
||||
goto free_host;
|
||||
dspi->irq = ret;
|
||||
|
||||
ret = devm_request_threaded_irq(&pdev->dev, dspi->irq, davinci_spi_irq,
|
||||
dummy_thread_fn, 0, dev_name(&pdev->dev), dspi);
|
||||
if (ret)
|
||||
goto free_master;
|
||||
goto free_host;
|
||||
|
||||
dspi->bitbang.master = master;
|
||||
dspi->bitbang.master = host;
|
||||
|
||||
dspi->clk = devm_clk_get(&pdev->dev, NULL);
|
||||
if (IS_ERR(dspi->clk)) {
|
||||
ret = -ENODEV;
|
||||
goto free_master;
|
||||
goto free_host;
|
||||
}
|
||||
ret = clk_prepare_enable(dspi->clk);
|
||||
if (ret)
|
||||
goto free_master;
|
||||
goto free_host;
|
||||
|
||||
master->use_gpio_descriptors = true;
|
||||
master->dev.of_node = pdev->dev.of_node;
|
||||
master->bus_num = pdev->id;
|
||||
master->num_chipselect = pdata->num_chipselect;
|
||||
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 16);
|
||||
master->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_GPIO_SS;
|
||||
master->setup = davinci_spi_setup;
|
||||
master->cleanup = davinci_spi_cleanup;
|
||||
master->can_dma = davinci_spi_can_dma;
|
||||
host->use_gpio_descriptors = true;
|
||||
host->dev.of_node = pdev->dev.of_node;
|
||||
host->bus_num = pdev->id;
|
||||
host->num_chipselect = pdata->num_chipselect;
|
||||
host->bits_per_word_mask = SPI_BPW_RANGE_MASK(2, 16);
|
||||
host->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_GPIO_SS;
|
||||
host->setup = davinci_spi_setup;
|
||||
host->cleanup = davinci_spi_cleanup;
|
||||
host->can_dma = davinci_spi_can_dma;
|
||||
|
||||
dspi->bitbang.chipselect = davinci_spi_chipselect;
|
||||
dspi->bitbang.setup_transfer = davinci_spi_setup_transfer;
|
||||
|
@ -973,7 +973,7 @@ static int davinci_spi_probe(struct platform_device *pdev)
|
|||
|
||||
iowrite32(CS_DEFAULT, dspi->base + SPIDEF);
|
||||
|
||||
/* master mode default */
|
||||
/* host mode default */
|
||||
set_io_bits(dspi->base + SPIGCR1, SPIGCR1_CLKMOD_MASK);
|
||||
set_io_bits(dspi->base + SPIGCR1, SPIGCR1_MASTER_MASK);
|
||||
set_io_bits(dspi->base + SPIGCR1, SPIGCR1_POWERDOWN_MASK);
|
||||
|
@ -993,8 +993,8 @@ free_dma:
|
|||
}
|
||||
free_clk:
|
||||
clk_disable_unprepare(dspi->clk);
|
||||
free_master:
|
||||
spi_master_put(master);
|
||||
free_host:
|
||||
spi_controller_put(host);
|
||||
err:
|
||||
return ret;
|
||||
}
|
||||
|
@ -1011,10 +1011,10 @@ err:
|
|||
static void davinci_spi_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct davinci_spi *dspi;
|
||||
struct spi_master *master;
|
||||
struct spi_controller *host;
|
||||
|
||||
master = platform_get_drvdata(pdev);
|
||||
dspi = spi_master_get_devdata(master);
|
||||
host = platform_get_drvdata(pdev);
|
||||
dspi = spi_controller_get_devdata(host);
|
||||
|
||||
spi_bitbang_stop(&dspi->bitbang);
|
||||
|
||||
|
@ -1025,7 +1025,7 @@ static void davinci_spi_remove(struct platform_device *pdev)
|
|||
dma_release_channel(dspi->dma_tx);
|
||||
}
|
||||
|
||||
spi_master_put(master);
|
||||
spi_controller_put(host);
|
||||
}
|
||||
|
||||
static struct platform_driver davinci_spi_driver = {
|
||||
|
|
|
@ -79,7 +79,7 @@
|
|||
|
||||
struct dln2_spi {
|
||||
struct platform_device *pdev;
|
||||
struct spi_master *master;
|
||||
struct spi_controller *host;
|
||||
u8 port;
|
||||
|
||||
/*
|
||||
|
@ -176,7 +176,7 @@ static int dln2_spi_cs_enable(struct dln2_spi *dln2, u8 cs_mask, bool enable)
|
|||
|
||||
static int dln2_spi_cs_enable_all(struct dln2_spi *dln2, bool enable)
|
||||
{
|
||||
u8 cs_mask = GENMASK(dln2->master->num_chipselect - 1, 0);
|
||||
u8 cs_mask = GENMASK(dln2->host->num_chipselect - 1, 0);
|
||||
|
||||
return dln2_spi_cs_enable(dln2, cs_mask, enable);
|
||||
}
|
||||
|
@ -589,11 +589,11 @@ static int dln2_spi_rdwr(struct dln2_spi *dln2, const u8 *tx_data,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int dln2_spi_prepare_message(struct spi_master *master,
|
||||
static int dln2_spi_prepare_message(struct spi_controller *host,
|
||||
struct spi_message *message)
|
||||
{
|
||||
int ret;
|
||||
struct dln2_spi *dln2 = spi_master_get_devdata(master);
|
||||
struct dln2_spi *dln2 = spi_controller_get_devdata(host);
|
||||
struct spi_device *spi = message->spi;
|
||||
|
||||
if (dln2->cs != spi_get_chipselect(spi, 0)) {
|
||||
|
@ -650,11 +650,11 @@ static int dln2_spi_transfer_setup(struct dln2_spi *dln2, u32 speed,
|
|||
return dln2_spi_enable(dln2, true);
|
||||
}
|
||||
|
||||
static int dln2_spi_transfer_one(struct spi_master *master,
|
||||
static int dln2_spi_transfer_one(struct spi_controller *host,
|
||||
struct spi_device *spi,
|
||||
struct spi_transfer *xfer)
|
||||
{
|
||||
struct dln2_spi *dln2 = spi_master_get_devdata(master);
|
||||
struct dln2_spi *dln2 = spi_controller_get_devdata(host);
|
||||
int status;
|
||||
u8 attr = 0;
|
||||
|
||||
|
@ -666,7 +666,7 @@ static int dln2_spi_transfer_one(struct spi_master *master,
|
|||
return status;
|
||||
}
|
||||
|
||||
if (!xfer->cs_change && !spi_transfer_is_last(master, xfer))
|
||||
if (!xfer->cs_change && !spi_transfer_is_last(host, xfer))
|
||||
attr = DLN2_SPI_ATTR_LEAVE_SS_LOW;
|
||||
|
||||
status = dln2_spi_rdwr(dln2, xfer->tx_buf, xfer->rx_buf,
|
||||
|
@ -679,29 +679,29 @@ static int dln2_spi_transfer_one(struct spi_master *master,
|
|||
|
||||
static int dln2_spi_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct spi_master *master;
|
||||
struct spi_controller *host;
|
||||
struct dln2_spi *dln2;
|
||||
struct dln2_platform_data *pdata = dev_get_platdata(&pdev->dev);
|
||||
struct device *dev = &pdev->dev;
|
||||
int ret;
|
||||
|
||||
master = spi_alloc_master(&pdev->dev, sizeof(*dln2));
|
||||
if (!master)
|
||||
host = spi_alloc_host(&pdev->dev, sizeof(*dln2));
|
||||
if (!host)
|
||||
return -ENOMEM;
|
||||
|
||||
device_set_node(&master->dev, dev_fwnode(dev));
|
||||
device_set_node(&host->dev, dev_fwnode(dev));
|
||||
|
||||
platform_set_drvdata(pdev, master);
|
||||
platform_set_drvdata(pdev, host);
|
||||
|
||||
dln2 = spi_master_get_devdata(master);
|
||||
dln2 = spi_controller_get_devdata(host);
|
||||
|
||||
dln2->buf = devm_kmalloc(&pdev->dev, DLN2_SPI_BUF_SIZE, GFP_KERNEL);
|
||||
if (!dln2->buf) {
|
||||
ret = -ENOMEM;
|
||||
goto exit_free_master;
|
||||
goto exit_free_host;
|
||||
}
|
||||
|
||||
dln2->master = master;
|
||||
dln2->host = host;
|
||||
dln2->pdev = pdev;
|
||||
dln2->port = pdata->port;
|
||||
/* cs/mode can never be 0xff, so the first transfer will set them */
|
||||
|
@ -712,47 +712,47 @@ static int dln2_spi_probe(struct platform_device *pdev)
|
|||
ret = dln2_spi_enable(dln2, false);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "Failed to disable SPI module\n");
|
||||
goto exit_free_master;
|
||||
goto exit_free_host;
|
||||
}
|
||||
|
||||
ret = dln2_spi_get_cs_num(dln2, &master->num_chipselect);
|
||||
ret = dln2_spi_get_cs_num(dln2, &host->num_chipselect);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "Failed to get number of CS pins\n");
|
||||
goto exit_free_master;
|
||||
goto exit_free_host;
|
||||
}
|
||||
|
||||
ret = dln2_spi_get_speed_range(dln2,
|
||||
&master->min_speed_hz,
|
||||
&master->max_speed_hz);
|
||||
&host->min_speed_hz,
|
||||
&host->max_speed_hz);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "Failed to read bus min/max freqs\n");
|
||||
goto exit_free_master;
|
||||
goto exit_free_host;
|
||||
}
|
||||
|
||||
ret = dln2_spi_get_supported_frame_sizes(dln2,
|
||||
&master->bits_per_word_mask);
|
||||
&host->bits_per_word_mask);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "Failed to read supported frame sizes\n");
|
||||
goto exit_free_master;
|
||||
goto exit_free_host;
|
||||
}
|
||||
|
||||
ret = dln2_spi_cs_enable_all(dln2, true);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "Failed to enable CS pins\n");
|
||||
goto exit_free_master;
|
||||
goto exit_free_host;
|
||||
}
|
||||
|
||||
master->bus_num = -1;
|
||||
master->mode_bits = SPI_CPOL | SPI_CPHA;
|
||||
master->prepare_message = dln2_spi_prepare_message;
|
||||
master->transfer_one = dln2_spi_transfer_one;
|
||||
master->auto_runtime_pm = true;
|
||||
host->bus_num = -1;
|
||||
host->mode_bits = SPI_CPOL | SPI_CPHA;
|
||||
host->prepare_message = dln2_spi_prepare_message;
|
||||
host->transfer_one = dln2_spi_transfer_one;
|
||||
host->auto_runtime_pm = true;
|
||||
|
||||
/* enable SPI module, we're good to go */
|
||||
ret = dln2_spi_enable(dln2, true);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "Failed to enable SPI module\n");
|
||||
goto exit_free_master;
|
||||
goto exit_free_host;
|
||||
}
|
||||
|
||||
pm_runtime_set_autosuspend_delay(&pdev->dev,
|
||||
|
@ -761,9 +761,9 @@ static int dln2_spi_probe(struct platform_device *pdev)
|
|||
pm_runtime_set_active(&pdev->dev);
|
||||
pm_runtime_enable(&pdev->dev);
|
||||
|
||||
ret = devm_spi_register_master(&pdev->dev, master);
|
||||
ret = devm_spi_register_controller(&pdev->dev, host);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "Failed to register master\n");
|
||||
dev_err(&pdev->dev, "Failed to register host\n");
|
||||
goto exit_register;
|
||||
}
|
||||
|
||||
|
@ -775,16 +775,16 @@ exit_register:
|
|||
|
||||
if (dln2_spi_enable(dln2, false) < 0)
|
||||
dev_err(&pdev->dev, "Failed to disable SPI module\n");
|
||||
exit_free_master:
|
||||
spi_master_put(master);
|
||||
exit_free_host:
|
||||
spi_controller_put(host);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void dln2_spi_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct spi_master *master = platform_get_drvdata(pdev);
|
||||
struct dln2_spi *dln2 = spi_master_get_devdata(master);
|
||||
struct spi_controller *host = platform_get_drvdata(pdev);
|
||||
struct dln2_spi *dln2 = spi_controller_get_devdata(host);
|
||||
|
||||
pm_runtime_disable(&pdev->dev);
|
||||
|
||||
|
@ -796,10 +796,10 @@ static void dln2_spi_remove(struct platform_device *pdev)
|
|||
static int dln2_spi_suspend(struct device *dev)
|
||||
{
|
||||
int ret;
|
||||
struct spi_master *master = dev_get_drvdata(dev);
|
||||
struct dln2_spi *dln2 = spi_master_get_devdata(master);
|
||||
struct spi_controller *host = dev_get_drvdata(dev);
|
||||
struct dln2_spi *dln2 = spi_controller_get_devdata(host);
|
||||
|
||||
ret = spi_master_suspend(master);
|
||||
ret = spi_controller_suspend(host);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
|
@ -824,8 +824,8 @@ static int dln2_spi_suspend(struct device *dev)
|
|||
static int dln2_spi_resume(struct device *dev)
|
||||
{
|
||||
int ret;
|
||||
struct spi_master *master = dev_get_drvdata(dev);
|
||||
struct dln2_spi *dln2 = spi_master_get_devdata(master);
|
||||
struct spi_controller *host = dev_get_drvdata(dev);
|
||||
struct dln2_spi *dln2 = spi_controller_get_devdata(host);
|
||||
|
||||
if (!pm_runtime_suspended(dev)) {
|
||||
ret = dln2_spi_cs_enable_all(dln2, true);
|
||||
|
@ -837,23 +837,23 @@ static int dln2_spi_resume(struct device *dev)
|
|||
return ret;
|
||||
}
|
||||
|
||||
return spi_master_resume(master);
|
||||
return spi_controller_resume(host);
|
||||
}
|
||||
#endif /* CONFIG_PM_SLEEP */
|
||||
|
||||
#ifdef CONFIG_PM
|
||||
static int dln2_spi_runtime_suspend(struct device *dev)
|
||||
{
|
||||
struct spi_master *master = dev_get_drvdata(dev);
|
||||
struct dln2_spi *dln2 = spi_master_get_devdata(master);
|
||||
struct spi_controller *host = dev_get_drvdata(dev);
|
||||
struct dln2_spi *dln2 = spi_controller_get_devdata(host);
|
||||
|
||||
return dln2_spi_enable(dln2, false);
|
||||
}
|
||||
|
||||
static int dln2_spi_runtime_resume(struct device *dev)
|
||||
{
|
||||
struct spi_master *master = dev_get_drvdata(dev);
|
||||
struct dln2_spi *dln2 = spi_master_get_devdata(master);
|
||||
struct spi_controller *host = dev_get_drvdata(dev);
|
||||
struct dln2_spi *dln2 = spi_controller_get_devdata(host);
|
||||
|
||||
return dln2_spi_enable(dln2, true);
|
||||
}
|
||||
|
@ -875,7 +875,7 @@ static struct platform_driver spi_dln2_driver = {
|
|||
};
|
||||
module_platform_driver(spi_dln2_driver);
|
||||
|
||||
MODULE_DESCRIPTION("Driver for the Diolan DLN2 SPI master interface");
|
||||
MODULE_DESCRIPTION("Driver for the Diolan DLN2 SPI host interface");
|
||||
MODULE_AUTHOR("Laurentiu Palcu <laurentiu.palcu@intel.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
MODULE_ALIAS("platform:dln2-spi");
|
||||
|
|
|
@ -61,7 +61,7 @@ static void dw_spi_debugfs_init(struct dw_spi *dws)
|
|||
{
|
||||
char name[32];
|
||||
|
||||
snprintf(name, 32, "dw_spi%d", dws->master->bus_num);
|
||||
snprintf(name, 32, "dw_spi%d", dws->host->bus_num);
|
||||
dws->debugfs = debugfs_create_dir(name, NULL);
|
||||
|
||||
dws->regset.regs = dw_spi_dbgfs_regs;
|
||||
|
@ -183,25 +183,25 @@ int dw_spi_check_status(struct dw_spi *dws, bool raw)
|
|||
irq_status = dw_readl(dws, DW_SPI_ISR);
|
||||
|
||||
if (irq_status & DW_SPI_INT_RXOI) {
|
||||
dev_err(&dws->master->dev, "RX FIFO overflow detected\n");
|
||||
dev_err(&dws->host->dev, "RX FIFO overflow detected\n");
|
||||
ret = -EIO;
|
||||
}
|
||||
|
||||
if (irq_status & DW_SPI_INT_RXUI) {
|
||||
dev_err(&dws->master->dev, "RX FIFO underflow detected\n");
|
||||
dev_err(&dws->host->dev, "RX FIFO underflow detected\n");
|
||||
ret = -EIO;
|
||||
}
|
||||
|
||||
if (irq_status & DW_SPI_INT_TXOI) {
|
||||
dev_err(&dws->master->dev, "TX FIFO overflow detected\n");
|
||||
dev_err(&dws->host->dev, "TX FIFO overflow detected\n");
|
||||
ret = -EIO;
|
||||
}
|
||||
|
||||
/* Generically handle the erroneous situation */
|
||||
if (ret) {
|
||||
dw_spi_reset_chip(dws);
|
||||
if (dws->master->cur_msg)
|
||||
dws->master->cur_msg->status = ret;
|
||||
if (dws->host->cur_msg)
|
||||
dws->host->cur_msg->status = ret;
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
@ -213,7 +213,7 @@ static irqreturn_t dw_spi_transfer_handler(struct dw_spi *dws)
|
|||
u16 irq_status = dw_readl(dws, DW_SPI_ISR);
|
||||
|
||||
if (dw_spi_check_status(dws, false)) {
|
||||
spi_finalize_current_transfer(dws->master);
|
||||
spi_finalize_current_transfer(dws->host);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
|
@ -227,7 +227,7 @@ static irqreturn_t dw_spi_transfer_handler(struct dw_spi *dws)
|
|||
dw_reader(dws);
|
||||
if (!dws->rx_len) {
|
||||
dw_spi_mask_intr(dws, 0xff);
|
||||
spi_finalize_current_transfer(dws->master);
|
||||
spi_finalize_current_transfer(dws->host);
|
||||
} else if (dws->rx_len <= dw_readl(dws, DW_SPI_RXFTLR)) {
|
||||
dw_writel(dws, DW_SPI_RXFTLR, dws->rx_len - 1);
|
||||
}
|
||||
|
@ -248,14 +248,14 @@ static irqreturn_t dw_spi_transfer_handler(struct dw_spi *dws)
|
|||
|
||||
static irqreturn_t dw_spi_irq(int irq, void *dev_id)
|
||||
{
|
||||
struct spi_controller *master = dev_id;
|
||||
struct dw_spi *dws = spi_controller_get_devdata(master);
|
||||
struct spi_controller *host = dev_id;
|
||||
struct dw_spi *dws = spi_controller_get_devdata(host);
|
||||
u16 irq_status = dw_readl(dws, DW_SPI_ISR) & DW_SPI_INT_MASK;
|
||||
|
||||
if (!irq_status)
|
||||
return IRQ_NONE;
|
||||
|
||||
if (!master->cur_msg) {
|
||||
if (!host->cur_msg) {
|
||||
dw_spi_mask_intr(dws, 0xff);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
@ -408,11 +408,11 @@ static int dw_spi_poll_transfer(struct dw_spi *dws,
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int dw_spi_transfer_one(struct spi_controller *master,
|
||||
static int dw_spi_transfer_one(struct spi_controller *host,
|
||||
struct spi_device *spi,
|
||||
struct spi_transfer *transfer)
|
||||
{
|
||||
struct dw_spi *dws = spi_controller_get_devdata(master);
|
||||
struct dw_spi *dws = spi_controller_get_devdata(host);
|
||||
struct dw_spi_cfg cfg = {
|
||||
.tmode = DW_SPI_CTRLR0_TMOD_TR,
|
||||
.dfs = transfer->bits_per_word,
|
||||
|
@ -440,8 +440,8 @@ static int dw_spi_transfer_one(struct spi_controller *master,
|
|||
transfer->effective_speed_hz = dws->current_freq;
|
||||
|
||||
/* Check if current transfer is a DMA transaction */
|
||||
if (master->can_dma && master->can_dma(master, spi, transfer))
|
||||
dws->dma_mapped = master->cur_msg_mapped;
|
||||
if (host->can_dma && host->can_dma(host, spi, transfer))
|
||||
dws->dma_mapped = host->cur_msg_mapped;
|
||||
|
||||
/* For poll mode just disable all interrupts */
|
||||
dw_spi_mask_intr(dws, 0xff);
|
||||
|
@ -464,10 +464,10 @@ static int dw_spi_transfer_one(struct spi_controller *master,
|
|||
return 1;
|
||||
}
|
||||
|
||||
static void dw_spi_handle_err(struct spi_controller *master,
|
||||
static void dw_spi_handle_err(struct spi_controller *host,
|
||||
struct spi_message *msg)
|
||||
{
|
||||
struct dw_spi *dws = spi_controller_get_devdata(master);
|
||||
struct dw_spi *dws = spi_controller_get_devdata(host);
|
||||
|
||||
if (dws->dma_mapped)
|
||||
dws->dma_ops->dma_stop(dws);
|
||||
|
@ -576,7 +576,7 @@ static int dw_spi_write_then_read(struct dw_spi *dws, struct spi_device *spi)
|
|||
while (len) {
|
||||
entries = readl_relaxed(dws->regs + DW_SPI_TXFLR);
|
||||
if (!entries) {
|
||||
dev_err(&dws->master->dev, "CS de-assertion on Tx\n");
|
||||
dev_err(&dws->host->dev, "CS de-assertion on Tx\n");
|
||||
return -EIO;
|
||||
}
|
||||
room = min(dws->fifo_len - entries, len);
|
||||
|
@ -596,7 +596,7 @@ static int dw_spi_write_then_read(struct dw_spi *dws, struct spi_device *spi)
|
|||
if (!entries) {
|
||||
sts = readl_relaxed(dws->regs + DW_SPI_RISR);
|
||||
if (sts & DW_SPI_INT_RXOI) {
|
||||
dev_err(&dws->master->dev, "FIFO overflow on Rx\n");
|
||||
dev_err(&dws->host->dev, "FIFO overflow on Rx\n");
|
||||
return -EIO;
|
||||
}
|
||||
continue;
|
||||
|
@ -637,7 +637,7 @@ static int dw_spi_wait_mem_op_done(struct dw_spi *dws)
|
|||
spi_delay_exec(&delay, NULL);
|
||||
|
||||
if (retry < 0) {
|
||||
dev_err(&dws->master->dev, "Mem op hanged up\n");
|
||||
dev_err(&dws->host->dev, "Mem op hanged up\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
|
@ -884,56 +884,56 @@ static void dw_spi_hw_init(struct device *dev, struct dw_spi *dws)
|
|||
|
||||
int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
|
||||
{
|
||||
struct spi_controller *master;
|
||||
struct spi_controller *host;
|
||||
int ret;
|
||||
|
||||
if (!dws)
|
||||
return -EINVAL;
|
||||
|
||||
master = spi_alloc_master(dev, 0);
|
||||
if (!master)
|
||||
host = spi_alloc_host(dev, 0);
|
||||
if (!host)
|
||||
return -ENOMEM;
|
||||
|
||||
device_set_node(&master->dev, dev_fwnode(dev));
|
||||
device_set_node(&host->dev, dev_fwnode(dev));
|
||||
|
||||
dws->master = master;
|
||||
dws->host = host;
|
||||
dws->dma_addr = (dma_addr_t)(dws->paddr + DW_SPI_DR);
|
||||
|
||||
spi_controller_set_devdata(master, dws);
|
||||
spi_controller_set_devdata(host, dws);
|
||||
|
||||
/* Basic HW init */
|
||||
dw_spi_hw_init(dev, dws);
|
||||
|
||||
ret = request_irq(dws->irq, dw_spi_irq, IRQF_SHARED, dev_name(dev),
|
||||
master);
|
||||
host);
|
||||
if (ret < 0 && ret != -ENOTCONN) {
|
||||
dev_err(dev, "can not get IRQ\n");
|
||||
goto err_free_master;
|
||||
goto err_free_host;
|
||||
}
|
||||
|
||||
dw_spi_init_mem_ops(dws);
|
||||
|
||||
master->use_gpio_descriptors = true;
|
||||
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
|
||||
host->use_gpio_descriptors = true;
|
||||
host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
|
||||
if (dws->caps & DW_SPI_CAP_DFS32)
|
||||
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
|
||||
host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
|
||||
else
|
||||
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
|
||||
master->bus_num = dws->bus_num;
|
||||
master->num_chipselect = dws->num_cs;
|
||||
master->setup = dw_spi_setup;
|
||||
master->cleanup = dw_spi_cleanup;
|
||||
host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16);
|
||||
host->bus_num = dws->bus_num;
|
||||
host->num_chipselect = dws->num_cs;
|
||||
host->setup = dw_spi_setup;
|
||||
host->cleanup = dw_spi_cleanup;
|
||||
if (dws->set_cs)
|
||||
master->set_cs = dws->set_cs;
|
||||
host->set_cs = dws->set_cs;
|
||||
else
|
||||
master->set_cs = dw_spi_set_cs;
|
||||
master->transfer_one = dw_spi_transfer_one;
|
||||
master->handle_err = dw_spi_handle_err;
|
||||
host->set_cs = dw_spi_set_cs;
|
||||
host->transfer_one = dw_spi_transfer_one;
|
||||
host->handle_err = dw_spi_handle_err;
|
||||
if (dws->mem_ops.exec_op)
|
||||
master->mem_ops = &dws->mem_ops;
|
||||
master->max_speed_hz = dws->max_freq;
|
||||
master->flags = SPI_CONTROLLER_GPIO_SS;
|
||||
master->auto_runtime_pm = true;
|
||||
host->mem_ops = &dws->mem_ops;
|
||||
host->max_speed_hz = dws->max_freq;
|
||||
host->flags = SPI_CONTROLLER_GPIO_SS;
|
||||
host->auto_runtime_pm = true;
|
||||
|
||||
/* Get default rx sample delay */
|
||||
device_property_read_u32(dev, "rx-sample-delay-ns",
|
||||
|
@ -946,14 +946,14 @@ int dw_spi_add_host(struct device *dev, struct dw_spi *dws)
|
|||
} else if (ret) {
|
||||
dev_warn(dev, "DMA init failed\n");
|
||||
} else {
|
||||
master->can_dma = dws->dma_ops->can_dma;
|
||||
master->flags |= SPI_CONTROLLER_MUST_TX;
|
||||
host->can_dma = dws->dma_ops->can_dma;
|
||||
host->flags |= SPI_CONTROLLER_MUST_TX;
|
||||
}
|
||||
}
|
||||
|
||||
ret = spi_register_controller(master);
|
||||
ret = spi_register_controller(host);
|
||||
if (ret) {
|
||||
dev_err_probe(dev, ret, "problem registering spi master\n");
|
||||
dev_err_probe(dev, ret, "problem registering spi host\n");
|
||||
goto err_dma_exit;
|
||||
}
|
||||
|
||||
|
@ -965,9 +965,9 @@ err_dma_exit:
|
|||
dws->dma_ops->dma_exit(dws);
|
||||
dw_spi_enable_chip(dws, 0);
|
||||
err_free_irq:
|
||||
free_irq(dws->irq, master);
|
||||
err_free_master:
|
||||
spi_controller_put(master);
|
||||
free_irq(dws->irq, host);
|
||||
err_free_host:
|
||||
spi_controller_put(host);
|
||||
return ret;
|
||||
}
|
||||
EXPORT_SYMBOL_NS_GPL(dw_spi_add_host, SPI_DW_CORE);
|
||||
|
@ -976,14 +976,14 @@ void dw_spi_remove_host(struct dw_spi *dws)
|
|||
{
|
||||
dw_spi_debugfs_remove(dws);
|
||||
|
||||
spi_unregister_controller(dws->master);
|
||||
spi_unregister_controller(dws->host);
|
||||
|
||||
if (dws->dma_ops && dws->dma_ops->dma_exit)
|
||||
dws->dma_ops->dma_exit(dws);
|
||||
|
||||
dw_spi_shutdown_chip(dws);
|
||||
|
||||
free_irq(dws->irq, dws->master);
|
||||
free_irq(dws->irq, dws->host);
|
||||
}
|
||||
EXPORT_SYMBOL_NS_GPL(dw_spi_remove_host, SPI_DW_CORE);
|
||||
|
||||
|
@ -991,7 +991,7 @@ int dw_spi_suspend_host(struct dw_spi *dws)
|
|||
{
|
||||
int ret;
|
||||
|
||||
ret = spi_controller_suspend(dws->master);
|
||||
ret = spi_controller_suspend(dws->host);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
|
@ -1002,8 +1002,8 @@ EXPORT_SYMBOL_NS_GPL(dw_spi_suspend_host, SPI_DW_CORE);
|
|||
|
||||
int dw_spi_resume_host(struct dw_spi *dws)
|
||||
{
|
||||
dw_spi_hw_init(&dws->master->dev, dws);
|
||||
return spi_controller_resume(dws->master);
|
||||
dw_spi_hw_init(&dws->host->dev, dws);
|
||||
return spi_controller_resume(dws->host);
|
||||
}
|
||||
EXPORT_SYMBOL_NS_GPL(dw_spi_resume_host, SPI_DW_CORE);
|
||||
|
||||
|
|
|
@ -139,8 +139,8 @@ static int dw_spi_dma_init_mfld(struct device *dev, struct dw_spi *dws)
|
|||
if (!dws->txchan)
|
||||
goto free_rxchan;
|
||||
|
||||
dws->master->dma_rx = dws->rxchan;
|
||||
dws->master->dma_tx = dws->txchan;
|
||||
dws->host->dma_rx = dws->rxchan;
|
||||
dws->host->dma_tx = dws->txchan;
|
||||
|
||||
init_completion(&dws->dma_completion);
|
||||
|
||||
|
@ -183,8 +183,8 @@ static int dw_spi_dma_init_generic(struct device *dev, struct dw_spi *dws)
|
|||
goto free_rxchan;
|
||||
}
|
||||
|
||||
dws->master->dma_rx = dws->rxchan;
|
||||
dws->master->dma_tx = dws->txchan;
|
||||
dws->host->dma_rx = dws->rxchan;
|
||||
dws->host->dma_tx = dws->txchan;
|
||||
|
||||
init_completion(&dws->dma_completion);
|
||||
|
||||
|
@ -242,10 +242,10 @@ static enum dma_slave_buswidth dw_spi_dma_convert_width(u8 n_bytes)
|
|||
}
|
||||
}
|
||||
|
||||
static bool dw_spi_can_dma(struct spi_controller *master,
|
||||
static bool dw_spi_can_dma(struct spi_controller *host,
|
||||
struct spi_device *spi, struct spi_transfer *xfer)
|
||||
{
|
||||
struct dw_spi *dws = spi_controller_get_devdata(master);
|
||||
struct dw_spi *dws = spi_controller_get_devdata(host);
|
||||
enum dma_slave_buswidth dma_bus_width;
|
||||
|
||||
if (xfer->len <= dws->fifo_len)
|
||||
|
@ -271,7 +271,7 @@ static int dw_spi_dma_wait(struct dw_spi *dws, unsigned int len, u32 speed)
|
|||
msecs_to_jiffies(ms));
|
||||
|
||||
if (ms == 0) {
|
||||
dev_err(&dws->master->cur_msg->spi->dev,
|
||||
dev_err(&dws->host->cur_msg->spi->dev,
|
||||
"DMA transaction timed out\n");
|
||||
return -ETIMEDOUT;
|
||||
}
|
||||
|
@ -299,7 +299,7 @@ static int dw_spi_dma_wait_tx_done(struct dw_spi *dws,
|
|||
spi_delay_exec(&delay, xfer);
|
||||
|
||||
if (retry < 0) {
|
||||
dev_err(&dws->master->dev, "Tx hanged up\n");
|
||||
dev_err(&dws->host->dev, "Tx hanged up\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
|
@ -400,7 +400,7 @@ static int dw_spi_dma_wait_rx_done(struct dw_spi *dws)
|
|||
spi_delay_exec(&delay, NULL);
|
||||
|
||||
if (retry < 0) {
|
||||
dev_err(&dws->master->dev, "Rx hanged up\n");
|
||||
dev_err(&dws->host->dev, "Rx hanged up\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
|
@ -656,13 +656,13 @@ static int dw_spi_dma_transfer(struct dw_spi *dws, struct spi_transfer *xfer)
|
|||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (dws->master->cur_msg->status == -EINPROGRESS) {
|
||||
if (dws->host->cur_msg->status == -EINPROGRESS) {
|
||||
ret = dw_spi_dma_wait_tx_done(dws, xfer);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
if (xfer->rx_buf && dws->master->cur_msg->status == -EINPROGRESS)
|
||||
if (xfer->rx_buf && dws->host->cur_msg->status == -EINPROGRESS)
|
||||
ret = dw_spi_dma_wait_rx_done(dws);
|
||||
|
||||
return ret;
|
||||
|
|
|
@ -68,7 +68,7 @@ struct dw_spi_mscc {
|
|||
((((val) << 1) | BIT(0)) << ELBA_SPICS_OFFSET(cs))
|
||||
|
||||
/*
|
||||
* The Designware SPI controller (referred to as master in the documentation)
|
||||
* The Designware SPI controller (referred to as host in the documentation)
|
||||
* automatically deasserts chip select when the tx fifo is empty. The chip
|
||||
* selects then needs to be either driven as GPIOs or, for the first 4 using
|
||||
* the SPI boot controller registers. the final chip select is an OR gate
|
||||
|
@ -76,7 +76,7 @@ struct dw_spi_mscc {
|
|||
*/
|
||||
static void dw_spi_mscc_set_cs(struct spi_device *spi, bool enable)
|
||||
{
|
||||
struct dw_spi *dws = spi_master_get_devdata(spi->master);
|
||||
struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
|
||||
struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
|
||||
struct dw_spi_mscc *dwsmscc = dwsmmio->priv;
|
||||
u32 cs = spi_get_chipselect(spi, 0);
|
||||
|
@ -142,14 +142,14 @@ static int dw_spi_mscc_jaguar2_init(struct platform_device *pdev,
|
|||
}
|
||||
|
||||
/*
|
||||
* The Designware SPI controller (referred to as master in the
|
||||
* The Designware SPI controller (referred to as host in the
|
||||
* documentation) automatically deasserts chip select when the tx fifo
|
||||
* is empty. The chip selects then needs to be driven by a CS override
|
||||
* register. enable is an active low signal.
|
||||
*/
|
||||
static void dw_spi_sparx5_set_cs(struct spi_device *spi, bool enable)
|
||||
{
|
||||
struct dw_spi *dws = spi_master_get_devdata(spi->master);
|
||||
struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
|
||||
struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
|
||||
struct dw_spi_mscc *dwsmscc = dwsmmio->priv;
|
||||
u8 cs = spi_get_chipselect(spi, 0);
|
||||
|
@ -277,7 +277,7 @@ static void dw_spi_elba_override_cs(struct regmap *syscon, int cs, int enable)
|
|||
|
||||
static void dw_spi_elba_set_cs(struct spi_device *spi, bool enable)
|
||||
{
|
||||
struct dw_spi *dws = spi_master_get_devdata(spi->master);
|
||||
struct dw_spi *dws = spi_controller_get_devdata(spi->controller);
|
||||
struct dw_spi_mmio *dwsmmio = container_of(dws, struct dw_spi_mmio, dws);
|
||||
struct regmap *syscon = dwsmmio->priv;
|
||||
u8 cs;
|
||||
|
|
|
@ -142,14 +142,14 @@ struct dw_spi_dma_ops {
|
|||
int (*dma_init)(struct device *dev, struct dw_spi *dws);
|
||||
void (*dma_exit)(struct dw_spi *dws);
|
||||
int (*dma_setup)(struct dw_spi *dws, struct spi_transfer *xfer);
|
||||
bool (*can_dma)(struct spi_controller *master, struct spi_device *spi,
|
||||
bool (*can_dma)(struct spi_controller *host, struct spi_device *spi,
|
||||
struct spi_transfer *xfer);
|
||||
int (*dma_transfer)(struct dw_spi *dws, struct spi_transfer *xfer);
|
||||
void (*dma_stop)(struct dw_spi *dws);
|
||||
};
|
||||
|
||||
struct dw_spi {
|
||||
struct spi_controller *master;
|
||||
struct spi_controller *host;
|
||||
|
||||
u32 ip; /* Synopsys DW SSI IP-core ID */
|
||||
u32 ver; /* Synopsys component version */
|
||||
|
|
|
@ -164,10 +164,10 @@ static int hisi_spi_debugfs_init(struct hisi_spi *hs)
|
|||
{
|
||||
char name[32];
|
||||
|
||||
struct spi_controller *master;
|
||||
struct spi_controller *host;
|
||||
|
||||
master = container_of(hs->dev, struct spi_controller, dev);
|
||||
snprintf(name, 32, "hisi_spi%d", master->bus_num);
|
||||
host = container_of(hs->dev, struct spi_controller, dev);
|
||||
snprintf(name, 32, "hisi_spi%d", host->bus_num);
|
||||
hs->debugfs = debugfs_create_dir(name, NULL);
|
||||
if (IS_ERR(hs->debugfs))
|
||||
return -ENOMEM;
|
||||
|
@ -291,18 +291,18 @@ static void __hisi_calc_div_reg(struct hisi_chip_data *chip)
|
|||
chip->div_post = (chip->clk_div / chip->div_pre) - 1;
|
||||
}
|
||||
|
||||
static u32 hisi_calc_effective_speed(struct spi_controller *master,
|
||||
static u32 hisi_calc_effective_speed(struct spi_controller *host,
|
||||
struct hisi_chip_data *chip, u32 speed_hz)
|
||||
{
|
||||
u32 effective_speed;
|
||||
|
||||
/* Note clock divider doesn't support odd numbers */
|
||||
chip->clk_div = DIV_ROUND_UP(master->max_speed_hz, speed_hz) + 1;
|
||||
chip->clk_div = DIV_ROUND_UP(host->max_speed_hz, speed_hz) + 1;
|
||||
chip->clk_div &= 0xfffe;
|
||||
if (chip->clk_div > CLK_DIV_MAX)
|
||||
chip->clk_div = CLK_DIV_MAX;
|
||||
|
||||
effective_speed = master->max_speed_hz / chip->clk_div;
|
||||
effective_speed = host->max_speed_hz / chip->clk_div;
|
||||
if (chip->speed_hz != effective_speed) {
|
||||
__hisi_calc_div_reg(chip);
|
||||
chip->speed_hz = effective_speed;
|
||||
|
@ -336,20 +336,20 @@ static void hisi_spi_hw_init(struct hisi_spi *hs)
|
|||
|
||||
static irqreturn_t hisi_spi_irq(int irq, void *dev_id)
|
||||
{
|
||||
struct spi_controller *master = dev_id;
|
||||
struct hisi_spi *hs = spi_controller_get_devdata(master);
|
||||
struct spi_controller *host = dev_id;
|
||||
struct hisi_spi *hs = spi_controller_get_devdata(host);
|
||||
u32 irq_status = readl(hs->regs + HISI_SPI_ISR) & ISR_MASK;
|
||||
|
||||
if (!irq_status)
|
||||
return IRQ_NONE;
|
||||
|
||||
if (!master->cur_msg)
|
||||
if (!host->cur_msg)
|
||||
return IRQ_HANDLED;
|
||||
|
||||
/* Error handling */
|
||||
if (irq_status & ISR_RXOF) {
|
||||
dev_err(hs->dev, "interrupt_transfer: fifo overflow\n");
|
||||
master->cur_msg->status = -EIO;
|
||||
host->cur_msg->status = -EIO;
|
||||
goto finalize_transfer;
|
||||
}
|
||||
|
||||
|
@ -369,20 +369,20 @@ static irqreturn_t hisi_spi_irq(int irq, void *dev_id)
|
|||
|
||||
finalize_transfer:
|
||||
hisi_spi_disable(hs);
|
||||
spi_finalize_current_transfer(master);
|
||||
spi_finalize_current_transfer(host);
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int hisi_spi_transfer_one(struct spi_controller *master,
|
||||
static int hisi_spi_transfer_one(struct spi_controller *host,
|
||||
struct spi_device *spi, struct spi_transfer *transfer)
|
||||
{
|
||||
struct hisi_spi *hs = spi_controller_get_devdata(master);
|
||||
struct hisi_spi *hs = spi_controller_get_devdata(host);
|
||||
struct hisi_chip_data *chip = spi_get_ctldata(spi);
|
||||
u32 cr = chip->cr;
|
||||
|
||||
/* Update per transfer options for speed and bpw */
|
||||
transfer->effective_speed_hz =
|
||||
hisi_calc_effective_speed(master, chip, transfer->speed_hz);
|
||||
hisi_calc_effective_speed(host, chip, transfer->speed_hz);
|
||||
cr |= FIELD_PREP(CR_DIV_PRE_MASK, chip->div_pre);
|
||||
cr |= FIELD_PREP(CR_DIV_POST_MASK, chip->div_post);
|
||||
cr |= FIELD_PREP(CR_BPW_MASK, transfer->bits_per_word - 1);
|
||||
|
@ -409,10 +409,10 @@ static int hisi_spi_transfer_one(struct spi_controller *master,
|
|||
return 1;
|
||||
}
|
||||
|
||||
static void hisi_spi_handle_err(struct spi_controller *master,
|
||||
static void hisi_spi_handle_err(struct spi_controller *host,
|
||||
struct spi_message *msg)
|
||||
{
|
||||
struct hisi_spi *hs = spi_controller_get_devdata(master);
|
||||
struct hisi_spi *hs = spi_controller_get_devdata(host);
|
||||
|
||||
hisi_spi_disable(hs);
|
||||
|
||||
|
@ -452,7 +452,7 @@ static void hisi_spi_cleanup(struct spi_device *spi)
|
|||
static int hisi_spi_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct spi_controller *master;
|
||||
struct spi_controller *host;
|
||||
struct hisi_spi *hs;
|
||||
int ret, irq;
|
||||
|
||||
|
@ -460,13 +460,13 @@ static int hisi_spi_probe(struct platform_device *pdev)
|
|||
if (irq < 0)
|
||||
return irq;
|
||||
|
||||
master = devm_spi_alloc_master(dev, sizeof(*hs));
|
||||
if (!master)
|
||||
host = devm_spi_alloc_host(dev, sizeof(*hs));
|
||||
if (!host)
|
||||
return -ENOMEM;
|
||||
|
||||
platform_set_drvdata(pdev, master);
|
||||
platform_set_drvdata(pdev, host);
|
||||
|
||||
hs = spi_controller_get_devdata(master);
|
||||
hs = spi_controller_get_devdata(host);
|
||||
hs->dev = dev;
|
||||
hs->irq = irq;
|
||||
|
||||
|
@ -474,9 +474,9 @@ static int hisi_spi_probe(struct platform_device *pdev)
|
|||
if (IS_ERR(hs->regs))
|
||||
return PTR_ERR(hs->regs);
|
||||
|
||||
/* Specify maximum SPI clocking speed (master only) by firmware */
|
||||
/* Specify maximum SPI clocking speed (host only) by firmware */
|
||||
ret = device_property_read_u32(dev, "spi-max-frequency",
|
||||
&master->max_speed_hz);
|
||||
&host->max_speed_hz);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to get max SPI clocking speed, ret=%d\n",
|
||||
ret);
|
||||
|
@ -484,32 +484,32 @@ static int hisi_spi_probe(struct platform_device *pdev)
|
|||
}
|
||||
|
||||
ret = device_property_read_u16(dev, "num-cs",
|
||||
&master->num_chipselect);
|
||||
&host->num_chipselect);
|
||||
if (ret)
|
||||
master->num_chipselect = DEFAULT_NUM_CS;
|
||||
host->num_chipselect = DEFAULT_NUM_CS;
|
||||
|
||||
master->use_gpio_descriptors = true;
|
||||
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
|
||||
master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
|
||||
master->bus_num = pdev->id;
|
||||
master->setup = hisi_spi_setup;
|
||||
master->cleanup = hisi_spi_cleanup;
|
||||
master->transfer_one = hisi_spi_transfer_one;
|
||||
master->handle_err = hisi_spi_handle_err;
|
||||
master->dev.fwnode = dev->fwnode;
|
||||
host->use_gpio_descriptors = true;
|
||||
host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP;
|
||||
host->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
|
||||
host->bus_num = pdev->id;
|
||||
host->setup = hisi_spi_setup;
|
||||
host->cleanup = hisi_spi_cleanup;
|
||||
host->transfer_one = hisi_spi_transfer_one;
|
||||
host->handle_err = hisi_spi_handle_err;
|
||||
host->dev.fwnode = dev->fwnode;
|
||||
|
||||
hisi_spi_hw_init(hs);
|
||||
|
||||
ret = devm_request_irq(dev, hs->irq, hisi_spi_irq, 0, dev_name(dev),
|
||||
master);
|
||||
host);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "failed to get IRQ=%d, ret=%d\n", hs->irq, ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = spi_register_controller(master);
|
||||
ret = spi_register_controller(host);
|
||||
if (ret) {
|
||||
dev_err(dev, "failed to register spi master, ret=%d\n", ret);
|
||||
dev_err(dev, "failed to register spi host, ret=%d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
|
@ -518,18 +518,18 @@ static int hisi_spi_probe(struct platform_device *pdev)
|
|||
|
||||
dev_info(dev, "hw version:0x%x max-freq:%u kHz\n",
|
||||
readl(hs->regs + HISI_SPI_VERSION),
|
||||
master->max_speed_hz / 1000);
|
||||
host->max_speed_hz / 1000);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void hisi_spi_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct spi_controller *master = platform_get_drvdata(pdev);
|
||||
struct hisi_spi *hs = spi_controller_get_devdata(master);
|
||||
struct spi_controller *host = platform_get_drvdata(pdev);
|
||||
struct hisi_spi *hs = spi_controller_get_devdata(host);
|
||||
|
||||
debugfs_remove_recursive(hs->debugfs);
|
||||
spi_unregister_controller(master);
|
||||
spi_unregister_controller(host);
|
||||
}
|
||||
|
||||
static const struct acpi_device_id hisi_spi_acpi_match[] = {
|
||||
|
|
|
@ -287,7 +287,7 @@ static ssize_t npcm_fiu_direct_read(struct spi_mem_dirmap_desc *desc,
|
|||
u64 offs, size_t len, void *buf)
|
||||
{
|
||||
struct npcm_fiu_spi *fiu =
|
||||
spi_controller_get_devdata(desc->mem->spi->master);
|
||||
spi_controller_get_devdata(desc->mem->spi->controller);
|
||||
struct npcm_fiu_chip *chip = &fiu->chip[spi_get_chipselect(desc->mem->spi, 0)];
|
||||
void __iomem *src = (void __iomem *)(chip->flash_region_mapped_ptr +
|
||||
offs);
|
||||
|
@ -314,7 +314,7 @@ static ssize_t npcm_fiu_direct_write(struct spi_mem_dirmap_desc *desc,
|
|||
u64 offs, size_t len, const void *buf)
|
||||
{
|
||||
struct npcm_fiu_spi *fiu =
|
||||
spi_controller_get_devdata(desc->mem->spi->master);
|
||||
spi_controller_get_devdata(desc->mem->spi->controller);
|
||||
struct npcm_fiu_chip *chip = &fiu->chip[spi_get_chipselect(desc->mem->spi, 0)];
|
||||
void __iomem *dst = (void __iomem *)(chip->flash_region_mapped_ptr +
|
||||
offs);
|
||||
|
@ -335,7 +335,7 @@ static int npcm_fiu_uma_read(struct spi_mem *mem,
|
|||
bool is_address_size, u8 *data, u32 data_size)
|
||||
{
|
||||
struct npcm_fiu_spi *fiu =
|
||||
spi_controller_get_devdata(mem->spi->master);
|
||||
spi_controller_get_devdata(mem->spi->controller);
|
||||
u32 uma_cfg = BIT(10);
|
||||
u32 data_reg[4];
|
||||
int ret;
|
||||
|
@ -390,7 +390,7 @@ static int npcm_fiu_uma_write(struct spi_mem *mem,
|
|||
bool is_address_size, u8 *data, u32 data_size)
|
||||
{
|
||||
struct npcm_fiu_spi *fiu =
|
||||
spi_controller_get_devdata(mem->spi->master);
|
||||
spi_controller_get_devdata(mem->spi->controller);
|
||||
u32 uma_cfg = BIT(10);
|
||||
u32 data_reg[4] = {0};
|
||||
u32 val;
|
||||
|
@ -439,7 +439,7 @@ static int npcm_fiu_manualwrite(struct spi_mem *mem,
|
|||
const struct spi_mem_op *op)
|
||||
{
|
||||
struct npcm_fiu_spi *fiu =
|
||||
spi_controller_get_devdata(mem->spi->master);
|
||||
spi_controller_get_devdata(mem->spi->controller);
|
||||
u8 *data = (u8 *)op->data.buf.out;
|
||||
u32 num_data_chunks;
|
||||
u32 remain_data;
|
||||
|
@ -544,7 +544,7 @@ static void npcm_fiux_set_direct_rd(struct npcm_fiu_spi *fiu)
|
|||
static int npcm_fiu_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
|
||||
{
|
||||
struct npcm_fiu_spi *fiu =
|
||||
spi_controller_get_devdata(mem->spi->master);
|
||||
spi_controller_get_devdata(mem->spi->controller);
|
||||
struct npcm_fiu_chip *chip = &fiu->chip[spi_get_chipselect(mem->spi, 0)];
|
||||
int ret = 0;
|
||||
u8 *buf;
|
||||
|
@ -604,7 +604,7 @@ static int npcm_fiu_exec_op(struct spi_mem *mem, const struct spi_mem_op *op)
|
|||
static int npcm_fiu_dirmap_create(struct spi_mem_dirmap_desc *desc)
|
||||
{
|
||||
struct npcm_fiu_spi *fiu =
|
||||
spi_controller_get_devdata(desc->mem->spi->master);
|
||||
spi_controller_get_devdata(desc->mem->spi->controller);
|
||||
struct npcm_fiu_chip *chip = &fiu->chip[spi_get_chipselect(desc->mem->spi, 0)];
|
||||
struct regmap *gcr_regmap;
|
||||
|
||||
|
@ -665,7 +665,7 @@ static int npcm_fiu_dirmap_create(struct spi_mem_dirmap_desc *desc)
|
|||
|
||||
static int npcm_fiu_setup(struct spi_device *spi)
|
||||
{
|
||||
struct spi_controller *ctrl = spi->master;
|
||||
struct spi_controller *ctrl = spi->controller;
|
||||
struct npcm_fiu_spi *fiu = spi_controller_get_devdata(ctrl);
|
||||
struct npcm_fiu_chip *chip;
|
||||
|
||||
|
@ -701,7 +701,7 @@ static int npcm_fiu_probe(struct platform_device *pdev)
|
|||
void __iomem *regbase;
|
||||
int id, ret;
|
||||
|
||||
ctrl = devm_spi_alloc_master(dev, sizeof(*fiu));
|
||||
ctrl = devm_spi_alloc_host(dev, sizeof(*fiu));
|
||||
if (!ctrl)
|
||||
return -ENOMEM;
|
||||
|
||||
|
@ -755,7 +755,7 @@ static int npcm_fiu_probe(struct platform_device *pdev)
|
|||
ctrl->num_chipselect = fiu->info->max_cs;
|
||||
ctrl->dev.of_node = dev->of_node;
|
||||
|
||||
ret = devm_spi_register_master(dev, ctrl);
|
||||
ret = devm_spi_register_controller(dev, ctrl);
|
||||
if (ret)
|
||||
clk_disable_unprepare(fiu->clk);
|
||||
|
||||
|
|
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