drm/i915: Fix watermark calculation in self-refresh mode
For self-refresh mode WM calculation's "line time" should use mode's htotal instead of hdisplay. "surface width" is the hdisplay for display plane and 64 for cursor plane. Signed-off-by: Zhao Yakui <yakui.zhao@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Zhao Yakui
Eric Anholt
Родитель
36e83a187c
Коммит
fa143215b1
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@ -176,7 +176,8 @@ struct drm_i915_display_funcs {
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int (*get_display_clock_speed)(struct drm_device *dev);
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int (*get_fifo_size)(struct drm_device *dev, int plane);
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void (*update_wm)(struct drm_device *dev, int planea_clock,
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int planeb_clock, int sr_hdisplay, int pixel_size);
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int planeb_clock, int sr_hdisplay, int sr_htotal,
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int pixel_size);
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/* clock updates for mode set */
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/* cursor updates */
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/* render clock increase/decrease */
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@ -2809,7 +2809,8 @@ static int i830_get_fifo_size(struct drm_device *dev, int plane)
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}
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static void pineview_update_wm(struct drm_device *dev, int planea_clock,
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int planeb_clock, int sr_hdisplay, int pixel_size)
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int planeb_clock, int sr_hdisplay, int unused,
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int pixel_size)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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u32 reg;
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@ -2874,7 +2875,8 @@ static void pineview_update_wm(struct drm_device *dev, int planea_clock,
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}
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static void g4x_update_wm(struct drm_device *dev, int planea_clock,
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int planeb_clock, int sr_hdisplay, int pixel_size)
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int planeb_clock, int sr_hdisplay, int sr_htotal,
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int pixel_size)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int total_size, cacheline_size;
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@ -2917,11 +2919,11 @@ static void g4x_update_wm(struct drm_device *dev, int planea_clock,
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static const int sr_latency_ns = 12000;
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sr_clock = planea_clock ? planea_clock : planeb_clock;
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line_time_us = ((sr_hdisplay * 1000) / sr_clock);
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line_time_us = ((sr_htotal * 1000) / sr_clock);
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/* Use ns/us then divide to preserve precision */
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sr_entries = (((sr_latency_ns / line_time_us) + 1) *
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pixel_size * sr_hdisplay) / 1000;
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sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
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pixel_size * sr_hdisplay;
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sr_entries = roundup(sr_entries / cacheline_size, 1);
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DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
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I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
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@ -2948,7 +2950,8 @@ static void g4x_update_wm(struct drm_device *dev, int planea_clock,
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}
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static void i965_update_wm(struct drm_device *dev, int planea_clock,
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int planeb_clock, int sr_hdisplay, int pixel_size)
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int planeb_clock, int sr_hdisplay, int sr_htotal,
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int pixel_size)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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unsigned long line_time_us;
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@ -2960,11 +2963,11 @@ static void i965_update_wm(struct drm_device *dev, int planea_clock,
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static const int sr_latency_ns = 12000;
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sr_clock = planea_clock ? planea_clock : planeb_clock;
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line_time_us = ((sr_hdisplay * 1000) / sr_clock);
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line_time_us = ((sr_htotal * 1000) / sr_clock);
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/* Use ns/us then divide to preserve precision */
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sr_entries = (((sr_latency_ns / line_time_us) + 1) *
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pixel_size * sr_hdisplay) / 1000;
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sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
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pixel_size * sr_hdisplay;
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sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
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DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
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srwm = I945_FIFO_SIZE - sr_entries;
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@ -2990,7 +2993,8 @@ static void i965_update_wm(struct drm_device *dev, int planea_clock,
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}
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static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
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int planeb_clock, int sr_hdisplay, int pixel_size)
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int planeb_clock, int sr_hdisplay, int sr_htotal,
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int pixel_size)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t fwater_lo;
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@ -3035,11 +3039,11 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
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static const int sr_latency_ns = 6000;
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sr_clock = planea_clock ? planea_clock : planeb_clock;
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line_time_us = ((sr_hdisplay * 1000) / sr_clock);
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line_time_us = ((sr_htotal * 1000) / sr_clock);
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/* Use ns/us then divide to preserve precision */
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sr_entries = (((sr_latency_ns / line_time_us) + 1) *
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pixel_size * sr_hdisplay) / 1000;
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sr_entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
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pixel_size * sr_hdisplay;
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sr_entries = roundup(sr_entries / cacheline_size, 1);
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DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
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srwm = total_size - sr_entries;
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@ -3078,7 +3082,7 @@ static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
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}
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static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
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int unused2, int pixel_size)
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int unused2, int unused3, int pixel_size)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
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@ -3098,7 +3102,8 @@ static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
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#define ILK_LP0_PLANE_LATENCY 700
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static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
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int planeb_clock, int sr_hdisplay, int pixel_size)
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int planeb_clock, int sr_hdisplay, int sr_htotal,
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int pixel_size)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
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@ -3160,7 +3165,7 @@ static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
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int ilk_sr_latency = I915_READ(MLTR_ILK) & ILK_SRLT_MASK;
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sr_clock = planea_clock ? planea_clock : planeb_clock;
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line_time_us = ((sr_hdisplay * 1000) / sr_clock);
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line_time_us = ((sr_htotal * 1000) / sr_clock);
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/* Use ns/us then divide to preserve precision */
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line_count = ((ilk_sr_latency * 500) / line_time_us + 1000)
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@ -3220,6 +3225,7 @@ static void ironlake_update_wm(struct drm_device *dev, int planea_clock,
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* bytes per pixel
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* where
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* line time = htotal / dotclock
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* surface width = hdisplay for normal plane and 64 for cursor
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* and latency is assumed to be high, as above.
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*
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* The final value programmed to the register should always be rounded up,
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@ -3236,6 +3242,7 @@ static void intel_update_watermarks(struct drm_device *dev)
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int sr_hdisplay = 0;
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unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
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int enabled = 0, pixel_size = 0;
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int sr_htotal = 0;
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if (!dev_priv->display.update_wm)
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return;
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@ -3256,6 +3263,7 @@ static void intel_update_watermarks(struct drm_device *dev)
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}
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sr_hdisplay = crtc->mode.hdisplay;
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sr_clock = crtc->mode.clock;
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sr_htotal = crtc->mode.htotal;
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if (crtc->fb)
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pixel_size = crtc->fb->bits_per_pixel / 8;
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else
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@ -3267,7 +3275,7 @@ static void intel_update_watermarks(struct drm_device *dev)
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return;
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dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
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sr_hdisplay, pixel_size);
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sr_hdisplay, sr_htotal, pixel_size);
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}
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static int intel_crtc_mode_set(struct drm_crtc *crtc,
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