[PATCH] Net: add ath5k wireless driver
add ath5k wireless driver Portions of this driver are covered by one or both of the ISC and 3-clause BSD licenses. Specific license information is cited at the top of each file. Acked-by and Signed-off-by information is collected from individual patches as collected in the wireless-2.6 tree prior to upstream submission. Acked-by: Matthew W. S. Bell <mentor@madwifi.org> Acked-by: Michael Taylor <mike.taylor@apprion.com> Acked-by: Pavel Roskin <proski@gnu.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Bradley M. Kuhn <bkuhn@softwarefreedom.org> Signed-off-by: Bruno Randolf <bruno@thinktube.com> Signed-off-by: Dave Young <hidave.darkstar@gmail.com> Signed-off-by: Francesco Gringoli <francesco.gringoli@ing.unibs.it> Signed-off-by: Jiri Slaby <jirislaby@gmail.com> Signed-off-by: Johannes Berg <johannes@sipsolutions.net> Signed-off-by: Karen Sandler <karen@softwarefreedom.org> Signed-off-by: Krzysztof Halasa <khc@pm.waw.pl> Signed-off-by: Luis R. Rodriguez <mcgrof@gmail.com> Signed-off-by: Matt Norwood <norwood@softwarefreedom.org> Signed-off-by: Nick Kossifidis <mickflemm@gmail.com> Signed-off-by: Richard Fontana <fontana@softwarefreedom.org> Signed-off-by: Stephen Hemminger <shemminger@linux-foundation.org> Signed-off-by: Ulrich Meis <meis@nets.rwth-aachen.de> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
Jiri Slaby
David S. Miller
Родитель
3543f8069d
Коммит
fa1c114fda
11
MAINTAINERS
11
MAINTAINERS
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@ -646,6 +646,17 @@ M: ecashin@coraid.com
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W: http://www.coraid.com/support/linux
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S: Supported
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ATHEROS ATH5K WIRELESS DRIVER
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P: Jiri Slaby
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M: jirislaby@gmail.com
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P: Nick Kossifidis
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M: mickflemm@gmail.com
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P: Luis R. Rodriguez
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M: mcgrof@gmail.com
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L: linux-wireless@vger.kernel.org
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L: ath5k-devel@lists.ath5k.org
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S: Maintained
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ATL1 ETHERNET DRIVER
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P: Jay Cliburn
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M: jcliburn@gmail.com
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@ -648,6 +648,23 @@ config P54_PCI
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If you choose to build a module, it'll be called p54pci.
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config ATH5K
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tristate "Atheros 5xxx wireless cards support"
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depends on PCI && MAC80211 && WLAN_80211 && EXPERIMENTAL
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---help---
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This module adds support for wireless adapters based on
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Atheros 5xxx chipset.
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Currently the following chip versions are supported:
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MAC: AR5211 AR5212
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PHY: RF5111/2111 RF5112/2112 RF5413/2413
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This driver uses the kernel's mac80211 subsystem.
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If you choose to build a module, it'll be called ath5k. Say M if
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unsure.
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source "drivers/net/wireless/iwlwifi/Kconfig"
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source "drivers/net/wireless/hostap/Kconfig"
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source "drivers/net/wireless/bcm43xx/Kconfig"
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@ -59,3 +59,5 @@ obj-$(CONFIG_RT2X00) += rt2x00/
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obj-$(CONFIG_P54_COMMON) += p54common.o
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obj-$(CONFIG_P54_USB) += p54usb.o
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obj-$(CONFIG_P54_PCI) += p54pci.o
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obj-$(CONFIG_ATH5K) += ath5k/
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@ -0,0 +1,2 @@
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ath5k-objs = base.o hw.o regdom.o initvals.o phy.o debug.o
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obj-$(CONFIG_ATH5K) += ath5k.o
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Загрузить разницу
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@ -0,0 +1,178 @@
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/*-
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* Copyright (c) 2002-2007 Sam Leffler, Errno Consulting
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
|
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* notice, this list of conditions and the following disclaimer,
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* without modification.
|
||||
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
|
||||
* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
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||||
* redistribution must be conditioned upon including a substantially
|
||||
* similar Disclaimer requirement for further binary redistribution.
|
||||
* 3. Neither the names of the above-listed copyright holders nor the names
|
||||
* of any contributors may be used to endorse or promote products derived
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||||
* from this software without specific prior written permission.
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*
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* Alternatively, this software may be distributed under the terms of the
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* GNU General Public License ("GPL") version 2 as published by the Free
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* Software Foundation.
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*
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* NO WARRANTY
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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||||
* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
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* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
|
||||
* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
|
||||
* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGES.
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*
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*/
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/*
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* Defintions for the Atheros Wireless LAN controller driver.
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*/
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#ifndef _DEV_ATH_ATHVAR_H
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#define _DEV_ATH_ATHVAR_H
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#include <linux/interrupt.h>
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#include <linux/list.h>
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#include <linux/wireless.h>
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#include <linux/if_ether.h>
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#include "ath5k.h"
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#include "debug.h"
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#define ATH_RXBUF 40 /* number of RX buffers */
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#define ATH_TXBUF 200 /* number of TX buffers */
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#define ATH_BCBUF 1 /* number of beacon buffers */
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struct ath5k_buf {
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struct list_head list;
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unsigned int flags; /* tx descriptor flags */
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struct ath5k_desc *desc; /* virtual addr of desc */
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dma_addr_t daddr; /* physical addr of desc */
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struct sk_buff *skb; /* skbuff for buf */
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dma_addr_t skbaddr;/* physical addr of skb data */
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struct ieee80211_tx_control ctl;
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};
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/*
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* Data transmit queue state. One of these exists for each
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* hardware transmit queue. Packets sent to us from above
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* are assigned to queues based on their priority. Not all
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* devices support a complete set of hardware transmit queues.
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* For those devices the array sc_ac2q will map multiple
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* priorities to fewer hardware queues (typically all to one
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* hardware queue).
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*/
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struct ath5k_txq {
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unsigned int qnum; /* hardware q number */
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u32 *link; /* link ptr in last TX desc */
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struct list_head q; /* transmit queue */
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spinlock_t lock; /* lock on q and link */
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bool setup;
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};
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#if CHAN_DEBUG
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#define ATH_CHAN_MAX (26+26+26+200+200)
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#else
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#define ATH_CHAN_MAX (14+14+14+252+20) /* XXX what's the max? */
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#endif
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/* Software Carrier, keeps track of the driver state
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* associated with an instance of a device */
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struct ath5k_softc {
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struct pci_dev *pdev; /* for dma mapping */
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void __iomem *iobase; /* address of the device */
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struct mutex lock; /* dev-level lock */
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struct ieee80211_tx_queue_stats tx_stats;
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struct ieee80211_low_level_stats ll_stats;
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struct ieee80211_hw *hw; /* IEEE 802.11 common */
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struct ieee80211_hw_mode modes[NUM_DRIVER_MODES];
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struct ieee80211_channel channels[ATH_CHAN_MAX];
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struct ieee80211_rate rates[AR5K_MAX_RATES * NUM_DRIVER_MODES];
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enum ieee80211_if_types opmode;
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struct ath5k_hw *ah; /* Atheros HW */
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#if ATH5K_DEBUG
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struct ath5k_dbg_info debug; /* debug info */
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#endif
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struct ath5k_buf *bufptr; /* allocated buffer ptr */
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struct ath5k_desc *desc; /* TX/RX descriptors */
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dma_addr_t desc_daddr; /* DMA (physical) address */
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size_t desc_len; /* size of TX/RX descriptors */
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u16 cachelsz; /* cache line size */
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DECLARE_BITMAP(status, 6);
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#define ATH_STAT_INVALID 0 /* disable hardware accesses */
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#define ATH_STAT_MRRETRY 1 /* multi-rate retry support */
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#define ATH_STAT_PROMISC 2
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#define ATH_STAT_LEDBLINKING 3 /* LED blink operation active */
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#define ATH_STAT_LEDENDBLINK 4 /* finish LED blink operation */
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#define ATH_STAT_LEDSOFT 5 /* enable LED gpio status */
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unsigned int filter_flags; /* HW flags, AR5K_RX_FILTER_* */
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unsigned int curmode; /* current phy mode */
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struct ieee80211_channel *curchan; /* current h/w channel */
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int iface_id; /* add/remove_interface id */
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struct {
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u8 rxflags; /* radiotap rx flags */
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u8 txflags; /* radiotap tx flags */
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u16 ledon; /* softled on time */
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u16 ledoff; /* softled off time */
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} hwmap[32]; /* h/w rate ix mappings */
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enum ath5k_int imask; /* interrupt mask copy */
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DECLARE_BITMAP(keymap, AR5K_KEYCACHE_SIZE); /* key use bit map */
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u8 bssidmask[ETH_ALEN];
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unsigned int led_pin, /* GPIO pin for driving LED */
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led_on, /* pin setting for LED on */
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led_off; /* off time for current blink */
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struct timer_list led_tim; /* led off timer */
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u8 led_rxrate; /* current rx rate for LED */
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u8 led_txrate; /* current tx rate for LED */
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struct tasklet_struct restq; /* reset tasklet */
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unsigned int rxbufsize; /* rx size based on mtu */
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struct list_head rxbuf; /* receive buffer */
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spinlock_t rxbuflock;
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u32 *rxlink; /* link ptr in last RX desc */
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struct tasklet_struct rxtq; /* rx intr tasklet */
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struct list_head txbuf; /* transmit buffer */
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spinlock_t txbuflock;
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unsigned int txbuf_len; /* buf count in txbuf list */
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struct ath5k_txq txqs[2]; /* beacon and tx */
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struct ath5k_txq *txq; /* beacon and tx*/
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struct tasklet_struct txtq; /* tx intr tasklet */
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struct ath5k_buf *bbuf; /* beacon buffer */
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unsigned int bhalq, /* SW q for outgoing beacons */
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bmisscount, /* missed beacon transmits */
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bintval, /* beacon interval */
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bsent;
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struct timer_list calib_tim; /* calibration timer */
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};
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#define ath5k_hw_hasbssidmask(_ah) \
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(ath5k_hw_get_capability(_ah, AR5K_CAP_BSSIDMASK, 0, NULL) == 0)
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#define ath5k_hw_hasveol(_ah) \
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(ath5k_hw_get_capability(_ah, AR5K_CAP_VEOL, 0, NULL) == 0)
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#endif
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@ -0,0 +1,469 @@
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/*
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* Copyright (c) 2007 Bruno Randolf <bruno@thinktube.com>
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*
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* This file is free software: you may copy, redistribute and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation, either version 2 of the License, or (at your
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* option) any later version.
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*
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* This file is distributed in the hope that it will be useful, but
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* WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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*
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* This file incorporates work covered by the following copyright and
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* permission notice:
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*
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* Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
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* Copyright (c) 2004-2005 Atheros Communications, Inc.
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* Copyright (c) 2006 Devicescape Software, Inc.
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* Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
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* Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
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*
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
|
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* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer,
|
||||
* without modification.
|
||||
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
|
||||
* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
|
||||
* redistribution must be conditioned upon including a substantially
|
||||
* similar Disclaimer requirement for further binary redistribution.
|
||||
* 3. Neither the names of the above-listed copyright holders nor the names
|
||||
* of any contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* Alternatively, this software may be distributed under the terms of the
|
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* GNU General Public License ("GPL") version 2 as published by the Free
|
||||
* Software Foundation.
|
||||
*
|
||||
* NO WARRANTY
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
|
||||
* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
|
||||
* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES.
|
||||
*/
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#include "debug.h"
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#include "base.h"
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static unsigned int ath5k_debug;
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module_param_named(debug, ath5k_debug, uint, 0);
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#if ATH5K_DEBUG
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#include <linux/seq_file.h>
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#include "reg.h"
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static struct dentry *ath5k_global_debugfs;
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static int ath5k_debugfs_open(struct inode *inode, struct file *file)
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{
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file->private_data = inode->i_private;
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return 0;
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}
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/* debugfs: registers */
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struct reg {
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char *name;
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int addr;
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};
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#define REG_STRUCT_INIT(r) { #r, r }
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/* just a few random registers, might want to add more */
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static struct reg regs[] = {
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REG_STRUCT_INIT(AR5K_CR),
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REG_STRUCT_INIT(AR5K_RXDP),
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REG_STRUCT_INIT(AR5K_CFG),
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REG_STRUCT_INIT(AR5K_IER),
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REG_STRUCT_INIT(AR5K_BCR),
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REG_STRUCT_INIT(AR5K_RTSD0),
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REG_STRUCT_INIT(AR5K_RTSD1),
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REG_STRUCT_INIT(AR5K_TXCFG),
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REG_STRUCT_INIT(AR5K_RXCFG),
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REG_STRUCT_INIT(AR5K_RXJLA),
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REG_STRUCT_INIT(AR5K_MIBC),
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REG_STRUCT_INIT(AR5K_TOPS),
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REG_STRUCT_INIT(AR5K_RXNOFRM),
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REG_STRUCT_INIT(AR5K_TXNOFRM),
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REG_STRUCT_INIT(AR5K_RPGTO),
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REG_STRUCT_INIT(AR5K_RFCNT),
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REG_STRUCT_INIT(AR5K_MISC),
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REG_STRUCT_INIT(AR5K_QCUDCU_CLKGT),
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REG_STRUCT_INIT(AR5K_ISR),
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REG_STRUCT_INIT(AR5K_PISR),
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REG_STRUCT_INIT(AR5K_SISR0),
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REG_STRUCT_INIT(AR5K_SISR1),
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REG_STRUCT_INIT(AR5K_SISR2),
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REG_STRUCT_INIT(AR5K_SISR3),
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REG_STRUCT_INIT(AR5K_SISR4),
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REG_STRUCT_INIT(AR5K_IMR),
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REG_STRUCT_INIT(AR5K_PIMR),
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REG_STRUCT_INIT(AR5K_SIMR0),
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REG_STRUCT_INIT(AR5K_SIMR1),
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REG_STRUCT_INIT(AR5K_SIMR2),
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REG_STRUCT_INIT(AR5K_SIMR3),
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REG_STRUCT_INIT(AR5K_SIMR4),
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REG_STRUCT_INIT(AR5K_DCM_ADDR),
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REG_STRUCT_INIT(AR5K_DCCFG),
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REG_STRUCT_INIT(AR5K_CCFG),
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REG_STRUCT_INIT(AR5K_CPC0),
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REG_STRUCT_INIT(AR5K_CPC1),
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REG_STRUCT_INIT(AR5K_CPC2),
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REG_STRUCT_INIT(AR5K_CPC3),
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REG_STRUCT_INIT(AR5K_CPCORN),
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REG_STRUCT_INIT(AR5K_RESET_CTL),
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REG_STRUCT_INIT(AR5K_SLEEP_CTL),
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REG_STRUCT_INIT(AR5K_INTPEND),
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REG_STRUCT_INIT(AR5K_SFR),
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REG_STRUCT_INIT(AR5K_PCICFG),
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REG_STRUCT_INIT(AR5K_GPIOCR),
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REG_STRUCT_INIT(AR5K_GPIODO),
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REG_STRUCT_INIT(AR5K_SREV),
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||||
};
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static void *reg_start(struct seq_file *seq, loff_t *pos)
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{
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return *pos < ARRAY_SIZE(regs) ? ®s[*pos] : NULL;
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}
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static void reg_stop(struct seq_file *seq, void *p)
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{
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/* nothing to do */
|
||||
}
|
||||
|
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static void *reg_next(struct seq_file *seq, void *p, loff_t *pos)
|
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{
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++*pos;
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||||
return *pos < ARRAY_SIZE(regs) ? ®s[*pos] : NULL;
|
||||
}
|
||||
|
||||
static int reg_show(struct seq_file *seq, void *p)
|
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{
|
||||
struct ath5k_softc *sc = seq->private;
|
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struct reg *r = p;
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seq_printf(seq, "%-25s0x%08x\n", r->name,
|
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ath5k_hw_reg_read(sc->ah, r->addr));
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return 0;
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||||
}
|
||||
|
||||
static struct seq_operations register_seq_ops = {
|
||||
.start = reg_start,
|
||||
.next = reg_next,
|
||||
.stop = reg_stop,
|
||||
.show = reg_show
|
||||
};
|
||||
|
||||
static int open_file_registers(struct inode *inode, struct file *file)
|
||||
{
|
||||
struct seq_file *s;
|
||||
int res;
|
||||
res = seq_open(file, ®ister_seq_ops);
|
||||
if (res == 0) {
|
||||
s = file->private_data;
|
||||
s->private = inode->i_private;
|
||||
}
|
||||
return res;
|
||||
}
|
||||
|
||||
static const struct file_operations fops_registers = {
|
||||
.open = open_file_registers,
|
||||
.read = seq_read,
|
||||
.llseek = seq_lseek,
|
||||
.release = seq_release,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
|
||||
/* debugfs: TSF */
|
||||
|
||||
static ssize_t read_file_tsf(struct file *file, char __user *user_buf,
|
||||
size_t count, loff_t *ppos)
|
||||
{
|
||||
struct ath5k_softc *sc = file->private_data;
|
||||
char buf[100];
|
||||
snprintf(buf, 100, "0x%016llx\n", ath5k_hw_get_tsf64(sc->ah));
|
||||
return simple_read_from_buffer(user_buf, count, ppos, buf, 19);
|
||||
}
|
||||
|
||||
static ssize_t write_file_tsf(struct file *file,
|
||||
const char __user *userbuf,
|
||||
size_t count, loff_t *ppos)
|
||||
{
|
||||
struct ath5k_softc *sc = file->private_data;
|
||||
if (strncmp(userbuf, "reset", 5) == 0) {
|
||||
ath5k_hw_reset_tsf(sc->ah);
|
||||
printk(KERN_INFO "debugfs reset TSF\n");
|
||||
}
|
||||
return count;
|
||||
}
|
||||
|
||||
static const struct file_operations fops_tsf = {
|
||||
.read = read_file_tsf,
|
||||
.write = write_file_tsf,
|
||||
.open = ath5k_debugfs_open,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
|
||||
/* debugfs: beacons */
|
||||
|
||||
static ssize_t read_file_beacon(struct file *file, char __user *user_buf,
|
||||
size_t count, loff_t *ppos)
|
||||
{
|
||||
struct ath5k_softc *sc = file->private_data;
|
||||
struct ath5k_hw *ah = sc->ah;
|
||||
char buf[1000];
|
||||
int len = 0;
|
||||
unsigned int v;
|
||||
u64 tsf;
|
||||
|
||||
v = ath5k_hw_reg_read(sc->ah, AR5K_BEACON);
|
||||
len += snprintf(buf+len, sizeof(buf)-len,
|
||||
"%-24s0x%08x\tintval: %d\tTIM: 0x%x\n",
|
||||
"AR5K_BEACON", v, v & AR5K_BEACON_PERIOD,
|
||||
(v & AR5K_BEACON_TIM) >> AR5K_BEACON_TIM_S);
|
||||
|
||||
len += snprintf(buf+len, sizeof(buf)-len, "%-24s0x%08x\n",
|
||||
"AR5K_LAST_TSTP", ath5k_hw_reg_read(sc->ah, AR5K_LAST_TSTP));
|
||||
|
||||
len += snprintf(buf+len, sizeof(buf)-len, "%-24s0x%08x\n\n",
|
||||
"AR5K_BEACON_CNT", ath5k_hw_reg_read(sc->ah, AR5K_BEACON_CNT));
|
||||
|
||||
v = ath5k_hw_reg_read(sc->ah, AR5K_TIMER0);
|
||||
len += snprintf(buf+len, sizeof(buf)-len, "%-24s0x%08x\tTU: %08x\n",
|
||||
"AR5K_TIMER0 (TBTT)", v, v);
|
||||
|
||||
v = ath5k_hw_reg_read(sc->ah, AR5K_TIMER1);
|
||||
len += snprintf(buf+len, sizeof(buf)-len, "%-24s0x%08x\tTU: %08x\n",
|
||||
"AR5K_TIMER1 (DMA)", v, v >> 3);
|
||||
|
||||
v = ath5k_hw_reg_read(sc->ah, AR5K_TIMER2);
|
||||
len += snprintf(buf+len, sizeof(buf)-len, "%-24s0x%08x\tTU: %08x\n",
|
||||
"AR5K_TIMER2 (SWBA)", v, v >> 3);
|
||||
|
||||
v = ath5k_hw_reg_read(sc->ah, AR5K_TIMER3);
|
||||
len += snprintf(buf+len, sizeof(buf)-len, "%-24s0x%08x\tTU: %08x\n",
|
||||
"AR5K_TIMER3 (ATIM)", v, v);
|
||||
|
||||
tsf = ath5k_hw_get_tsf64(sc->ah);
|
||||
len += snprintf(buf+len, sizeof(buf)-len,
|
||||
"TSF\t\t0x%016llx\tTU: %08x\n", tsf, TSF_TO_TU(tsf));
|
||||
|
||||
return simple_read_from_buffer(user_buf, count, ppos, buf, len);
|
||||
}
|
||||
|
||||
static ssize_t write_file_beacon(struct file *file,
|
||||
const char __user *userbuf,
|
||||
size_t count, loff_t *ppos)
|
||||
{
|
||||
struct ath5k_softc *sc = file->private_data;
|
||||
struct ath5k_hw *ah = sc->ah;
|
||||
|
||||
if (strncmp(userbuf, "disable", 7) == 0) {
|
||||
AR5K_REG_DISABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE);
|
||||
printk(KERN_INFO "debugfs disable beacons\n");
|
||||
} else if (strncmp(userbuf, "enable", 6) == 0) {
|
||||
AR5K_REG_ENABLE_BITS(ah, AR5K_BEACON, AR5K_BEACON_ENABLE);
|
||||
printk(KERN_INFO "debugfs enable beacons\n");
|
||||
}
|
||||
return count;
|
||||
}
|
||||
|
||||
static const struct file_operations fops_beacon = {
|
||||
.read = read_file_beacon,
|
||||
.write = write_file_beacon,
|
||||
.open = ath5k_debugfs_open,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
|
||||
/* debugfs: reset */
|
||||
|
||||
static ssize_t write_file_reset(struct file *file,
|
||||
const char __user *userbuf,
|
||||
size_t count, loff_t *ppos)
|
||||
{
|
||||
struct ath5k_softc *sc = file->private_data;
|
||||
tasklet_schedule(&sc->restq);
|
||||
return count;
|
||||
}
|
||||
|
||||
static const struct file_operations fops_reset = {
|
||||
.write = write_file_reset,
|
||||
.open = ath5k_debugfs_open,
|
||||
.owner = THIS_MODULE,
|
||||
};
|
||||
|
||||
|
||||
/* init */
|
||||
|
||||
void
|
||||
ath5k_debug_init(void)
|
||||
{
|
||||
ath5k_global_debugfs = debugfs_create_dir("ath5k", NULL);
|
||||
}
|
||||
|
||||
void
|
||||
ath5k_debug_init_device(struct ath5k_softc *sc)
|
||||
{
|
||||
sc->debug.level = ath5k_debug;
|
||||
sc->debug.debugfs_phydir = debugfs_create_dir(wiphy_name(sc->hw->wiphy),
|
||||
ath5k_global_debugfs);
|
||||
sc->debug.debugfs_debug = debugfs_create_u32("debug",
|
||||
0666, sc->debug.debugfs_phydir, &sc->debug.level);
|
||||
|
||||
sc->debug.debugfs_registers = debugfs_create_file("registers", 0444,
|
||||
sc->debug.debugfs_phydir,
|
||||
sc, &fops_registers);
|
||||
|
||||
sc->debug.debugfs_tsf = debugfs_create_file("tsf", 0666,
|
||||
sc->debug.debugfs_phydir,
|
||||
sc, &fops_tsf);
|
||||
|
||||
sc->debug.debugfs_beacon = debugfs_create_file("beacon", 0666,
|
||||
sc->debug.debugfs_phydir,
|
||||
sc, &fops_beacon);
|
||||
|
||||
sc->debug.debugfs_reset = debugfs_create_file("reset", 0222,
|
||||
sc->debug.debugfs_phydir,
|
||||
sc, &fops_reset);
|
||||
}
|
||||
|
||||
void
|
||||
ath5k_debug_finish(void)
|
||||
{
|
||||
debugfs_remove(ath5k_global_debugfs);
|
||||
}
|
||||
|
||||
void
|
||||
ath5k_debug_finish_device(struct ath5k_softc *sc)
|
||||
{
|
||||
debugfs_remove(sc->debug.debugfs_debug);
|
||||
debugfs_remove(sc->debug.debugfs_registers);
|
||||
debugfs_remove(sc->debug.debugfs_tsf);
|
||||
debugfs_remove(sc->debug.debugfs_beacon);
|
||||
debugfs_remove(sc->debug.debugfs_reset);
|
||||
debugfs_remove(sc->debug.debugfs_phydir);
|
||||
}
|
||||
|
||||
|
||||
/* functions used in other places */
|
||||
|
||||
void
|
||||
ath5k_debug_dump_modes(struct ath5k_softc *sc, struct ieee80211_hw_mode *modes)
|
||||
{
|
||||
unsigned int m, i;
|
||||
|
||||
if (likely(!(sc->debug.level & ATH5K_DEBUG_DUMPMODES)))
|
||||
return;
|
||||
|
||||
for (m = 0; m < NUM_DRIVER_MODES; m++) {
|
||||
printk(KERN_DEBUG "Mode %u: channels %d, rates %d\n", m,
|
||||
modes[m].num_channels, modes[m].num_rates);
|
||||
printk(KERN_DEBUG " channels:\n");
|
||||
for (i = 0; i < modes[m].num_channels; i++)
|
||||
printk(KERN_DEBUG " %3d %d %.4x %.4x\n",
|
||||
modes[m].channels[i].chan,
|
||||
modes[m].channels[i].freq,
|
||||
modes[m].channels[i].val,
|
||||
modes[m].channels[i].flag);
|
||||
printk(KERN_DEBUG " rates:\n");
|
||||
for (i = 0; i < modes[m].num_rates; i++)
|
||||
printk(KERN_DEBUG " %4d %.4x %.4x %.4x\n",
|
||||
modes[m].rates[i].rate,
|
||||
modes[m].rates[i].val,
|
||||
modes[m].rates[i].flags,
|
||||
modes[m].rates[i].val2);
|
||||
}
|
||||
}
|
||||
|
||||
static inline void
|
||||
ath5k_debug_printrxbuf(struct ath5k_buf *bf, int done)
|
||||
{
|
||||
struct ath5k_desc *ds = bf->desc;
|
||||
|
||||
printk(KERN_DEBUG "R (%p %llx) %08x %08x %08x %08x %08x %08x %c\n",
|
||||
ds, (unsigned long long)bf->daddr,
|
||||
ds->ds_link, ds->ds_data, ds->ds_ctl0, ds->ds_ctl1,
|
||||
ds->ds_hw[0], ds->ds_hw[1],
|
||||
!done ? ' ' : (ds->ds_rxstat.rs_status == 0) ? '*' : '!');
|
||||
}
|
||||
|
||||
void
|
||||
ath5k_debug_printrxbuffs(struct ath5k_softc *sc, struct ath5k_hw *ah)
|
||||
{
|
||||
struct ath5k_desc *ds;
|
||||
struct ath5k_buf *bf;
|
||||
int status;
|
||||
|
||||
if (likely(!(sc->debug.level &
|
||||
(ATH5K_DEBUG_RESET | ATH5K_DEBUG_FATAL))))
|
||||
return;
|
||||
|
||||
printk(KERN_DEBUG "rx queue %x, link %p\n",
|
||||
ath5k_hw_get_rx_buf(ah), sc->rxlink);
|
||||
|
||||
spin_lock_bh(&sc->rxbuflock);
|
||||
list_for_each_entry(bf, &sc->rxbuf, list) {
|
||||
ds = bf->desc;
|
||||
status = ah->ah_proc_rx_desc(ah, ds);
|
||||
if (!status || (sc->debug.level & ATH5K_DEBUG_FATAL))
|
||||
ath5k_debug_printrxbuf(bf, status == 0);
|
||||
}
|
||||
spin_unlock_bh(&sc->rxbuflock);
|
||||
}
|
||||
|
||||
void
|
||||
ath5k_debug_dump_skb(struct ath5k_softc *sc,
|
||||
struct sk_buff *skb, const char *prefix, int tx)
|
||||
{
|
||||
char buf[16];
|
||||
|
||||
if (likely(!((tx && (sc->debug.level & ATH5K_DEBUG_DUMP_TX)) ||
|
||||
(!tx && (sc->debug.level & ATH5K_DEBUG_DUMP_RX)))))
|
||||
return;
|
||||
|
||||
snprintf(buf, sizeof(buf), "%s %s", wiphy_name(sc->hw->wiphy), prefix);
|
||||
|
||||
print_hex_dump_bytes(buf, DUMP_PREFIX_NONE, skb->data,
|
||||
min(200U, skb->len));
|
||||
|
||||
printk(KERN_DEBUG "\n");
|
||||
}
|
||||
|
||||
void
|
||||
ath5k_debug_printtxbuf(struct ath5k_softc *sc,
|
||||
struct ath5k_buf *bf, int done)
|
||||
{
|
||||
struct ath5k_desc *ds = bf->desc;
|
||||
|
||||
if (likely(!(sc->debug.level & ATH5K_DEBUG_RESET)))
|
||||
return;
|
||||
|
||||
printk(KERN_DEBUG "T (%p %llx) %08x %08x %08x %08x %08x %08x %08x "
|
||||
"%08x %c\n", ds, (unsigned long long)bf->daddr, ds->ds_link,
|
||||
ds->ds_data, ds->ds_ctl0, ds->ds_ctl1,
|
||||
ds->ds_hw[0], ds->ds_hw[1], ds->ds_hw[2], ds->ds_hw[3],
|
||||
!done ? ' ' : (ds->ds_txstat.ts_status == 0) ? '*' : '!');
|
||||
}
|
||||
|
||||
#endif /* if ATH5K_DEBUG */
|
||||
|
|
@ -0,0 +1,216 @@
|
|||
/*
|
||||
* Copyright (c) 2007 Bruno Randolf <bruno@thinktube.com>
|
||||
*
|
||||
* This file is free software: you may copy, redistribute and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation, either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* This file is distributed in the hope that it will be useful, but
|
||||
* WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
|
||||
* General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
*
|
||||
*
|
||||
* This file incorporates work covered by the following copyright and
|
||||
* permission notice:
|
||||
*
|
||||
* Copyright (c) 2002-2005 Sam Leffler, Errno Consulting
|
||||
* Copyright (c) 2004-2005 Atheros Communications, Inc.
|
||||
* Copyright (c) 2006 Devicescape Software, Inc.
|
||||
* Copyright (c) 2007 Jiri Slaby <jirislaby@gmail.com>
|
||||
* Copyright (c) 2007 Luis R. Rodriguez <mcgrof@winlab.rutgers.edu>
|
||||
*
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer,
|
||||
* without modification.
|
||||
* 2. Redistributions in binary form must reproduce at minimum a disclaimer
|
||||
* similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
|
||||
* redistribution must be conditioned upon including a substantially
|
||||
* similar Disclaimer requirement for further binary redistribution.
|
||||
* 3. Neither the names of the above-listed copyright holders nor the names
|
||||
* of any contributors may be used to endorse or promote products derived
|
||||
* from this software without specific prior written permission.
|
||||
*
|
||||
* Alternatively, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") version 2 as published by the Free
|
||||
* Software Foundation.
|
||||
*
|
||||
* NO WARRANTY
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
|
||||
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
|
||||
* LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
|
||||
* AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
|
||||
* THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
|
||||
* OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
|
||||
* IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGES.
|
||||
*/
|
||||
|
||||
#ifndef _ATH5K_DEBUG_H
|
||||
#define _ATH5K_DEBUG_H
|
||||
|
||||
/* set this to 1 for debugging output */
|
||||
#ifndef ATH5K_DEBUG
|
||||
#define ATH5K_DEBUG 0
|
||||
#endif
|
||||
|
||||
struct ath5k_softc;
|
||||
struct ath5k_hw;
|
||||
struct ieee80211_hw_mode;
|
||||
struct sk_buff;
|
||||
struct ath5k_buf;
|
||||
|
||||
struct ath5k_dbg_info {
|
||||
unsigned int level; /* debug level */
|
||||
/* debugfs entries */
|
||||
struct dentry *debugfs_phydir;
|
||||
struct dentry *debugfs_debug;
|
||||
struct dentry *debugfs_registers;
|
||||
struct dentry *debugfs_tsf;
|
||||
struct dentry *debugfs_beacon;
|
||||
struct dentry *debugfs_reset;
|
||||
};
|
||||
|
||||
/**
|
||||
* enum ath5k_debug_level - ath5k debug level
|
||||
*
|
||||
* @ATH5K_DEBUG_RESET: reset processing
|
||||
* @ATH5K_DEBUG_INTR: interrupt handling
|
||||
* @ATH5K_DEBUG_MODE: mode init/setup
|
||||
* @ATH5K_DEBUG_XMIT: basic xmit operation
|
||||
* @ATH5K_DEBUG_BEACON: beacon handling
|
||||
* @ATH5K_DEBUG_BEACON_PROC: beacon ISR proc
|
||||
* @ATH5K_DEBUG_CALIBRATE: periodic calibration
|
||||
* @ATH5K_DEBUG_TXPOWER: transmit power setting
|
||||
* @ATH5K_DEBUG_LED: led management
|
||||
* @ATH5K_DEBUG_DUMP_RX: print received skb content
|
||||
* @ATH5K_DEBUG_DUMP_TX: print transmit skb content
|
||||
* @ATH5K_DEBUG_DUMPMODES: dump modes
|
||||
* @ATH5K_DEBUG_TRACE: trace function calls
|
||||
* @ATH5K_DEBUG_FATAL: fatal errors
|
||||
* @ATH5K_DEBUG_ANY: show at any debug level
|
||||
*
|
||||
* The debug level is used to control the amount and type of debugging output
|
||||
* we want to see. The debug level is given in calls to ATH5K_DBG to specify
|
||||
* where the message should appear, and the user can control the debugging
|
||||
* messages he wants to see, either by the module parameter 'debug' on module
|
||||
* load, or dynamically by using debugfs 'ath5k/phyX/debug'. these levels can
|
||||
* be combined together by bitwise OR.
|
||||
*/
|
||||
enum ath5k_debug_level {
|
||||
ATH5K_DEBUG_RESET = 0x00000001,
|
||||
ATH5K_DEBUG_INTR = 0x00000002,
|
||||
ATH5K_DEBUG_MODE = 0x00000004,
|
||||
ATH5K_DEBUG_XMIT = 0x00000008,
|
||||
ATH5K_DEBUG_BEACON = 0x00000010,
|
||||
ATH5K_DEBUG_BEACON_PROC = 0x00000020,
|
||||
ATH5K_DEBUG_CALIBRATE = 0x00000100,
|
||||
ATH5K_DEBUG_TXPOWER = 0x00000200,
|
||||
ATH5K_DEBUG_LED = 0x00000400,
|
||||
ATH5K_DEBUG_DUMP_RX = 0x00001000,
|
||||
ATH5K_DEBUG_DUMP_TX = 0x00002000,
|
||||
ATH5K_DEBUG_DUMPMODES = 0x00004000,
|
||||
ATH5K_DEBUG_TRACE = 0x00010000,
|
||||
ATH5K_DEBUG_FATAL = 0x80000000,
|
||||
ATH5K_DEBUG_ANY = 0xffffffff
|
||||
};
|
||||
|
||||
#if ATH5K_DEBUG
|
||||
|
||||
#define ATH5K_TRACE(_sc) do { \
|
||||
if (unlikely((_sc)->debug.level & ATH5K_DEBUG_TRACE)) \
|
||||
printk(KERN_DEBUG "ath5k trace %s:%d\n", __func__, __LINE__); \
|
||||
} while (0)
|
||||
|
||||
#define ATH5K_DBG(_sc, _m, _fmt, ...) do { \
|
||||
if (unlikely((_sc)->debug.level & (_m) && net_ratelimit())) \
|
||||
ATH5K_PRINTK(_sc, KERN_DEBUG, "(%s:%d): " _fmt, \
|
||||
__func__, __LINE__, ##__VA_ARGS__); \
|
||||
} while (0)
|
||||
|
||||
#define ATH5K_DBG_UNLIMIT(_sc, _m, _fmt, ...) do { \
|
||||
if (unlikely((_sc)->debug.level & (_m))) \
|
||||
ATH5K_PRINTK(_sc, KERN_DEBUG, "(%s:%d): " _fmt, \
|
||||
__func__, __LINE__, ##__VA_ARGS__); \
|
||||
} while (0)
|
||||
|
||||
void
|
||||
ath5k_debug_init(void);
|
||||
|
||||
void
|
||||
ath5k_debug_init_device(struct ath5k_softc *sc);
|
||||
|
||||
void
|
||||
ath5k_debug_finish(void);
|
||||
|
||||
void
|
||||
ath5k_debug_finish_device(struct ath5k_softc *sc);
|
||||
|
||||
void
|
||||
ath5k_debug_printrxbuffs(struct ath5k_softc *sc, struct ath5k_hw *ah);
|
||||
|
||||
void
|
||||
ath5k_debug_dump_modes(struct ath5k_softc *sc,
|
||||
struct ieee80211_hw_mode *modes);
|
||||
|
||||
void
|
||||
ath5k_debug_dump_skb(struct ath5k_softc *sc,
|
||||
struct sk_buff *skb, const char *prefix, int tx);
|
||||
|
||||
void
|
||||
ath5k_debug_printtxbuf(struct ath5k_softc *sc,
|
||||
struct ath5k_buf *bf, int done);
|
||||
|
||||
#else /* no debugging */
|
||||
|
||||
#define ATH5K_TRACE(_sc) /* empty */
|
||||
|
||||
static inline void __attribute__ ((format (printf, 3, 4)))
|
||||
ATH5K_DBG(struct ath5k_softc *sc, unsigned int m, const char *fmt, ...) {}
|
||||
|
||||
static inline void __attribute__ ((format (printf, 3, 4)))
|
||||
ATH5K_DBG_UNLIMIT(struct ath5k_softc *sc, unsigned int m, const char *fmt, ...)
|
||||
{}
|
||||
|
||||
static inline void
|
||||
ath5k_debug_init(void) {}
|
||||
|
||||
static inline void
|
||||
ath5k_debug_init_device(struct ath5k_softc *sc) {}
|
||||
|
||||
static inline void
|
||||
ath5k_debug_finish(void) {}
|
||||
|
||||
static inline void
|
||||
ath5k_debug_finish_device(struct ath5k_softc *sc) {}
|
||||
|
||||
static inline void
|
||||
ath5k_debug_printrxbuffs(struct ath5k_softc *sc, struct ath5k_hw *ah) {}
|
||||
|
||||
static inline void
|
||||
ath5k_debug_dump_modes(struct ath5k_softc *sc,
|
||||
struct ieee80211_hw_mode *modes) {}
|
||||
|
||||
static inline void
|
||||
ath5k_debug_dump_skb(struct ath5k_softc *sc,
|
||||
struct sk_buff *skb, const char *prefix, int tx) {}
|
||||
|
||||
static inline void
|
||||
ath5k_debug_printtxbuf(struct ath5k_softc *sc,
|
||||
struct ath5k_buf *bf, int done) {}
|
||||
|
||||
#endif /* if ATH5K_DEBUG */
|
||||
|
||||
#endif /* ifndef _ATH5K_DEBUG_H */
|
||||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -0,0 +1,588 @@
|
|||
/*
|
||||
* Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
|
||||
* Copyright (c) 2006-2007 Nick Kossifidis <mickflemm@gmail.com>
|
||||
* Copyright (c) 2007 Matthew W. S. Bell <mentor@madwifi.org>
|
||||
* Copyright (c) 2007 Luis Rodriguez <mcgrof@winlab.rutgers.edu>
|
||||
*
|
||||
* Permission to use, copy, modify, and distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <linux/delay.h>
|
||||
|
||||
/*
|
||||
* Gain settings
|
||||
*/
|
||||
|
||||
enum ath5k_rfgain {
|
||||
AR5K_RFGAIN_INACTIVE = 0,
|
||||
AR5K_RFGAIN_READ_REQUESTED,
|
||||
AR5K_RFGAIN_NEED_CHANGE,
|
||||
};
|
||||
|
||||
#define AR5K_GAIN_CRN_FIX_BITS_5111 4
|
||||
#define AR5K_GAIN_CRN_FIX_BITS_5112 7
|
||||
#define AR5K_GAIN_CRN_MAX_FIX_BITS AR5K_GAIN_CRN_FIX_BITS_5112
|
||||
#define AR5K_GAIN_DYN_ADJUST_HI_MARGIN 15
|
||||
#define AR5K_GAIN_DYN_ADJUST_LO_MARGIN 20
|
||||
#define AR5K_GAIN_CCK_PROBE_CORR 5
|
||||
#define AR5K_GAIN_CCK_OFDM_GAIN_DELTA 15
|
||||
#define AR5K_GAIN_STEP_COUNT 10
|
||||
#define AR5K_GAIN_PARAM_TX_CLIP 0
|
||||
#define AR5K_GAIN_PARAM_PD_90 1
|
||||
#define AR5K_GAIN_PARAM_PD_84 2
|
||||
#define AR5K_GAIN_PARAM_GAIN_SEL 3
|
||||
#define AR5K_GAIN_PARAM_MIX_ORN 0
|
||||
#define AR5K_GAIN_PARAM_PD_138 1
|
||||
#define AR5K_GAIN_PARAM_PD_137 2
|
||||
#define AR5K_GAIN_PARAM_PD_136 3
|
||||
#define AR5K_GAIN_PARAM_PD_132 4
|
||||
#define AR5K_GAIN_PARAM_PD_131 5
|
||||
#define AR5K_GAIN_PARAM_PD_130 6
|
||||
#define AR5K_GAIN_CHECK_ADJUST(_g) \
|
||||
((_g)->g_current <= (_g)->g_low || (_g)->g_current >= (_g)->g_high)
|
||||
|
||||
struct ath5k_gain_opt_step {
|
||||
s16 gos_param[AR5K_GAIN_CRN_MAX_FIX_BITS];
|
||||
s32 gos_gain;
|
||||
};
|
||||
|
||||
struct ath5k_gain {
|
||||
u32 g_step_idx;
|
||||
u32 g_current;
|
||||
u32 g_target;
|
||||
u32 g_low;
|
||||
u32 g_high;
|
||||
u32 g_f_corr;
|
||||
u32 g_active;
|
||||
const struct ath5k_gain_opt_step *g_step;
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* HW SPECIFIC STRUCTS
|
||||
*/
|
||||
|
||||
/* Some EEPROM defines */
|
||||
#define AR5K_EEPROM_EEP_SCALE 100
|
||||
#define AR5K_EEPROM_EEP_DELTA 10
|
||||
#define AR5K_EEPROM_N_MODES 3
|
||||
#define AR5K_EEPROM_N_5GHZ_CHAN 10
|
||||
#define AR5K_EEPROM_N_2GHZ_CHAN 3
|
||||
#define AR5K_EEPROM_MAX_CHAN 10
|
||||
#define AR5K_EEPROM_N_PCDAC 11
|
||||
#define AR5K_EEPROM_N_TEST_FREQ 8
|
||||
#define AR5K_EEPROM_N_EDGES 8
|
||||
#define AR5K_EEPROM_N_INTERCEPTS 11
|
||||
#define AR5K_EEPROM_FREQ_M(_v) AR5K_EEPROM_OFF(_v, 0x7f, 0xff)
|
||||
#define AR5K_EEPROM_PCDAC_M 0x3f
|
||||
#define AR5K_EEPROM_PCDAC_START 1
|
||||
#define AR5K_EEPROM_PCDAC_STOP 63
|
||||
#define AR5K_EEPROM_PCDAC_STEP 1
|
||||
#define AR5K_EEPROM_NON_EDGE_M 0x40
|
||||
#define AR5K_EEPROM_CHANNEL_POWER 8
|
||||
#define AR5K_EEPROM_N_OBDB 4
|
||||
#define AR5K_EEPROM_OBDB_DIS 0xffff
|
||||
#define AR5K_EEPROM_CHANNEL_DIS 0xff
|
||||
#define AR5K_EEPROM_SCALE_OC_DELTA(_x) (((_x) * 2) / 10)
|
||||
#define AR5K_EEPROM_N_CTLS(_v) AR5K_EEPROM_OFF(_v, 16, 32)
|
||||
#define AR5K_EEPROM_MAX_CTLS 32
|
||||
#define AR5K_EEPROM_N_XPD_PER_CHANNEL 4
|
||||
#define AR5K_EEPROM_N_XPD0_POINTS 4
|
||||
#define AR5K_EEPROM_N_XPD3_POINTS 3
|
||||
#define AR5K_EEPROM_N_INTERCEPT_10_2GHZ 35
|
||||
#define AR5K_EEPROM_N_INTERCEPT_10_5GHZ 55
|
||||
#define AR5K_EEPROM_POWER_M 0x3f
|
||||
#define AR5K_EEPROM_POWER_MIN 0
|
||||
#define AR5K_EEPROM_POWER_MAX 3150
|
||||
#define AR5K_EEPROM_POWER_STEP 50
|
||||
#define AR5K_EEPROM_POWER_TABLE_SIZE 64
|
||||
#define AR5K_EEPROM_N_POWER_LOC_11B 4
|
||||
#define AR5K_EEPROM_N_POWER_LOC_11G 6
|
||||
#define AR5K_EEPROM_I_GAIN 10
|
||||
#define AR5K_EEPROM_CCK_OFDM_DELTA 15
|
||||
#define AR5K_EEPROM_N_IQ_CAL 2
|
||||
|
||||
/* Struct to hold EEPROM calibration data */
|
||||
struct ath5k_eeprom_info {
|
||||
u16 ee_magic;
|
||||
u16 ee_protect;
|
||||
u16 ee_regdomain;
|
||||
u16 ee_version;
|
||||
u16 ee_header;
|
||||
u16 ee_ant_gain;
|
||||
u16 ee_misc0;
|
||||
u16 ee_misc1;
|
||||
u16 ee_cck_ofdm_gain_delta;
|
||||
u16 ee_cck_ofdm_power_delta;
|
||||
u16 ee_scaled_cck_delta;
|
||||
|
||||
/* Used for tx thermal adjustment (eeprom_init, rfregs) */
|
||||
u16 ee_tx_clip;
|
||||
u16 ee_pwd_84;
|
||||
u16 ee_pwd_90;
|
||||
u16 ee_gain_select;
|
||||
|
||||
/* RF Calibration settings (reset, rfregs) */
|
||||
u16 ee_i_cal[AR5K_EEPROM_N_MODES];
|
||||
u16 ee_q_cal[AR5K_EEPROM_N_MODES];
|
||||
u16 ee_fixed_bias[AR5K_EEPROM_N_MODES];
|
||||
u16 ee_turbo_max_power[AR5K_EEPROM_N_MODES];
|
||||
u16 ee_xr_power[AR5K_EEPROM_N_MODES];
|
||||
u16 ee_switch_settling[AR5K_EEPROM_N_MODES];
|
||||
u16 ee_ant_tx_rx[AR5K_EEPROM_N_MODES];
|
||||
u16 ee_ant_control[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_PCDAC];
|
||||
u16 ee_ob[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB];
|
||||
u16 ee_db[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_OBDB];
|
||||
u16 ee_tx_end2xlna_enable[AR5K_EEPROM_N_MODES];
|
||||
u16 ee_tx_end2xpa_disable[AR5K_EEPROM_N_MODES];
|
||||
u16 ee_tx_frm2xpa_enable[AR5K_EEPROM_N_MODES];
|
||||
u16 ee_thr_62[AR5K_EEPROM_N_MODES];
|
||||
u16 ee_xlna_gain[AR5K_EEPROM_N_MODES];
|
||||
u16 ee_xpd[AR5K_EEPROM_N_MODES];
|
||||
u16 ee_x_gain[AR5K_EEPROM_N_MODES];
|
||||
u16 ee_i_gain[AR5K_EEPROM_N_MODES];
|
||||
u16 ee_margin_tx_rx[AR5K_EEPROM_N_MODES];
|
||||
|
||||
/* Unused */
|
||||
u16 ee_false_detect[AR5K_EEPROM_N_MODES];
|
||||
u16 ee_cal_pier[AR5K_EEPROM_N_MODES][AR5K_EEPROM_N_2GHZ_CHAN];
|
||||
u16 ee_channel[AR5K_EEPROM_N_MODES][AR5K_EEPROM_MAX_CHAN]; /*empty*/
|
||||
|
||||
/* Conformance test limits (Unused) */
|
||||
u16 ee_ctls;
|
||||
u16 ee_ctl[AR5K_EEPROM_MAX_CTLS];
|
||||
|
||||
/* Noise Floor Calibration settings */
|
||||
s16 ee_noise_floor_thr[AR5K_EEPROM_N_MODES];
|
||||
s8 ee_adc_desired_size[AR5K_EEPROM_N_MODES];
|
||||
s8 ee_pga_desired_size[AR5K_EEPROM_N_MODES];
|
||||
};
|
||||
|
||||
/*
|
||||
* Internal RX/TX descriptor structures
|
||||
* (rX: reserved fields possibily used by future versions of the ar5k chipset)
|
||||
*/
|
||||
|
||||
struct ath5k_rx_desc {
|
||||
u32 rx_control_0; /* RX control word 0 */
|
||||
|
||||
#define AR5K_DESC_RX_CTL0 0x00000000
|
||||
|
||||
u32 rx_control_1; /* RX control word 1 */
|
||||
|
||||
#define AR5K_DESC_RX_CTL1_BUF_LEN 0x00000fff
|
||||
#define AR5K_DESC_RX_CTL1_INTREQ 0x00002000
|
||||
} __packed;
|
||||
|
||||
/*
|
||||
* 5210/5211 rx status descriptor
|
||||
*/
|
||||
struct ath5k_hw_old_rx_status {
|
||||
u32 rx_status_0; /* RX status word 0 */
|
||||
|
||||
#define AR5K_OLD_RX_DESC_STATUS0_DATA_LEN 0x00000fff
|
||||
#define AR5K_OLD_RX_DESC_STATUS0_MORE 0x00001000
|
||||
#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_RATE 0x00078000
|
||||
#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_RATE_S 15
|
||||
#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x07f80000
|
||||
#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_SIGNAL_S 19
|
||||
#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_ANTENNA 0x38000000
|
||||
#define AR5K_OLD_RX_DESC_STATUS0_RECEIVE_ANTENNA_S 27
|
||||
|
||||
u32 rx_status_1; /* RX status word 1 */
|
||||
|
||||
#define AR5K_OLD_RX_DESC_STATUS1_DONE 0x00000001
|
||||
#define AR5K_OLD_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002
|
||||
#define AR5K_OLD_RX_DESC_STATUS1_CRC_ERROR 0x00000004
|
||||
#define AR5K_OLD_RX_DESC_STATUS1_FIFO_OVERRUN 0x00000008
|
||||
#define AR5K_OLD_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000010
|
||||
#define AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR 0x000000e0
|
||||
#define AR5K_OLD_RX_DESC_STATUS1_PHY_ERROR_S 5
|
||||
#define AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100
|
||||
#define AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX 0x00007e00
|
||||
#define AR5K_OLD_RX_DESC_STATUS1_KEY_INDEX_S 9
|
||||
#define AR5K_OLD_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x0fff8000
|
||||
#define AR5K_OLD_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 15
|
||||
#define AR5K_OLD_RX_DESC_STATUS1_KEY_CACHE_MISS 0x10000000
|
||||
} __packed;
|
||||
|
||||
/*
|
||||
* 5212 rx status descriptor
|
||||
*/
|
||||
struct ath5k_hw_new_rx_status {
|
||||
u32 rx_status_0; /* RX status word 0 */
|
||||
|
||||
#define AR5K_NEW_RX_DESC_STATUS0_DATA_LEN 0x00000fff
|
||||
#define AR5K_NEW_RX_DESC_STATUS0_MORE 0x00001000
|
||||
#define AR5K_NEW_RX_DESC_STATUS0_DECOMP_CRC_ERROR 0x00002000
|
||||
#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_RATE 0x000f8000
|
||||
#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_RATE_S 15
|
||||
#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_SIGNAL 0x0ff00000
|
||||
#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_SIGNAL_S 20
|
||||
#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_ANTENNA 0xf0000000
|
||||
#define AR5K_NEW_RX_DESC_STATUS0_RECEIVE_ANTENNA_S 28
|
||||
|
||||
u32 rx_status_1; /* RX status word 1 */
|
||||
|
||||
#define AR5K_NEW_RX_DESC_STATUS1_DONE 0x00000001
|
||||
#define AR5K_NEW_RX_DESC_STATUS1_FRAME_RECEIVE_OK 0x00000002
|
||||
#define AR5K_NEW_RX_DESC_STATUS1_CRC_ERROR 0x00000004
|
||||
#define AR5K_NEW_RX_DESC_STATUS1_DECRYPT_CRC_ERROR 0x00000008
|
||||
#define AR5K_NEW_RX_DESC_STATUS1_PHY_ERROR 0x00000010
|
||||
#define AR5K_NEW_RX_DESC_STATUS1_MIC_ERROR 0x00000020
|
||||
#define AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX_VALID 0x00000100
|
||||
#define AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX 0x0000fe00
|
||||
#define AR5K_NEW_RX_DESC_STATUS1_KEY_INDEX_S 9
|
||||
#define AR5K_NEW_RX_DESC_STATUS1_RECEIVE_TIMESTAMP 0x7fff0000
|
||||
#define AR5K_NEW_RX_DESC_STATUS1_RECEIVE_TIMESTAMP_S 16
|
||||
#define AR5K_NEW_RX_DESC_STATUS1_KEY_CACHE_MISS 0x80000000
|
||||
} __packed;
|
||||
|
||||
struct ath5k_hw_rx_error {
|
||||
u32 rx_error_0; /* RX error word 0 */
|
||||
|
||||
#define AR5K_RX_DESC_ERROR0 0x00000000
|
||||
|
||||
u32 rx_error_1; /* RX error word 1 */
|
||||
|
||||
#define AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE 0x0000ff00
|
||||
#define AR5K_RX_DESC_ERROR1_PHY_ERROR_CODE_S 8
|
||||
} __packed;
|
||||
|
||||
#define AR5K_DESC_RX_PHY_ERROR_NONE 0x00
|
||||
#define AR5K_DESC_RX_PHY_ERROR_TIMING 0x20
|
||||
#define AR5K_DESC_RX_PHY_ERROR_PARITY 0x40
|
||||
#define AR5K_DESC_RX_PHY_ERROR_RATE 0x60
|
||||
#define AR5K_DESC_RX_PHY_ERROR_LENGTH 0x80
|
||||
#define AR5K_DESC_RX_PHY_ERROR_64QAM 0xa0
|
||||
#define AR5K_DESC_RX_PHY_ERROR_SERVICE 0xc0
|
||||
#define AR5K_DESC_RX_PHY_ERROR_TRANSMITOVR 0xe0
|
||||
|
||||
struct ath5k_hw_2w_tx_desc {
|
||||
u32 tx_control_0; /* TX control word 0 */
|
||||
|
||||
#define AR5K_2W_TX_DESC_CTL0_FRAME_LEN 0x00000fff
|
||||
#define AR5K_2W_TX_DESC_CTL0_HEADER_LEN 0x0003f000 /*[5210 ?]*/
|
||||
#define AR5K_2W_TX_DESC_CTL0_HEADER_LEN_S 12
|
||||
#define AR5K_2W_TX_DESC_CTL0_XMIT_RATE 0x003c0000
|
||||
#define AR5K_2W_TX_DESC_CTL0_XMIT_RATE_S 18
|
||||
#define AR5K_2W_TX_DESC_CTL0_RTSENA 0x00400000
|
||||
#define AR5K_2W_TX_DESC_CTL0_CLRDMASK 0x01000000
|
||||
#define AR5K_2W_TX_DESC_CTL0_LONG_PACKET 0x00800000 /*[5210]*/
|
||||
#define AR5K_2W_TX_DESC_CTL0_VEOL 0x00800000 /*[5211]*/
|
||||
#define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE 0x1c000000 /*[5210]*/
|
||||
#define AR5K_2W_TX_DESC_CTL0_FRAME_TYPE_S 26
|
||||
#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 0x02000000
|
||||
#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211 0x1e000000
|
||||
#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT (ah->ah_version == AR5K_AR5210 ? \
|
||||
AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5210 : \
|
||||
AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_5211)
|
||||
#define AR5K_2W_TX_DESC_CTL0_ANT_MODE_XMIT_S 25
|
||||
#define AR5K_2W_TX_DESC_CTL0_INTREQ 0x20000000
|
||||
#define AR5K_2W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000
|
||||
|
||||
u32 tx_control_1; /* TX control word 1 */
|
||||
|
||||
#define AR5K_2W_TX_DESC_CTL1_BUF_LEN 0x00000fff
|
||||
#define AR5K_2W_TX_DESC_CTL1_MORE 0x00001000
|
||||
#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5210 0x0007e000
|
||||
#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5211 0x000fe000
|
||||
#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX (ah->ah_version == AR5K_AR5210 ? \
|
||||
AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5210 : \
|
||||
AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_5211)
|
||||
#define AR5K_2W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_S 13
|
||||
#define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE 0x00700000 /*[5211]*/
|
||||
#define AR5K_2W_TX_DESC_CTL1_FRAME_TYPE_S 20
|
||||
#define AR5K_2W_TX_DESC_CTL1_NOACK 0x00800000 /*[5211]*/
|
||||
#define AR5K_2W_TX_DESC_CTL1_RTS_DURATION 0xfff80000 /*[5210 ?]*/
|
||||
} __packed;
|
||||
|
||||
#define AR5K_AR5210_TX_DESC_FRAME_TYPE_NORMAL 0x00
|
||||
#define AR5K_AR5210_TX_DESC_FRAME_TYPE_ATIM 0x04
|
||||
#define AR5K_AR5210_TX_DESC_FRAME_TYPE_PSPOLL 0x08
|
||||
#define AR5K_AR5210_TX_DESC_FRAME_TYPE_NO_DELAY 0x0c
|
||||
#define AR5K_AR5210_TX_DESC_FRAME_TYPE_PIFS 0x10
|
||||
|
||||
/*
|
||||
* 5212 4-word tx control descriptor
|
||||
*/
|
||||
struct ath5k_hw_4w_tx_desc {
|
||||
u32 tx_control_0; /* TX control word 0 */
|
||||
|
||||
#define AR5K_4W_TX_DESC_CTL0_FRAME_LEN 0x00000fff
|
||||
#define AR5K_4W_TX_DESC_CTL0_XMIT_POWER 0x003f0000
|
||||
#define AR5K_4W_TX_DESC_CTL0_XMIT_POWER_S 16
|
||||
#define AR5K_4W_TX_DESC_CTL0_RTSENA 0x00400000
|
||||
#define AR5K_4W_TX_DESC_CTL0_VEOL 0x00800000
|
||||
#define AR5K_4W_TX_DESC_CTL0_CLRDMASK 0x01000000
|
||||
#define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT 0x1e000000
|
||||
#define AR5K_4W_TX_DESC_CTL0_ANT_MODE_XMIT_S 25
|
||||
#define AR5K_4W_TX_DESC_CTL0_INTREQ 0x20000000
|
||||
#define AR5K_4W_TX_DESC_CTL0_ENCRYPT_KEY_VALID 0x40000000
|
||||
#define AR5K_4W_TX_DESC_CTL0_CTSENA 0x80000000
|
||||
|
||||
u32 tx_control_1; /* TX control word 1 */
|
||||
|
||||
#define AR5K_4W_TX_DESC_CTL1_BUF_LEN 0x00000fff
|
||||
#define AR5K_4W_TX_DESC_CTL1_MORE 0x00001000
|
||||
#define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX 0x000fe000
|
||||
#define AR5K_4W_TX_DESC_CTL1_ENCRYPT_KEY_INDEX_S 13
|
||||
#define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE 0x00f00000
|
||||
#define AR5K_4W_TX_DESC_CTL1_FRAME_TYPE_S 20
|
||||
#define AR5K_4W_TX_DESC_CTL1_NOACK 0x01000000
|
||||
#define AR5K_4W_TX_DESC_CTL1_COMP_PROC 0x06000000
|
||||
#define AR5K_4W_TX_DESC_CTL1_COMP_PROC_S 25
|
||||
#define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN 0x18000000
|
||||
#define AR5K_4W_TX_DESC_CTL1_COMP_IV_LEN_S 27
|
||||
#define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN 0x60000000
|
||||
#define AR5K_4W_TX_DESC_CTL1_COMP_ICV_LEN_S 29
|
||||
|
||||
u32 tx_control_2; /* TX control word 2 */
|
||||
|
||||
#define AR5K_4W_TX_DESC_CTL2_RTS_DURATION 0x00007fff
|
||||
#define AR5K_4W_TX_DESC_CTL2_DURATION_UPDATE_ENABLE 0x00008000
|
||||
#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0 0x000f0000
|
||||
#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES0_S 16
|
||||
#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1 0x00f00000
|
||||
#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES1_S 20
|
||||
#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2 0x0f000000
|
||||
#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES2_S 24
|
||||
#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3 0xf0000000
|
||||
#define AR5K_4W_TX_DESC_CTL2_XMIT_TRIES3_S 28
|
||||
|
||||
u32 tx_control_3; /* TX control word 3 */
|
||||
|
||||
#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE0 0x0000001f
|
||||
#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1 0x000003e0
|
||||
#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE1_S 5
|
||||
#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2 0x00007c00
|
||||
#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE2_S 10
|
||||
#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3 0x000f8000
|
||||
#define AR5K_4W_TX_DESC_CTL3_XMIT_RATE3_S 15
|
||||
#define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE 0x01f00000
|
||||
#define AR5K_4W_TX_DESC_CTL3_RTS_CTS_RATE_S 20
|
||||
} __packed;
|
||||
|
||||
/*
|
||||
* Common tx status descriptor
|
||||
*/
|
||||
struct ath5k_hw_tx_status {
|
||||
u32 tx_status_0; /* TX status word 0 */
|
||||
|
||||
#define AR5K_DESC_TX_STATUS0_FRAME_XMIT_OK 0x00000001
|
||||
#define AR5K_DESC_TX_STATUS0_EXCESSIVE_RETRIES 0x00000002
|
||||
#define AR5K_DESC_TX_STATUS0_FIFO_UNDERRUN 0x00000004
|
||||
#define AR5K_DESC_TX_STATUS0_FILTERED 0x00000008
|
||||
/*???
|
||||
#define AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT 0x000000f0
|
||||
#define AR5K_DESC_TX_STATUS0_RTS_FAIL_COUNT_S 4
|
||||
*/
|
||||
#define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT 0x000000f0
|
||||
#define AR5K_DESC_TX_STATUS0_SHORT_RETRY_COUNT_S 4
|
||||
/*???
|
||||
#define AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT 0x00000f00
|
||||
#define AR5K_DESC_TX_STATUS0_DATA_FAIL_COUNT_S 8
|
||||
*/
|
||||
#define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT 0x00000f00
|
||||
#define AR5K_DESC_TX_STATUS0_LONG_RETRY_COUNT_S 8
|
||||
#define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT 0x0000f000
|
||||
#define AR5K_DESC_TX_STATUS0_VIRT_COLL_COUNT_S 12
|
||||
#define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP 0xffff0000
|
||||
#define AR5K_DESC_TX_STATUS0_SEND_TIMESTAMP_S 16
|
||||
|
||||
u32 tx_status_1; /* TX status word 1 */
|
||||
|
||||
#define AR5K_DESC_TX_STATUS1_DONE 0x00000001
|
||||
#define AR5K_DESC_TX_STATUS1_SEQ_NUM 0x00001ffe
|
||||
#define AR5K_DESC_TX_STATUS1_SEQ_NUM_S 1
|
||||
#define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH 0x001fe000
|
||||
#define AR5K_DESC_TX_STATUS1_ACK_SIG_STRENGTH_S 13
|
||||
#define AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX 0x00600000
|
||||
#define AR5K_DESC_TX_STATUS1_FINAL_TS_INDEX_S 21
|
||||
#define AR5K_DESC_TX_STATUS1_COMP_SUCCESS 0x00800000
|
||||
#define AR5K_DESC_TX_STATUS1_XMIT_ANTENNA 0x01000000
|
||||
} __packed;
|
||||
|
||||
|
||||
/*
|
||||
* AR5K REGISTER ACCESS
|
||||
*/
|
||||
|
||||
/*Swap RX/TX Descriptor for big endian archs*/
|
||||
#if defined(__BIG_ENDIAN)
|
||||
#define AR5K_INIT_CFG ( \
|
||||
AR5K_CFG_SWTD | AR5K_CFG_SWRD \
|
||||
)
|
||||
#else
|
||||
#define AR5K_INIT_CFG 0x00000000
|
||||
#endif
|
||||
|
||||
/*#define AR5K_REG_READ(_reg) ath5k_hw_reg_read(ah, _reg)
|
||||
|
||||
#define AR5K_REG_WRITE(_reg, _val) ath5k_hw_reg_write(ah, _val, _reg)*/
|
||||
|
||||
#define AR5K_REG_SM(_val, _flags) \
|
||||
(((_val) << _flags##_S) & (_flags))
|
||||
|
||||
#define AR5K_REG_MS(_val, _flags) \
|
||||
(((_val) & (_flags)) >> _flags##_S)
|
||||
|
||||
/* Some registers can hold multiple values of interest. For this
|
||||
* reason when we want to write to these registers we must first
|
||||
* retrieve the values which we do not want to clear (lets call this
|
||||
* old_data) and then set the register with this and our new_value:
|
||||
* ( old_data | new_value) */
|
||||
#define AR5K_REG_WRITE_BITS(ah, _reg, _flags, _val) \
|
||||
ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & ~(_flags)) | \
|
||||
(((_val) << _flags##_S) & (_flags)), _reg)
|
||||
|
||||
#define AR5K_REG_MASKED_BITS(ah, _reg, _flags, _mask) \
|
||||
ath5k_hw_reg_write(ah, (ath5k_hw_reg_read(ah, _reg) & \
|
||||
(_mask)) | (_flags), _reg)
|
||||
|
||||
#define AR5K_REG_ENABLE_BITS(ah, _reg, _flags) \
|
||||
ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) | (_flags), _reg)
|
||||
|
||||
#define AR5K_REG_DISABLE_BITS(ah, _reg, _flags) \
|
||||
ath5k_hw_reg_write(ah, ath5k_hw_reg_read(ah, _reg) & ~(_flags), _reg)
|
||||
|
||||
#define AR5K_PHY_WRITE(ah, _reg, _val) \
|
||||
ath5k_hw_reg_write(ah, _val, (ah)->ah_phy + ((_reg) << 2))
|
||||
|
||||
#define AR5K_PHY_READ(ah, _reg) \
|
||||
ath5k_hw_reg_read(ah, (ah)->ah_phy + ((_reg) << 2))
|
||||
|
||||
#define AR5K_REG_WAIT(_i) do { \
|
||||
if (_i % 64) \
|
||||
udelay(1); \
|
||||
} while (0)
|
||||
|
||||
#define AR5K_EEPROM_READ(_o, _v) do { \
|
||||
if ((ret = ath5k_hw_eeprom_read(ah, (_o), &(_v))) != 0) \
|
||||
return (ret); \
|
||||
} while (0)
|
||||
|
||||
#define AR5K_EEPROM_READ_HDR(_o, _v) \
|
||||
AR5K_EEPROM_READ(_o, ah->ah_capabilities.cap_eeprom._v); \
|
||||
|
||||
/* Read status of selected queue */
|
||||
#define AR5K_REG_READ_Q(ah, _reg, _queue) \
|
||||
(ath5k_hw_reg_read(ah, _reg) & (1 << _queue)) \
|
||||
|
||||
#define AR5K_REG_WRITE_Q(ah, _reg, _queue) \
|
||||
ath5k_hw_reg_write(ah, (1 << _queue), _reg)
|
||||
|
||||
#define AR5K_Q_ENABLE_BITS(_reg, _queue) do { \
|
||||
_reg |= 1 << _queue; \
|
||||
} while (0)
|
||||
|
||||
#define AR5K_Q_DISABLE_BITS(_reg, _queue) do { \
|
||||
_reg &= ~(1 << _queue); \
|
||||
} while (0)
|
||||
|
||||
#define AR5K_LOW_ID(_a)( \
|
||||
(_a)[0] | (_a)[1] << 8 | (_a)[2] << 16 | (_a)[3] << 24 \
|
||||
)
|
||||
|
||||
#define AR5K_HIGH_ID(_a) ((_a)[4] | (_a)[5] << 8)
|
||||
|
||||
/*
|
||||
* Initial register values
|
||||
*/
|
||||
|
||||
/*
|
||||
* Common initial register values
|
||||
*/
|
||||
#define AR5K_INIT_MODE CHANNEL_B
|
||||
|
||||
#define AR5K_INIT_TX_LATENCY 502
|
||||
#define AR5K_INIT_USEC 39
|
||||
#define AR5K_INIT_USEC_TURBO 79
|
||||
#define AR5K_INIT_USEC_32 31
|
||||
#define AR5K_INIT_CARR_SENSE_EN 1
|
||||
#define AR5K_INIT_PROG_IFS 920
|
||||
#define AR5K_INIT_PROG_IFS_TURBO 960
|
||||
#define AR5K_INIT_EIFS 3440
|
||||
#define AR5K_INIT_EIFS_TURBO 6880
|
||||
#define AR5K_INIT_SLOT_TIME 396
|
||||
#define AR5K_INIT_SLOT_TIME_TURBO 480
|
||||
#define AR5K_INIT_ACK_CTS_TIMEOUT 1024
|
||||
#define AR5K_INIT_ACK_CTS_TIMEOUT_TURBO 0x08000800
|
||||
#define AR5K_INIT_SIFS 560
|
||||
#define AR5K_INIT_SIFS_TURBO 480
|
||||
#define AR5K_INIT_SH_RETRY 10
|
||||
#define AR5K_INIT_LG_RETRY AR5K_INIT_SH_RETRY
|
||||
#define AR5K_INIT_SSH_RETRY 32
|
||||
#define AR5K_INIT_SLG_RETRY AR5K_INIT_SSH_RETRY
|
||||
#define AR5K_INIT_TX_RETRY 10
|
||||
#define AR5K_INIT_TOPS 8
|
||||
#define AR5K_INIT_RXNOFRM 8
|
||||
#define AR5K_INIT_RPGTO 0
|
||||
#define AR5K_INIT_TXNOFRM 0
|
||||
#define AR5K_INIT_BEACON_PERIOD 65535
|
||||
#define AR5K_INIT_TIM_OFFSET 0
|
||||
#define AR5K_INIT_BEACON_EN 0
|
||||
#define AR5K_INIT_RESET_TSF 0
|
||||
|
||||
#define AR5K_INIT_TRANSMIT_LATENCY ( \
|
||||
(AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
|
||||
(AR5K_INIT_USEC) \
|
||||
)
|
||||
#define AR5K_INIT_TRANSMIT_LATENCY_TURBO ( \
|
||||
(AR5K_INIT_TX_LATENCY << 14) | (AR5K_INIT_USEC_32 << 7) | \
|
||||
(AR5K_INIT_USEC_TURBO) \
|
||||
)
|
||||
#define AR5K_INIT_PROTO_TIME_CNTRL ( \
|
||||
(AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS << 12) | \
|
||||
(AR5K_INIT_PROG_IFS) \
|
||||
)
|
||||
#define AR5K_INIT_PROTO_TIME_CNTRL_TURBO ( \
|
||||
(AR5K_INIT_CARR_SENSE_EN << 26) | (AR5K_INIT_EIFS_TURBO << 12) | \
|
||||
(AR5K_INIT_PROG_IFS_TURBO) \
|
||||
)
|
||||
#define AR5K_INIT_BEACON_CONTROL ( \
|
||||
(AR5K_INIT_RESET_TSF << 24) | (AR5K_INIT_BEACON_EN << 23) | \
|
||||
(AR5K_INIT_TIM_OFFSET << 16) | (AR5K_INIT_BEACON_PERIOD) \
|
||||
)
|
||||
|
||||
/*
|
||||
* Non-common initial register values which have to be loaded into the
|
||||
* card at boot time and after each reset.
|
||||
*/
|
||||
|
||||
/* Register dumps are done per operation mode */
|
||||
#define AR5K_INI_RFGAIN_5GHZ 0
|
||||
#define AR5K_INI_RFGAIN_2GHZ 1
|
||||
|
||||
#define AR5K_INI_VAL_11A 0
|
||||
#define AR5K_INI_VAL_11A_TURBO 1
|
||||
#define AR5K_INI_VAL_11B 2
|
||||
#define AR5K_INI_VAL_11G 3
|
||||
#define AR5K_INI_VAL_11G_TURBO 4
|
||||
#define AR5K_INI_VAL_XR 0
|
||||
#define AR5K_INI_VAL_MAX 5
|
||||
|
||||
#define AR5K_RF5111_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS
|
||||
#define AR5K_RF5112_INI_RF_MAX_BANKS AR5K_MAX_RF_BANKS
|
||||
|
||||
static inline u32 ath5k_hw_bitswap(u32 val, unsigned int bits)
|
||||
{
|
||||
u32 retval = 0, bit, i;
|
||||
|
||||
for (i = 0; i < bits; i++) {
|
||||
bit = (val >> i) & 1;
|
||||
retval = (retval << 1) | bit;
|
||||
}
|
||||
|
||||
return retval;
|
||||
}
|
||||
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
Разница между файлами не показана из-за своего большого размера
Загрузить разницу
|
|
@ -0,0 +1,121 @@
|
|||
/*
|
||||
* Copyright (c) 2004, 2005 Reyk Floeter <reyk@vantronix.net>
|
||||
*
|
||||
* Permission to use, copy, modify, and distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
/*
|
||||
* Basic regulation domain extensions for the IEEE 802.11 stack
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/string.h>
|
||||
|
||||
#include "regdom.h"
|
||||
|
||||
static const struct ath5k_regdommap {
|
||||
enum ath5k_regdom dmn;
|
||||
enum ath5k_regdom dmn5;
|
||||
enum ath5k_regdom dmn2;
|
||||
} r_map[] = {
|
||||
{ DMN_DEFAULT, DMN_DEBUG, DMN_DEBUG },
|
||||
{ DMN_NULL_WORLD, DMN_NULL, DMN_WORLD },
|
||||
{ DMN_NULL_ETSIB, DMN_NULL, DMN_ETSIB },
|
||||
{ DMN_NULL_ETSIC, DMN_NULL, DMN_ETSIC },
|
||||
{ DMN_FCC1_FCCA, DMN_FCC1, DMN_FCCA },
|
||||
{ DMN_FCC1_WORLD, DMN_FCC1, DMN_WORLD },
|
||||
{ DMN_FCC2_FCCA, DMN_FCC2, DMN_FCCA },
|
||||
{ DMN_FCC2_WORLD, DMN_FCC2, DMN_WORLD },
|
||||
{ DMN_FCC2_ETSIC, DMN_FCC2, DMN_ETSIC },
|
||||
{ DMN_FRANCE_NULL, DMN_ETSI3, DMN_ETSI3 },
|
||||
{ DMN_FCC3_FCCA, DMN_FCC3, DMN_WORLD },
|
||||
{ DMN_ETSI1_WORLD, DMN_ETSI1, DMN_WORLD },
|
||||
{ DMN_ETSI3_ETSIA, DMN_ETSI3, DMN_WORLD },
|
||||
{ DMN_ETSI2_WORLD, DMN_ETSI2, DMN_WORLD },
|
||||
{ DMN_ETSI3_WORLD, DMN_ETSI3, DMN_WORLD },
|
||||
{ DMN_ETSI4_WORLD, DMN_ETSI4, DMN_WORLD },
|
||||
{ DMN_ETSI4_ETSIC, DMN_ETSI4, DMN_ETSIC },
|
||||
{ DMN_ETSI5_WORLD, DMN_ETSI5, DMN_WORLD },
|
||||
{ DMN_ETSI6_WORLD, DMN_ETSI6, DMN_WORLD },
|
||||
{ DMN_ETSI_NULL, DMN_ETSI1, DMN_ETSI1 },
|
||||
{ DMN_MKK1_MKKA, DMN_MKK1, DMN_MKKA },
|
||||
{ DMN_MKK1_MKKB, DMN_MKK1, DMN_MKKA },
|
||||
{ DMN_APL4_WORLD, DMN_APL4, DMN_WORLD },
|
||||
{ DMN_MKK2_MKKA, DMN_MKK2, DMN_MKKA },
|
||||
{ DMN_APL_NULL, DMN_APL1, DMN_NULL },
|
||||
{ DMN_APL2_WORLD, DMN_APL2, DMN_WORLD },
|
||||
{ DMN_APL2_APLC, DMN_APL2, DMN_WORLD },
|
||||
{ DMN_APL3_WORLD, DMN_APL3, DMN_WORLD },
|
||||
{ DMN_MKK1_FCCA, DMN_MKK1, DMN_FCCA },
|
||||
{ DMN_APL2_APLD, DMN_APL2, DMN_APLD },
|
||||
{ DMN_MKK1_MKKA1, DMN_MKK1, DMN_MKKA },
|
||||
{ DMN_MKK1_MKKA2, DMN_MKK1, DMN_MKKA },
|
||||
{ DMN_APL1_WORLD, DMN_APL1, DMN_WORLD },
|
||||
{ DMN_APL1_FCCA, DMN_APL1, DMN_FCCA },
|
||||
{ DMN_APL1_APLA, DMN_APL1, DMN_WORLD },
|
||||
{ DMN_APL1_ETSIC, DMN_APL1, DMN_ETSIC },
|
||||
{ DMN_APL2_ETSIC, DMN_APL2, DMN_ETSIC },
|
||||
{ DMN_APL5_WORLD, DMN_APL5, DMN_WORLD },
|
||||
{ DMN_WOR0_WORLD, DMN_WORLD, DMN_WORLD },
|
||||
{ DMN_WOR1_WORLD, DMN_WORLD, DMN_WORLD },
|
||||
{ DMN_WOR2_WORLD, DMN_WORLD, DMN_WORLD },
|
||||
{ DMN_WOR3_WORLD, DMN_WORLD, DMN_WORLD },
|
||||
{ DMN_WOR4_WORLD, DMN_WORLD, DMN_WORLD },
|
||||
{ DMN_WOR5_ETSIC, DMN_WORLD, DMN_WORLD },
|
||||
{ DMN_WOR01_WORLD, DMN_WORLD, DMN_WORLD },
|
||||
{ DMN_WOR02_WORLD, DMN_WORLD, DMN_WORLD },
|
||||
{ DMN_EU1_WORLD, DMN_ETSI1, DMN_WORLD },
|
||||
{ DMN_WOR9_WORLD, DMN_WORLD, DMN_WORLD },
|
||||
{ DMN_WORA_WORLD, DMN_WORLD, DMN_WORLD },
|
||||
};
|
||||
|
||||
enum ath5k_regdom ath5k_regdom2flag(enum ath5k_regdom dmn, u16 mhz)
|
||||
{
|
||||
unsigned int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(r_map); i++) {
|
||||
if (r_map[i].dmn == dmn) {
|
||||
if (mhz >= 2000 && mhz <= 3000)
|
||||
return r_map[i].dmn2;
|
||||
if (mhz >= IEEE80211_CHANNELS_5GHZ_MIN &&
|
||||
mhz <= IEEE80211_CHANNELS_5GHZ_MAX)
|
||||
return r_map[i].dmn5;
|
||||
}
|
||||
}
|
||||
|
||||
return DMN_DEBUG;
|
||||
}
|
||||
|
||||
u16 ath5k_regdom_from_ieee(enum ath5k_regdom ieee)
|
||||
{
|
||||
u32 regdomain = (u32)ieee;
|
||||
|
||||
/*
|
||||
* Use the default regulation domain if the value is empty
|
||||
* or not supported by the net80211 regulation code.
|
||||
*/
|
||||
if (ath5k_regdom2flag(regdomain, IEEE80211_CHANNELS_5GHZ_MIN) ==
|
||||
DMN_DEBUG)
|
||||
return (u16)AR5K_TUNE_REGDOMAIN;
|
||||
|
||||
/* It is supported, just return the value */
|
||||
return regdomain;
|
||||
}
|
||||
|
||||
enum ath5k_regdom ath5k_regdom_to_ieee(u16 regdomain)
|
||||
{
|
||||
enum ath5k_regdom ieee = (enum ath5k_regdom)regdomain;
|
||||
|
||||
return ieee;
|
||||
}
|
||||
|
||||
|
|
@ -0,0 +1,500 @@
|
|||
/*
|
||||
* Copyright (c) 2004, 2005 Reyk Floeter <reyk@openbsd.org>
|
||||
*
|
||||
* Permission to use, copy, modify, and distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
* copyright notice and this permission notice appear in all copies.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
|
||||
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
|
||||
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
|
||||
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
|
||||
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
|
||||
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
|
||||
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef _IEEE80211_REGDOMAIN_H_
|
||||
#define _IEEE80211_REGDOMAIN_H_
|
||||
|
||||
#include <linux/types.h>
|
||||
|
||||
/* Default regulation domain if stored value EEPROM value is invalid */
|
||||
#define AR5K_TUNE_REGDOMAIN DMN_FCC2_FCCA /* Canada */
|
||||
#define AR5K_TUNE_CTRY CTRY_DEFAULT
|
||||
|
||||
|
||||
enum ath5k_regdom {
|
||||
DMN_DEFAULT = 0x00,
|
||||
DMN_NULL_WORLD = 0x03,
|
||||
DMN_NULL_ETSIB = 0x07,
|
||||
DMN_NULL_ETSIC = 0x08,
|
||||
DMN_FCC1_FCCA = 0x10,
|
||||
DMN_FCC1_WORLD = 0x11,
|
||||
DMN_FCC2_FCCA = 0x20,
|
||||
DMN_FCC2_WORLD = 0x21,
|
||||
DMN_FCC2_ETSIC = 0x22,
|
||||
DMN_FRANCE_NULL = 0x31,
|
||||
DMN_FCC3_FCCA = 0x3A,
|
||||
DMN_ETSI1_WORLD = 0x37,
|
||||
DMN_ETSI3_ETSIA = 0x32,
|
||||
DMN_ETSI2_WORLD = 0x35,
|
||||
DMN_ETSI3_WORLD = 0x36,
|
||||
DMN_ETSI4_WORLD = 0x30,
|
||||
DMN_ETSI4_ETSIC = 0x38,
|
||||
DMN_ETSI5_WORLD = 0x39,
|
||||
DMN_ETSI6_WORLD = 0x34,
|
||||
DMN_ETSI_NULL = 0x33,
|
||||
DMN_MKK1_MKKA = 0x40,
|
||||
DMN_MKK1_MKKB = 0x41,
|
||||
DMN_APL4_WORLD = 0x42,
|
||||
DMN_MKK2_MKKA = 0x43,
|
||||
DMN_APL_NULL = 0x44,
|
||||
DMN_APL2_WORLD = 0x45,
|
||||
DMN_APL2_APLC = 0x46,
|
||||
DMN_APL3_WORLD = 0x47,
|
||||
DMN_MKK1_FCCA = 0x48,
|
||||
DMN_APL2_APLD = 0x49,
|
||||
DMN_MKK1_MKKA1 = 0x4A,
|
||||
DMN_MKK1_MKKA2 = 0x4B,
|
||||
DMN_APL1_WORLD = 0x52,
|
||||
DMN_APL1_FCCA = 0x53,
|
||||
DMN_APL1_APLA = 0x54,
|
||||
DMN_APL1_ETSIC = 0x55,
|
||||
DMN_APL2_ETSIC = 0x56,
|
||||
DMN_APL5_WORLD = 0x58,
|
||||
DMN_WOR0_WORLD = 0x60,
|
||||
DMN_WOR1_WORLD = 0x61,
|
||||
DMN_WOR2_WORLD = 0x62,
|
||||
DMN_WOR3_WORLD = 0x63,
|
||||
DMN_WOR4_WORLD = 0x64,
|
||||
DMN_WOR5_ETSIC = 0x65,
|
||||
DMN_WOR01_WORLD = 0x66,
|
||||
DMN_WOR02_WORLD = 0x67,
|
||||
DMN_EU1_WORLD = 0x68,
|
||||
DMN_WOR9_WORLD = 0x69,
|
||||
DMN_WORA_WORLD = 0x6A,
|
||||
|
||||
DMN_APL1 = 0xf0000001,
|
||||
DMN_APL2 = 0xf0000002,
|
||||
DMN_APL3 = 0xf0000004,
|
||||
DMN_APL4 = 0xf0000008,
|
||||
DMN_APL5 = 0xf0000010,
|
||||
DMN_ETSI1 = 0xf0000020,
|
||||
DMN_ETSI2 = 0xf0000040,
|
||||
DMN_ETSI3 = 0xf0000080,
|
||||
DMN_ETSI4 = 0xf0000100,
|
||||
DMN_ETSI5 = 0xf0000200,
|
||||
DMN_ETSI6 = 0xf0000400,
|
||||
DMN_ETSIA = 0xf0000800,
|
||||
DMN_ETSIB = 0xf0001000,
|
||||
DMN_ETSIC = 0xf0002000,
|
||||
DMN_FCC1 = 0xf0004000,
|
||||
DMN_FCC2 = 0xf0008000,
|
||||
DMN_FCC3 = 0xf0010000,
|
||||
DMN_FCCA = 0xf0020000,
|
||||
DMN_APLD = 0xf0040000,
|
||||
DMN_MKK1 = 0xf0080000,
|
||||
DMN_MKK2 = 0xf0100000,
|
||||
DMN_MKKA = 0xf0200000,
|
||||
DMN_NULL = 0xf0400000,
|
||||
DMN_WORLD = 0xf0800000,
|
||||
DMN_DEBUG = 0xf1000000 /* used for debugging */
|
||||
};
|
||||
|
||||
#define IEEE80211_DMN(_d) ((_d) & ~0xf0000000)
|
||||
|
||||
enum ath5k_countrycode {
|
||||
CTRY_DEFAULT = 0, /* Default domain (NA) */
|
||||
CTRY_ALBANIA = 8, /* Albania */
|
||||
CTRY_ALGERIA = 12, /* Algeria */
|
||||
CTRY_ARGENTINA = 32, /* Argentina */
|
||||
CTRY_ARMENIA = 51, /* Armenia */
|
||||
CTRY_AUSTRALIA = 36, /* Australia */
|
||||
CTRY_AUSTRIA = 40, /* Austria */
|
||||
CTRY_AZERBAIJAN = 31, /* Azerbaijan */
|
||||
CTRY_BAHRAIN = 48, /* Bahrain */
|
||||
CTRY_BELARUS = 112, /* Belarus */
|
||||
CTRY_BELGIUM = 56, /* Belgium */
|
||||
CTRY_BELIZE = 84, /* Belize */
|
||||
CTRY_BOLIVIA = 68, /* Bolivia */
|
||||
CTRY_BRAZIL = 76, /* Brazil */
|
||||
CTRY_BRUNEI_DARUSSALAM = 96, /* Brunei Darussalam */
|
||||
CTRY_BULGARIA = 100, /* Bulgaria */
|
||||
CTRY_CANADA = 124, /* Canada */
|
||||
CTRY_CHILE = 152, /* Chile */
|
||||
CTRY_CHINA = 156, /* People's Republic of China */
|
||||
CTRY_COLOMBIA = 170, /* Colombia */
|
||||
CTRY_COSTA_RICA = 188, /* Costa Rica */
|
||||
CTRY_CROATIA = 191, /* Croatia */
|
||||
CTRY_CYPRUS = 196, /* Cyprus */
|
||||
CTRY_CZECH = 203, /* Czech Republic */
|
||||
CTRY_DENMARK = 208, /* Denmark */
|
||||
CTRY_DOMINICAN_REPUBLIC = 214, /* Dominican Republic */
|
||||
CTRY_ECUADOR = 218, /* Ecuador */
|
||||
CTRY_EGYPT = 818, /* Egypt */
|
||||
CTRY_EL_SALVADOR = 222, /* El Salvador */
|
||||
CTRY_ESTONIA = 233, /* Estonia */
|
||||
CTRY_FAEROE_ISLANDS = 234, /* Faeroe Islands */
|
||||
CTRY_FINLAND = 246, /* Finland */
|
||||
CTRY_FRANCE = 250, /* France */
|
||||
CTRY_FRANCE2 = 255, /* France2 */
|
||||
CTRY_GEORGIA = 268, /* Georgia */
|
||||
CTRY_GERMANY = 276, /* Germany */
|
||||
CTRY_GREECE = 300, /* Greece */
|
||||
CTRY_GUATEMALA = 320, /* Guatemala */
|
||||
CTRY_HONDURAS = 340, /* Honduras */
|
||||
CTRY_HONG_KONG = 344, /* Hong Kong S.A.R., P.R.C. */
|
||||
CTRY_HUNGARY = 348, /* Hungary */
|
||||
CTRY_ICELAND = 352, /* Iceland */
|
||||
CTRY_INDIA = 356, /* India */
|
||||
CTRY_INDONESIA = 360, /* Indonesia */
|
||||
CTRY_IRAN = 364, /* Iran */
|
||||
CTRY_IRAQ = 368, /* Iraq */
|
||||
CTRY_IRELAND = 372, /* Ireland */
|
||||
CTRY_ISRAEL = 376, /* Israel */
|
||||
CTRY_ITALY = 380, /* Italy */
|
||||
CTRY_JAMAICA = 388, /* Jamaica */
|
||||
CTRY_JAPAN = 392, /* Japan */
|
||||
CTRY_JAPAN1 = 393, /* Japan (JP1) */
|
||||
CTRY_JAPAN2 = 394, /* Japan (JP0) */
|
||||
CTRY_JAPAN3 = 395, /* Japan (JP1-1) */
|
||||
CTRY_JAPAN4 = 396, /* Japan (JE1) */
|
||||
CTRY_JAPAN5 = 397, /* Japan (JE2) */
|
||||
CTRY_JORDAN = 400, /* Jordan */
|
||||
CTRY_KAZAKHSTAN = 398, /* Kazakhstan */
|
||||
CTRY_KENYA = 404, /* Kenya */
|
||||
CTRY_KOREA_NORTH = 408, /* North Korea */
|
||||
CTRY_KOREA_ROC = 410, /* South Korea */
|
||||
CTRY_KOREA_ROC2 = 411, /* South Korea */
|
||||
CTRY_KUWAIT = 414, /* Kuwait */
|
||||
CTRY_LATVIA = 428, /* Latvia */
|
||||
CTRY_LEBANON = 422, /* Lebanon */
|
||||
CTRY_LIBYA = 434, /* Libya */
|
||||
CTRY_LIECHTENSTEIN = 438, /* Liechtenstein */
|
||||
CTRY_LITHUANIA = 440, /* Lithuania */
|
||||
CTRY_LUXEMBOURG = 442, /* Luxembourg */
|
||||
CTRY_MACAU = 446, /* Macau */
|
||||
CTRY_MACEDONIA = 807, /* Republic of Macedonia */
|
||||
CTRY_MALAYSIA = 458, /* Malaysia */
|
||||
CTRY_MEXICO = 484, /* Mexico */
|
||||
CTRY_MONACO = 492, /* Principality of Monaco */
|
||||
CTRY_MOROCCO = 504, /* Morocco */
|
||||
CTRY_NETHERLANDS = 528, /* Netherlands */
|
||||
CTRY_NEW_ZEALAND = 554, /* New Zealand */
|
||||
CTRY_NICARAGUA = 558, /* Nicaragua */
|
||||
CTRY_NORWAY = 578, /* Norway */
|
||||
CTRY_OMAN = 512, /* Oman */
|
||||
CTRY_PAKISTAN = 586, /* Islamic Republic of Pakistan */
|
||||
CTRY_PANAMA = 591, /* Panama */
|
||||
CTRY_PARAGUAY = 600, /* Paraguay */
|
||||
CTRY_PERU = 604, /* Peru */
|
||||
CTRY_PHILIPPINES = 608, /* Republic of the Philippines */
|
||||
CTRY_POLAND = 616, /* Poland */
|
||||
CTRY_PORTUGAL = 620, /* Portugal */
|
||||
CTRY_PUERTO_RICO = 630, /* Puerto Rico */
|
||||
CTRY_QATAR = 634, /* Qatar */
|
||||
CTRY_ROMANIA = 642, /* Romania */
|
||||
CTRY_RUSSIA = 643, /* Russia */
|
||||
CTRY_SAUDI_ARABIA = 682, /* Saudi Arabia */
|
||||
CTRY_SINGAPORE = 702, /* Singapore */
|
||||
CTRY_SLOVAKIA = 703, /* Slovak Republic */
|
||||
CTRY_SLOVENIA = 705, /* Slovenia */
|
||||
CTRY_SOUTH_AFRICA = 710, /* South Africa */
|
||||
CTRY_SPAIN = 724, /* Spain */
|
||||
CTRY_SRI_LANKA = 728, /* Sri Lanka */
|
||||
CTRY_SWEDEN = 752, /* Sweden */
|
||||
CTRY_SWITZERLAND = 756, /* Switzerland */
|
||||
CTRY_SYRIA = 760, /* Syria */
|
||||
CTRY_TAIWAN = 158, /* Taiwan */
|
||||
CTRY_THAILAND = 764, /* Thailand */
|
||||
CTRY_TRINIDAD_Y_TOBAGO = 780, /* Trinidad y Tobago */
|
||||
CTRY_TUNISIA = 788, /* Tunisia */
|
||||
CTRY_TURKEY = 792, /* Turkey */
|
||||
CTRY_UAE = 784, /* U.A.E. */
|
||||
CTRY_UKRAINE = 804, /* Ukraine */
|
||||
CTRY_UNITED_KINGDOM = 826, /* United Kingdom */
|
||||
CTRY_UNITED_STATES = 840, /* United States */
|
||||
CTRY_URUGUAY = 858, /* Uruguay */
|
||||
CTRY_UZBEKISTAN = 860, /* Uzbekistan */
|
||||
CTRY_VENEZUELA = 862, /* Venezuela */
|
||||
CTRY_VIET_NAM = 704, /* Viet Nam */
|
||||
CTRY_YEMEN = 887, /* Yemen */
|
||||
CTRY_ZIMBABWE = 716, /* Zimbabwe */
|
||||
};
|
||||
|
||||
#define IEEE80211_CHANNELS_2GHZ_MIN 2412 /* 2GHz channel 1 */
|
||||
#define IEEE80211_CHANNELS_2GHZ_MAX 2732 /* 2GHz channel 26 */
|
||||
#define IEEE80211_CHANNELS_5GHZ_MIN 5005 /* 5GHz channel 1 */
|
||||
#define IEEE80211_CHANNELS_5GHZ_MAX 6100 /* 5GHz channel 220 */
|
||||
|
||||
struct ath5k_regchannel {
|
||||
u16 chan;
|
||||
enum ath5k_regdom domain;
|
||||
u32 mode;
|
||||
};
|
||||
|
||||
#define IEEE80211_CHANNELS_2GHZ { \
|
||||
/*2412*/ { 1, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2417*/ { 2, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2422*/ { 3, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2427*/ { 4, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2432*/ { 5, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2437*/ { 6, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2442*/ { 7, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2447*/ { 8, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2452*/ { 9, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2457*/ { 10, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2462*/ { 11, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2467*/ { 12, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2472*/ { 13, DMN_APLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
\
|
||||
/*2432*/ { 5, DMN_ETSIB, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2437*/ { 6, DMN_ETSIB, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \
|
||||
/*2442*/ { 7, DMN_ETSIB, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
\
|
||||
/*2412*/ { 1, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2417*/ { 2, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2422*/ { 3, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2427*/ { 4, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2432*/ { 5, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2437*/ { 6, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \
|
||||
/*2442*/ { 7, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2447*/ { 8, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2452*/ { 9, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2457*/ { 10, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2462*/ { 11, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2467*/ { 12, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2472*/ { 13, DMN_ETSIC, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
\
|
||||
/*2412*/ { 1, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2417*/ { 2, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2422*/ { 3, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2427*/ { 4, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2432*/ { 5, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2437*/ { 6, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \
|
||||
/*2442*/ { 7, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2447*/ { 8, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2452*/ { 9, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2457*/ { 10, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2462*/ { 11, DMN_FCCA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
\
|
||||
/*2412*/ { 1, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2417*/ { 2, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2422*/ { 3, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2427*/ { 4, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2432*/ { 5, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2437*/ { 6, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2442*/ { 7, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2447*/ { 8, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2452*/ { 9, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2457*/ { 10, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2462*/ { 11, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2467*/ { 12, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2472*/ { 13, DMN_MKKA, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2484*/ { 14, DMN_MKKA, CHANNEL_CCK }, \
|
||||
\
|
||||
/*2412*/ { 1, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2417*/ { 2, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2422*/ { 3, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2427*/ { 4, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2432*/ { 5, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2437*/ { 6, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM|CHANNEL_TURBO }, \
|
||||
/*2442*/ { 7, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2447*/ { 8, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2452*/ { 9, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2457*/ { 10, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2462*/ { 11, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2467*/ { 12, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
/*2472*/ { 13, DMN_WORLD, CHANNEL_CCK|CHANNEL_OFDM }, \
|
||||
}
|
||||
|
||||
#define IEEE80211_CHANNELS_5GHZ { \
|
||||
/*5745*/ { 149, DMN_APL1, CHANNEL_OFDM }, \
|
||||
/*5765*/ { 153, DMN_APL1, CHANNEL_OFDM }, \
|
||||
/*5785*/ { 157, DMN_APL1, CHANNEL_OFDM }, \
|
||||
/*5805*/ { 161, DMN_APL1, CHANNEL_OFDM }, \
|
||||
/*5825*/ { 165, DMN_APL1, CHANNEL_OFDM }, \
|
||||
\
|
||||
/*5745*/ { 149, DMN_APL2, CHANNEL_OFDM }, \
|
||||
/*5765*/ { 153, DMN_APL2, CHANNEL_OFDM }, \
|
||||
/*5785*/ { 157, DMN_APL2, CHANNEL_OFDM }, \
|
||||
/*5805*/ { 161, DMN_APL2, CHANNEL_OFDM }, \
|
||||
\
|
||||
/*5280*/ { 56, DMN_APL3, CHANNEL_OFDM }, \
|
||||
/*5300*/ { 60, DMN_APL3, CHANNEL_OFDM }, \
|
||||
/*5320*/ { 64, DMN_APL3, CHANNEL_OFDM }, \
|
||||
/*5745*/ { 149, DMN_APL3, CHANNEL_OFDM }, \
|
||||
/*5765*/ { 153, DMN_APL3, CHANNEL_OFDM }, \
|
||||
/*5785*/ { 157, DMN_APL3, CHANNEL_OFDM }, \
|
||||
/*5805*/ { 161, DMN_APL3, CHANNEL_OFDM }, \
|
||||
\
|
||||
/*5180*/ { 36, DMN_APL4, CHANNEL_OFDM }, \
|
||||
/*5200*/ { 40, DMN_APL4, CHANNEL_OFDM }, \
|
||||
/*5220*/ { 44, DMN_APL4, CHANNEL_OFDM }, \
|
||||
/*5240*/ { 48, DMN_APL4, CHANNEL_OFDM }, \
|
||||
/*5745*/ { 149, DMN_APL4, CHANNEL_OFDM }, \
|
||||
/*5765*/ { 153, DMN_APL4, CHANNEL_OFDM }, \
|
||||
/*5785*/ { 157, DMN_APL4, CHANNEL_OFDM }, \
|
||||
/*5805*/ { 161, DMN_APL4, CHANNEL_OFDM }, \
|
||||
/*5825*/ { 165, DMN_APL4, CHANNEL_OFDM }, \
|
||||
\
|
||||
/*5745*/ { 149, DMN_APL5, CHANNEL_OFDM }, \
|
||||
/*5765*/ { 153, DMN_APL5, CHANNEL_OFDM }, \
|
||||
/*5785*/ { 157, DMN_APL5, CHANNEL_OFDM }, \
|
||||
/*5805*/ { 161, DMN_APL5, CHANNEL_OFDM }, \
|
||||
/*5825*/ { 165, DMN_APL5, CHANNEL_OFDM }, \
|
||||
\
|
||||
/*5180*/ { 36, DMN_ETSI1, CHANNEL_OFDM }, \
|
||||
/*5200*/ { 40, DMN_ETSI1, CHANNEL_OFDM }, \
|
||||
/*5220*/ { 44, DMN_ETSI1, CHANNEL_OFDM }, \
|
||||
/*5240*/ { 48, DMN_ETSI1, CHANNEL_OFDM }, \
|
||||
/*5260*/ { 52, DMN_ETSI1, CHANNEL_OFDM }, \
|
||||
/*5280*/ { 56, DMN_ETSI1, CHANNEL_OFDM }, \
|
||||
/*5300*/ { 60, DMN_ETSI1, CHANNEL_OFDM }, \
|
||||
/*5320*/ { 64, DMN_ETSI1, CHANNEL_OFDM }, \
|
||||
/*5500*/ { 100, DMN_ETSI1, CHANNEL_OFDM }, \
|
||||
/*5520*/ { 104, DMN_ETSI1, CHANNEL_OFDM }, \
|
||||
/*5540*/ { 108, DMN_ETSI1, CHANNEL_OFDM }, \
|
||||
/*5560*/ { 112, DMN_ETSI1, CHANNEL_OFDM }, \
|
||||
/*5580*/ { 116, DMN_ETSI1, CHANNEL_OFDM }, \
|
||||
/*5600*/ { 120, DMN_ETSI1, CHANNEL_OFDM }, \
|
||||
/*5620*/ { 124, DMN_ETSI1, CHANNEL_OFDM }, \
|
||||
/*5640*/ { 128, DMN_ETSI1, CHANNEL_OFDM }, \
|
||||
/*5660*/ { 132, DMN_ETSI1, CHANNEL_OFDM }, \
|
||||
/*5680*/ { 136, DMN_ETSI1, CHANNEL_OFDM }, \
|
||||
/*5700*/ { 140, DMN_ETSI1, CHANNEL_OFDM }, \
|
||||
\
|
||||
/*5180*/ { 36, DMN_ETSI2, CHANNEL_OFDM }, \
|
||||
/*5200*/ { 40, DMN_ETSI2, CHANNEL_OFDM }, \
|
||||
/*5220*/ { 44, DMN_ETSI2, CHANNEL_OFDM }, \
|
||||
/*5240*/ { 48, DMN_ETSI2, CHANNEL_OFDM }, \
|
||||
\
|
||||
/*5180*/ { 36, DMN_ETSI3, CHANNEL_OFDM }, \
|
||||
/*5200*/ { 40, DMN_ETSI3, CHANNEL_OFDM }, \
|
||||
/*5220*/ { 44, DMN_ETSI3, CHANNEL_OFDM }, \
|
||||
/*5240*/ { 48, DMN_ETSI3, CHANNEL_OFDM }, \
|
||||
/*5260*/ { 52, DMN_ETSI3, CHANNEL_OFDM }, \
|
||||
/*5280*/ { 56, DMN_ETSI3, CHANNEL_OFDM }, \
|
||||
/*5300*/ { 60, DMN_ETSI3, CHANNEL_OFDM }, \
|
||||
/*5320*/ { 64, DMN_ETSI3, CHANNEL_OFDM }, \
|
||||
\
|
||||
/*5180*/ { 36, DMN_ETSI4, CHANNEL_OFDM }, \
|
||||
/*5200*/ { 40, DMN_ETSI4, CHANNEL_OFDM }, \
|
||||
/*5220*/ { 44, DMN_ETSI4, CHANNEL_OFDM }, \
|
||||
/*5240*/ { 48, DMN_ETSI4, CHANNEL_OFDM }, \
|
||||
/*5260*/ { 52, DMN_ETSI4, CHANNEL_OFDM }, \
|
||||
/*5280*/ { 56, DMN_ETSI4, CHANNEL_OFDM }, \
|
||||
/*5300*/ { 60, DMN_ETSI4, CHANNEL_OFDM }, \
|
||||
/*5320*/ { 64, DMN_ETSI4, CHANNEL_OFDM }, \
|
||||
\
|
||||
/*5180*/ { 36, DMN_ETSI5, CHANNEL_OFDM }, \
|
||||
/*5200*/ { 40, DMN_ETSI5, CHANNEL_OFDM }, \
|
||||
/*5220*/ { 44, DMN_ETSI5, CHANNEL_OFDM }, \
|
||||
/*5240*/ { 48, DMN_ETSI5, CHANNEL_OFDM }, \
|
||||
\
|
||||
/*5180*/ { 36, DMN_ETSI6, CHANNEL_OFDM }, \
|
||||
/*5200*/ { 40, DMN_ETSI6, CHANNEL_OFDM }, \
|
||||
/*5220*/ { 44, DMN_ETSI6, CHANNEL_OFDM }, \
|
||||
/*5240*/ { 48, DMN_ETSI6, CHANNEL_OFDM }, \
|
||||
/*5260*/ { 52, DMN_ETSI6, CHANNEL_OFDM }, \
|
||||
/*5280*/ { 56, DMN_ETSI6, CHANNEL_OFDM }, \
|
||||
/*5500*/ { 100, DMN_ETSI6, CHANNEL_OFDM }, \
|
||||
/*5520*/ { 104, DMN_ETSI6, CHANNEL_OFDM }, \
|
||||
/*5540*/ { 108, DMN_ETSI6, CHANNEL_OFDM }, \
|
||||
/*5560*/ { 112, DMN_ETSI6, CHANNEL_OFDM }, \
|
||||
/*5580*/ { 116, DMN_ETSI6, CHANNEL_OFDM }, \
|
||||
/*5600*/ { 120, DMN_ETSI6, CHANNEL_OFDM }, \
|
||||
/*5620*/ { 124, DMN_ETSI6, CHANNEL_OFDM }, \
|
||||
/*5640*/ { 128, DMN_ETSI6, CHANNEL_OFDM }, \
|
||||
/*5660*/ { 132, DMN_ETSI6, CHANNEL_OFDM }, \
|
||||
/*5680*/ { 136, DMN_ETSI6, CHANNEL_OFDM }, \
|
||||
/*5700*/ { 140, DMN_ETSI6, CHANNEL_OFDM }, \
|
||||
\
|
||||
/*5180*/ { 36, DMN_FCC1, CHANNEL_OFDM }, \
|
||||
/*5200*/ { 40, DMN_FCC1, CHANNEL_OFDM }, \
|
||||
/*5210*/ { 42, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \
|
||||
/*5220*/ { 44, DMN_FCC1, CHANNEL_OFDM }, \
|
||||
/*5240*/ { 48, DMN_FCC1, CHANNEL_OFDM }, \
|
||||
/*5250*/ { 50, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \
|
||||
/*5260*/ { 52, DMN_FCC1, CHANNEL_OFDM }, \
|
||||
/*5280*/ { 56, DMN_FCC1, CHANNEL_OFDM }, \
|
||||
/*5290*/ { 58, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \
|
||||
/*5300*/ { 60, DMN_FCC1, CHANNEL_OFDM }, \
|
||||
/*5320*/ { 64, DMN_FCC1, CHANNEL_OFDM }, \
|
||||
/*5745*/ { 149, DMN_FCC1, CHANNEL_OFDM }, \
|
||||
/*5760*/ { 152, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \
|
||||
/*5765*/ { 153, DMN_FCC1, CHANNEL_OFDM }, \
|
||||
/*5785*/ { 157, DMN_FCC1, CHANNEL_OFDM }, \
|
||||
/*5800*/ { 160, DMN_FCC1, CHANNEL_OFDM|CHANNEL_TURBO }, \
|
||||
/*5805*/ { 161, DMN_FCC1, CHANNEL_OFDM }, \
|
||||
/*5825*/ { 165, DMN_FCC1, CHANNEL_OFDM }, \
|
||||
\
|
||||
/*5180*/ { 36, DMN_FCC2, CHANNEL_OFDM }, \
|
||||
/*5200*/ { 40, DMN_FCC2, CHANNEL_OFDM }, \
|
||||
/*5220*/ { 44, DMN_FCC2, CHANNEL_OFDM }, \
|
||||
/*5240*/ { 48, DMN_FCC2, CHANNEL_OFDM }, \
|
||||
/*5260*/ { 52, DMN_FCC2, CHANNEL_OFDM }, \
|
||||
/*5280*/ { 56, DMN_FCC2, CHANNEL_OFDM }, \
|
||||
/*5300*/ { 60, DMN_FCC2, CHANNEL_OFDM }, \
|
||||
/*5320*/ { 64, DMN_FCC2, CHANNEL_OFDM }, \
|
||||
/*5745*/ { 149, DMN_FCC2, CHANNEL_OFDM }, \
|
||||
/*5765*/ { 153, DMN_FCC2, CHANNEL_OFDM }, \
|
||||
/*5785*/ { 157, DMN_FCC2, CHANNEL_OFDM }, \
|
||||
/*5805*/ { 161, DMN_FCC2, CHANNEL_OFDM }, \
|
||||
/*5825*/ { 165, DMN_FCC2, CHANNEL_OFDM }, \
|
||||
\
|
||||
/*5180*/ { 36, DMN_FCC3, CHANNEL_OFDM }, \
|
||||
/*5200*/ { 40, DMN_FCC3, CHANNEL_OFDM }, \
|
||||
/*5210*/ { 42, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \
|
||||
/*5220*/ { 44, DMN_FCC3, CHANNEL_OFDM }, \
|
||||
/*5240*/ { 48, DMN_FCC3, CHANNEL_OFDM }, \
|
||||
/*5250*/ { 50, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \
|
||||
/*5260*/ { 52, DMN_FCC3, CHANNEL_OFDM }, \
|
||||
/*5280*/ { 56, DMN_FCC3, CHANNEL_OFDM }, \
|
||||
/*5290*/ { 58, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \
|
||||
/*5300*/ { 60, DMN_FCC3, CHANNEL_OFDM }, \
|
||||
/*5320*/ { 64, DMN_FCC3, CHANNEL_OFDM }, \
|
||||
/*5500*/ { 100, DMN_FCC3, CHANNEL_OFDM }, \
|
||||
/*5520*/ { 104, DMN_FCC3, CHANNEL_OFDM }, \
|
||||
/*5540*/ { 108, DMN_FCC3, CHANNEL_OFDM }, \
|
||||
/*5560*/ { 112, DMN_FCC3, CHANNEL_OFDM }, \
|
||||
/*5580*/ { 116, DMN_FCC3, CHANNEL_OFDM }, \
|
||||
/*5600*/ { 120, DMN_FCC3, CHANNEL_OFDM }, \
|
||||
/*5620*/ { 124, DMN_FCC3, CHANNEL_OFDM }, \
|
||||
/*5640*/ { 128, DMN_FCC3, CHANNEL_OFDM }, \
|
||||
/*5660*/ { 132, DMN_FCC3, CHANNEL_OFDM }, \
|
||||
/*5680*/ { 136, DMN_FCC3, CHANNEL_OFDM }, \
|
||||
/*5700*/ { 140, DMN_FCC3, CHANNEL_OFDM }, \
|
||||
/*5745*/ { 149, DMN_FCC3, CHANNEL_OFDM }, \
|
||||
/*5760*/ { 152, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \
|
||||
/*5765*/ { 153, DMN_FCC3, CHANNEL_OFDM }, \
|
||||
/*5785*/ { 157, DMN_FCC3, CHANNEL_OFDM }, \
|
||||
/*5800*/ { 160, DMN_FCC3, CHANNEL_OFDM|CHANNEL_TURBO }, \
|
||||
/*5805*/ { 161, DMN_FCC3, CHANNEL_OFDM }, \
|
||||
/*5825*/ { 165, DMN_FCC3, CHANNEL_OFDM }, \
|
||||
\
|
||||
/*5170*/ { 34, DMN_MKK1, CHANNEL_OFDM }, \
|
||||
/*5190*/ { 38, DMN_MKK1, CHANNEL_OFDM }, \
|
||||
/*5210*/ { 42, DMN_MKK1, CHANNEL_OFDM }, \
|
||||
/*5230*/ { 46, DMN_MKK1, CHANNEL_OFDM }, \
|
||||
\
|
||||
/*5040*/ { 8, DMN_MKK2, CHANNEL_OFDM }, \
|
||||
/*5060*/ { 12, DMN_MKK2, CHANNEL_OFDM }, \
|
||||
/*5080*/ { 16, DMN_MKK2, CHANNEL_OFDM }, \
|
||||
/*5170*/ { 34, DMN_MKK2, CHANNEL_OFDM }, \
|
||||
/*5190*/ { 38, DMN_MKK2, CHANNEL_OFDM }, \
|
||||
/*5210*/ { 42, DMN_MKK2, CHANNEL_OFDM }, \
|
||||
/*5230*/ { 46, DMN_MKK2, CHANNEL_OFDM }, \
|
||||
\
|
||||
/*5180*/ { 36, DMN_WORLD, CHANNEL_OFDM }, \
|
||||
/*5200*/ { 40, DMN_WORLD, CHANNEL_OFDM }, \
|
||||
/*5220*/ { 44, DMN_WORLD, CHANNEL_OFDM }, \
|
||||
/*5240*/ { 48, DMN_WORLD, CHANNEL_OFDM }, \
|
||||
}
|
||||
|
||||
enum ath5k_regdom ath5k_regdom2flag(enum ath5k_regdom, u16);
|
||||
u16 ath5k_regdom_from_ieee(enum ath5k_regdom ieee);
|
||||
enum ath5k_regdom ath5k_regdom_to_ieee(u16 regdomain);
|
||||
|
||||
#endif
|
||||
Загрузка…
Ссылка в новой задаче