octeontx2-pf: cn10k: Add mbox support for CN10K
Firmware allocates memory regions for PFs and VFs in DRAM. The PFs memory region is used for AF-PF and PF-VF mailbox. This mbox facilitate communication between AF-PF and PF-VF. On CN10K platform: The DRAM region allocated to PF is enumerated as PF BAR4 memory. PF BAR4 contains AF-PF mbox region followed by its VFs mbox region. AF-PF mbox region base address is configured at RVU_AF_PFX_BAR4_ADDR PF-VF mailbox base address is configured at RVU_PF(x)_VF_MBOX_ADDR = RVU_AF_PF()_BAR4_ADDR+64KB. PF access its mbox region via BAR4, whereas VF accesses PF-VF DRAM mailboxes via BAR2 indirect access. On CN9XX platform: Mailbox region in DRAM is divided into two parts AF-PF mbox region and PF-VF mbox region i.e all PFs mbox region is contiguous similarly all VFs. The base address of the AF-PF mbox region is configured at RVU_AF_PF_BAR4_ADDR. AF-PF1 mbox address can be calculated as RVU_AF_PF_BAR4_ADDR * mbox size. The base address of PF-VF mbox region for each PF is configure at RVU_AF_PF(0..15)_VF_BAR4_ADDR.PF access its mbox region via BAR4 and its VF mbox regions from RVU_PF_VF_BAR4_ADDR register, whereas VF access its mbox region via BAR4. This patch changes mbox initialization to support both CN9XX and CN10K platform. The patch also adds new hw_cap flag to setting hw features like TSO etc and removes platform specific name from the PF/VF driver name to make it appropriate for all supported platforms This patch also removes platform specific name from the PF/VF driver name to make it appropriate for all supported platforms Signed-off-by: Subbaraya Sundeep <sbhatta@marvell.com> Signed-off-by: Geetha sowjanya <gakula@marvell.com> Signed-off-by: Sunil Goutham <sgoutham@marvell.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Subbaraya Sundeep
David S. Miller
Родитель
98c5611163
Коммит
facede8209
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@ -3,11 +3,11 @@
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# Makefile for Marvell's OcteonTX2 ethernet device drivers
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#
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obj-$(CONFIG_OCTEONTX2_PF) += octeontx2_nicpf.o
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obj-$(CONFIG_OCTEONTX2_VF) += octeontx2_nicvf.o
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obj-$(CONFIG_OCTEONTX2_PF) += rvu_nicpf.o
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obj-$(CONFIG_OCTEONTX2_VF) += rvu_nicvf.o
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octeontx2_nicpf-y := otx2_pf.o otx2_common.o otx2_txrx.o otx2_ethtool.o \
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rvu_nicpf-y := otx2_pf.o otx2_common.o otx2_txrx.o otx2_ethtool.o \
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otx2_ptp.o otx2_flows.o
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octeontx2_nicvf-y := otx2_vf.o
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rvu_nicvf-y := otx2_vf.o
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ccflags-y += -I$(srctree)/drivers/net/ethernet/marvell/octeontx2/af
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@ -190,7 +190,6 @@ struct otx2_hw {
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u8 lso_tsov6_idx;
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u8 lso_udpv4_idx;
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u8 lso_udpv6_idx;
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u8 hw_tso;
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/* MSI-X */
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u8 cint_cnt; /* CQ interrupt count */
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@ -208,6 +207,9 @@ struct otx2_hw {
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u64 cgx_fec_uncorr_blks;
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u8 cgx_links; /* No. of CGX links present in HW */
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u8 lbk_links; /* No. of LBK links present in HW */
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#define HW_TSO BIT_ULL(0)
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#define CN10K_MBOX BIT_ULL(1)
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unsigned long cap_flag;
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};
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struct otx2_vf_config {
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@ -341,6 +343,25 @@ static inline bool is_96xx_B0(struct pci_dev *pdev)
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(pdev->subsystem_device == PCI_SUBSYS_DEVID_96XX_RVU_PFVF);
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}
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/* REVID for PCIe devices.
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* Bits 0..1: minor pass, bit 3..2: major pass
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* bits 7..4: midr id
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*/
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#define PCI_REVISION_ID_96XX 0x00
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#define PCI_REVISION_ID_95XX 0x10
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#define PCI_REVISION_ID_LOKI 0x20
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#define PCI_REVISION_ID_98XX 0x30
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#define PCI_REVISION_ID_95XXMM 0x40
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static inline bool is_dev_otx2(struct pci_dev *pdev)
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{
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u8 midr = pdev->revision & 0xF0;
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return (midr == PCI_REVISION_ID_96XX || midr == PCI_REVISION_ID_95XX ||
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midr == PCI_REVISION_ID_LOKI || midr == PCI_REVISION_ID_98XX ||
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midr == PCI_REVISION_ID_95XXMM);
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}
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static inline void otx2_setup_dev_hw_settings(struct otx2_nic *pfvf)
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{
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struct otx2_hw *hw = &pfvf->hw;
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@ -349,10 +370,10 @@ static inline void otx2_setup_dev_hw_settings(struct otx2_nic *pfvf)
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pfvf->hw.cq_ecount_wait = CQ_CQE_THRESH_DEFAULT;
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pfvf->hw.cq_qcount_wait = CQ_QCOUNT_DEFAULT;
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hw->hw_tso = true;
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__set_bit(HW_TSO, &hw->cap_flag);
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if (is_96xx_A0(pfvf->pdev)) {
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hw->hw_tso = false;
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__clear_bit(HW_TSO, &hw->cap_flag);
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/* Time based irq coalescing is not supported */
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pfvf->hw.cq_qcount_wait = 0x0;
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@ -363,6 +384,8 @@ static inline void otx2_setup_dev_hw_settings(struct otx2_nic *pfvf)
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pfvf->hw.rq_skid = 600;
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pfvf->qset.rqe_cnt = Q_COUNT(Q_SIZE_1K);
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}
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if (!is_dev_otx2(pfvf->pdev))
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__set_bit(CN10K_MBOX, &hw->cap_flag);
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}
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/* Register read/write APIs */
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@ -24,8 +24,8 @@
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#include "otx2_ptp.h"
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#include <rvu_trace.h>
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#define DRV_NAME "octeontx2-nicpf"
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#define DRV_STRING "Marvell OcteonTX2 NIC Physical Function Driver"
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#define DRV_NAME "rvu_nicpf"
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#define DRV_STRING "Marvell RVU NIC Physical Function Driver"
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/* Supported devices */
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static const struct pci_device_id otx2_pf_id_table[] = {
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@ -585,9 +585,17 @@ static int otx2_pfvf_mbox_init(struct otx2_nic *pf, int numvfs)
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if (!pf->mbox_pfvf_wq)
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return -ENOMEM;
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base = readq((void __iomem *)((u64)pf->reg_base + RVU_PF_VF_BAR4_ADDR));
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hwbase = ioremap_wc(base, MBOX_SIZE * pf->total_vfs);
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/* On CN10K platform, PF <-> VF mailbox region follows after
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* PF <-> AF mailbox region.
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*/
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if (test_bit(CN10K_MBOX, &pf->hw.cap_flag))
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base = pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM) +
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MBOX_SIZE;
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else
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base = readq((void __iomem *)((u64)pf->reg_base +
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RVU_PF_VF_BAR4_ADDR));
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hwbase = ioremap_wc(base, MBOX_SIZE * pf->total_vfs);
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if (!hwbase) {
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err = -ENOMEM;
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goto free_wq;
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@ -1042,7 +1050,7 @@ static int otx2_pfaf_mbox_init(struct otx2_nic *pf)
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* device memory to allow unaligned accesses.
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*/
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hwbase = ioremap_wc(pci_resource_start(pf->pdev, PCI_MBOX_BAR_NUM),
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pci_resource_len(pf->pdev, PCI_MBOX_BAR_NUM));
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MBOX_SIZE);
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if (!hwbase) {
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dev_err(pf->dev, "Unable to map PFAF mailbox region\n");
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err = -ENOMEM;
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@ -44,6 +44,8 @@
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#define RVU_PF_MSIX_VECX_ADDR(a) (0x000 | (a) << 4)
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#define RVU_PF_MSIX_VECX_CTL(a) (0x008 | (a) << 4)
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#define RVU_PF_MSIX_PBAX(a) (0xF0000 | (a) << 3)
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#define RVU_PF_VF_MBOX_ADDR (0xC40)
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#define RVU_PF_LMTLINE_ADDR (0xC48)
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/* RVU VF registers */
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#define RVU_VF_VFPF_MBOX0 (0x00000)
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@ -57,6 +59,7 @@
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#define RVU_VF_MSIX_VECX_ADDR(a) (0x000 | (a) << 4)
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#define RVU_VF_MSIX_VECX_CTL(a) (0x008 | (a) << 4)
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#define RVU_VF_MSIX_PBAX(a) (0xF0000 | (a) << 3)
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#define RVU_VF_MBOX_REGION (0xC0000)
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#define RVU_FUNC_BLKADDR_SHIFT 20
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#define RVU_FUNC_BLKADDR_MASK 0x1FULL
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@ -805,8 +805,6 @@ static bool is_hw_tso_supported(struct otx2_nic *pfvf,
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{
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int payload_len, last_seg_size;
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if (!pfvf->hw.hw_tso)
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return false;
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/* HW has an issue due to which when the payload of the last LSO
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* segment is shorter than 16 bytes, some header fields may not
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@ -820,6 +818,9 @@ static bool is_hw_tso_supported(struct otx2_nic *pfvf,
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if (last_seg_size && last_seg_size < 16)
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return false;
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if (!test_bit(HW_TSO, &pfvf->hw.cap_flag))
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return false;
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return true;
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}
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@ -8,8 +8,8 @@
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#include "otx2_common.h"
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#include "otx2_reg.h"
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#define DRV_NAME "octeontx2-nicvf"
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#define DRV_STRING "Marvell OcteonTX2 NIC Virtual Function Driver"
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#define DRV_NAME "rvu_nicvf"
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#define DRV_STRING "Marvell RVU NIC Virtual Function Driver"
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static const struct pci_device_id otx2_vf_id_table[] = {
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{ PCI_DEVICE(PCI_VENDOR_ID_CAVIUM, PCI_DEVID_OCTEONTX2_RVU_AFVF) },
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@ -277,7 +277,7 @@ static void otx2vf_vfaf_mbox_destroy(struct otx2_nic *vf)
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vf->mbox_wq = NULL;
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}
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if (mbox->mbox.hwbase)
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if (mbox->mbox.hwbase && !test_bit(CN10K_MBOX, &vf->hw.cap_flag))
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iounmap((void __iomem *)mbox->mbox.hwbase);
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otx2_mbox_destroy(&mbox->mbox);
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@ -297,16 +297,25 @@ static int otx2vf_vfaf_mbox_init(struct otx2_nic *vf)
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if (!vf->mbox_wq)
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return -ENOMEM;
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/* Mailbox is a reserved memory (in RAM) region shared between
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* admin function (i.e PF0) and this VF, shouldn't be mapped as
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* device memory to allow unaligned accesses.
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*/
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hwbase = ioremap_wc(pci_resource_start(vf->pdev, PCI_MBOX_BAR_NUM),
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pci_resource_len(vf->pdev, PCI_MBOX_BAR_NUM));
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if (!hwbase) {
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dev_err(vf->dev, "Unable to map VFAF mailbox region\n");
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err = -ENOMEM;
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goto exit;
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if (test_bit(CN10K_MBOX, &vf->hw.cap_flag)) {
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/* For cn10k platform, VF mailbox region is in its BAR2
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* register space
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*/
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hwbase = vf->reg_base + RVU_VF_MBOX_REGION;
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} else {
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/* Mailbox is a reserved memory (in RAM) region shared between
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* admin function (i.e PF0) and this VF, shouldn't be mapped as
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* device memory to allow unaligned accesses.
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*/
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hwbase = ioremap_wc(pci_resource_start(vf->pdev,
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PCI_MBOX_BAR_NUM),
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pci_resource_len(vf->pdev,
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PCI_MBOX_BAR_NUM));
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if (!hwbase) {
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dev_err(vf->dev, "Unable to map VFAF mailbox region\n");
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err = -ENOMEM;
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goto exit;
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}
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}
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err = otx2_mbox_init(&mbox->mbox, hwbase, vf->pdev, vf->reg_base,
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@ -329,6 +338,8 @@ static int otx2vf_vfaf_mbox_init(struct otx2_nic *vf)
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return 0;
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exit:
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if (hwbase && !test_bit(CN10K_MBOX, &vf->hw.cap_flag))
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iounmap(hwbase);
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destroy_workqueue(vf->mbox_wq);
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return err;
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}
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