DMA: PL08x: fix infinite wait when terminating transfers
If we try to pause a channel when terminating a transfer, we could end up spinning for it to become inactive indefinitely, and can result in an uninterruptible wait requiring a reset to recover from. Terminating a transfer is supposed to take effect immediately, but may result in data loss. To make this clear, rename the function to pl08x_terminate_phy_chan(). Also, make sure it is always consistently called - with the spinlock held and IRQs disabled, and ensure that the TC and ERR interrupt status is always cleared. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> Acked-by: Linus Walleij <linus.walleij@stericsson.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
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@ -267,19 +267,24 @@ static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
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}
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/* Stops the channel */
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static void pl08x_stop_phy_chan(struct pl08x_phy_chan *ch)
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/*
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* pl08x_terminate_phy_chan() stops the channel, clears the FIFO and
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* clears any pending interrupt status. This should not be used for
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* an on-going transfer, but as a method of shutting down a channel
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* (eg, when it's no longer used) or terminating a transfer.
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*/
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static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x,
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struct pl08x_phy_chan *ch)
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{
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u32 val;
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u32 val = readl(ch->base + PL080_CH_CONFIG);
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pl08x_pause_phy_chan(ch);
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val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK |
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PL080_CONFIG_TC_IRQ_MASK);
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/* Disable channel */
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val = readl(ch->base + PL080_CH_CONFIG);
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val &= ~PL080_CONFIG_ENABLE;
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val &= ~PL080_CONFIG_ERR_IRQ_MASK;
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val &= ~PL080_CONFIG_TC_IRQ_MASK;
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writel(val, ch->base + PL080_CH_CONFIG);
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writel(1 << ch->id, pl08x->base + PL080_ERR_CLEAR);
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writel(1 << ch->id, pl08x->base + PL080_TC_CLEAR);
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}
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static inline u32 get_bytes_in_cctl(u32 cctl)
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@ -404,13 +409,12 @@ static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x,
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{
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unsigned long flags;
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spin_lock_irqsave(&ch->lock, flags);
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/* Stop the channel and clear its interrupts */
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pl08x_stop_phy_chan(ch);
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writel((1 << ch->id), pl08x->base + PL080_ERR_CLEAR);
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writel((1 << ch->id), pl08x->base + PL080_TC_CLEAR);
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pl08x_terminate_phy_chan(pl08x, ch);
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/* Mark it as free */
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spin_lock_irqsave(&ch->lock, flags);
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ch->serving = NULL;
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spin_unlock_irqrestore(&ch->lock, flags);
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}
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@ -1449,7 +1453,7 @@ static int pl08x_control(struct dma_chan *chan, enum dma_ctrl_cmd cmd,
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plchan->state = PL08X_CHAN_IDLE;
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if (plchan->phychan) {
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pl08x_stop_phy_chan(plchan->phychan);
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pl08x_terminate_phy_chan(pl08x, plchan->phychan);
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/*
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* Mark physical channel as free and free any slave
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