[POWERPC] 8xx: Infrastructure code cleanup.
1. Keep a global mpc8xx_immr mapping, rather than constantly creating temporary mappings. 2. Look for new fsl,cpm1 and fsl,cpm1-pic names. 3. Always reset the CPM when not using the udbg console; this is required in case the firmware initialized a device that is incompatible with one that the kernel is about to use. 4. Remove some superfluous casts and header includes. 5. Change a usage of IMAP_ADDR to get_immrbase(). 6. Use phys_addr_t, not uint, for dpram_pbase. 7. Various sparse-related fixes, such as __iomem annotations. 8. Remove mpc8xx_show_cpuinfo, which doesn't provide anything useful beyond the generic cpuinfo handler. 9. Move prototypes for 8xx support functions from board files to sysdev/commproc.h. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Scott Wood
Kumar Gala
Родитель
ccf0d68e83
Коммит
fb533d0c5a
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@ -10,57 +10,33 @@
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* bootup setup stuff..
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*/
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#include <linux/errno.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/mm.h>
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#include <linux/stddef.h>
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#include <linux/unistd.h>
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#include <linux/ptrace.h>
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#include <linux/slab.h>
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#include <linux/user.h>
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#include <linux/a.out.h>
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#include <linux/tty.h>
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#include <linux/major.h>
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#include <linux/interrupt.h>
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#include <linux/reboot.h>
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#include <linux/init.h>
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#include <linux/initrd.h>
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#include <linux/ioport.h>
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#include <linux/bootmem.h>
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#include <linux/seq_file.h>
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#include <linux/root_dev.h>
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#include <linux/time.h>
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#include <linux/rtc.h>
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#include <linux/fsl_devices.h>
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#include <asm/mmu.h>
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#include <asm/reg.h>
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#include <asm/io.h>
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#include <asm/pgtable.h>
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#include <asm/mpc8xx.h>
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#include <asm/8xx_immap.h>
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#include <asm/machdep.h>
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#include <asm/time.h>
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#include <asm/prom.h>
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#include <asm/fs_pd.h>
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#include <mm/mmu_decl.h>
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#include "sysdev/mpc8xx_pic.h"
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#include <sysdev/mpc8xx_pic.h>
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#include <sysdev/commproc.h>
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#ifdef CONFIG_PCMCIA_M8XX
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struct mpc8xx_pcmcia_ops m8xx_pcmcia_ops;
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#endif
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void m8xx_calibrate_decr(void);
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#ifdef CONFIG_8xx_WDT
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extern void m8xx_wdt_handler_install(bd_t *bp);
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#endif
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extern int cpm_pic_init(void);
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extern int cpm_get_irq(void);
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/* A place holder for time base interrupts, if they are ever enabled. */
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irqreturn_t timebase_interrupt(int irq, void * dev)
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static irqreturn_t timebase_interrupt(int irq, void *dev)
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{
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printk ("timebase_interrupt()\n");
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@ -77,7 +53,7 @@ static struct irqaction tbint_irqaction = {
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void __init __attribute__ ((weak))
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init_internal_rtc(void)
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{
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sit8xx_t *sys_tmr = (sit8xx_t *) immr_map(im_sit);
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sit8xx_t __iomem *sys_tmr = immr_map(im_sit);
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/* Disable the RTC one second and alarm interrupts. */
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clrbits16(&sys_tmr->sit_rtcsc, (RTCSC_SIE | RTCSC_ALE));
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@ -116,13 +92,13 @@ static int __init get_freq(char *name, unsigned long *val)
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void __init mpc8xx_calibrate_decr(void)
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{
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struct device_node *cpu;
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cark8xx_t *clk_r1;
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car8xx_t *clk_r2;
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sitk8xx_t *sys_tmr1;
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sit8xx_t *sys_tmr2;
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cark8xx_t __iomem *clk_r1;
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car8xx_t __iomem *clk_r2;
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sitk8xx_t __iomem *sys_tmr1;
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sit8xx_t __iomem *sys_tmr2;
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int irq, virq;
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clk_r1 = (cark8xx_t *) immr_map(im_clkrstk);
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clk_r1 = immr_map(im_clkrstk);
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/* Unlock the SCCR. */
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out_be32(&clk_r1->cark_sccrk, ~KAPWR_KEY);
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@ -130,7 +106,7 @@ void __init mpc8xx_calibrate_decr(void)
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immr_unmap(clk_r1);
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/* Force all 8xx processors to use divide by 16 processor clock. */
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clk_r2 = (car8xx_t *) immr_map(im_clkrst);
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clk_r2 = immr_map(im_clkrst);
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setbits32(&clk_r2->car_sccr, 0x02000000);
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immr_unmap(clk_r2);
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@ -164,7 +140,7 @@ void __init mpc8xx_calibrate_decr(void)
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* we guarantee the registers are locked, then we unlock them
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* for our use.
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*/
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sys_tmr1 = (sitk8xx_t *) immr_map(im_sitk);
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sys_tmr1 = immr_map(im_sitk);
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out_be32(&sys_tmr1->sitk_tbscrk, ~KAPWR_KEY);
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out_be32(&sys_tmr1->sitk_rtcsck, ~KAPWR_KEY);
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out_be32(&sys_tmr1->sitk_tbk, ~KAPWR_KEY);
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@ -184,20 +160,13 @@ void __init mpc8xx_calibrate_decr(void)
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virq= irq_of_parse_and_map(cpu, 0);
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irq = irq_map[virq].hwirq;
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sys_tmr2 = (sit8xx_t *) immr_map(im_sit);
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sys_tmr2 = immr_map(im_sit);
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out_be16(&sys_tmr2->sit_tbscr, ((1 << (7 - (irq/2))) << 8) |
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(TBSCR_TBF | TBSCR_TBE));
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immr_unmap(sys_tmr2);
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if (setup_irq(virq, &tbint_irqaction))
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panic("Could not allocate timer IRQ!");
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#ifdef CONFIG_8xx_WDT
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/* Install watchdog timer handler early because it might be
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* already enabled by the bootloader
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*/
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m8xx_wdt_handler_install(binfo);
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#endif
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}
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/* The RTC on the MPC8xx is an internal register.
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@ -207,12 +176,12 @@ void __init mpc8xx_calibrate_decr(void)
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int mpc8xx_set_rtc_time(struct rtc_time *tm)
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{
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sitk8xx_t *sys_tmr1;
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sit8xx_t *sys_tmr2;
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sitk8xx_t __iomem *sys_tmr1;
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sit8xx_t __iomem *sys_tmr2;
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int time;
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sys_tmr1 = (sitk8xx_t *) immr_map(im_sitk);
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sys_tmr2 = (sit8xx_t *) immr_map(im_sit);
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sys_tmr1 = immr_map(im_sitk);
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sys_tmr2 = immr_map(im_sit);
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time = mktime(tm->tm_year+1900, tm->tm_mon+1, tm->tm_mday,
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tm->tm_hour, tm->tm_min, tm->tm_sec);
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@ -228,7 +197,7 @@ int mpc8xx_set_rtc_time(struct rtc_time *tm)
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void mpc8xx_get_rtc_time(struct rtc_time *tm)
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{
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unsigned long data;
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sit8xx_t *sys_tmr = (sit8xx_t *) immr_map(im_sit);
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sit8xx_t __iomem *sys_tmr = immr_map(im_sit);
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/* Get time from the RTC. */
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data = in_be32(&sys_tmr->sit_rtc);
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@ -241,8 +210,7 @@ void mpc8xx_get_rtc_time(struct rtc_time *tm)
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void mpc8xx_restart(char *cmd)
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{
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__volatile__ unsigned char dummy;
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car8xx_t * clk_r = (car8xx_t *) immr_map(im_clkrst);
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car8xx_t __iomem *clk_r = immr_map(im_clkrst);
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local_irq_disable();
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@ -252,26 +220,8 @@ void mpc8xx_restart(char *cmd)
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*/
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mtmsr(mfmsr() & ~0x1000);
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dummy = in_8(&clk_r->res[0]);
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printk("Restart failed\n");
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while(1);
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}
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void mpc8xx_show_cpuinfo(struct seq_file *m)
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{
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struct device_node *root;
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uint memsize = total_memory;
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const char *model = "";
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seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
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root = of_find_node_by_path("/");
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if (root)
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model = of_get_property(root, "model", NULL);
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seq_printf(m, "Machine\t\t: %s\n", model);
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of_node_put(root);
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seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
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in_8(&clk_r->res[0]);
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panic("Restart failed\n");
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}
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static void cpm_cascade(unsigned int irq, struct irq_desc *desc)
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@ -29,9 +29,6 @@
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#define CFG_PHYDEV_ADDR ((uint)0xff0a0000)
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#define BCSR5 ((uint)(CFG_PHYDEV_ADDR + 0x300))
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#define IMAP_ADDR (get_immrbase())
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#define IMAP_SIZE ((uint)(64 * 1024))
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#define MPC8xx_CPM_OFFSET (0x9c0)
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#define CPM_MAP_ADDR (get_immrbase() + MPC8xx_CPM_OFFSET)
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#define CPM_IRQ_OFFSET 16 // for compability with cpm_uart driver
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@ -37,14 +37,7 @@
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#include <asm/fs_pd.h>
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#include <asm/prom.h>
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extern void cpm_reset(void);
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extern void mpc8xx_show_cpuinfo(struct seq_file*);
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extern void mpc8xx_restart(char *cmd);
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extern void mpc8xx_calibrate_decr(void);
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extern int mpc8xx_set_rtc_time(struct rtc_time *tm);
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extern void mpc8xx_get_rtc_time(struct rtc_time *tm);
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extern void m8xx_pic_init(void);
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extern unsigned int mpc8xx_get_irq(void);
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#include <sysdev/commproc.h>
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static void init_smc1_uart_ioports(struct fs_uart_platform_info* fpi);
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static void init_smc2_uart_ioports(struct fs_uart_platform_info* fpi);
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@ -277,7 +270,6 @@ define_machine(mpc86x_ads) {
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.probe = mpc86xads_probe,
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.setup_arch = mpc86xads_setup_arch,
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.init_IRQ = m8xx_pic_init,
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.show_cpuinfo = mpc8xx_show_cpuinfo,
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.get_irq = mpc8xx_get_irq,
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.restart = mpc8xx_restart,
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.calibrate_decr = mpc8xx_calibrate_decr,
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@ -29,9 +29,6 @@
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#define CFG_PHYDEV_ADDR ((uint)0xff0a0000)
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#define BCSR5 ((uint)(CFG_PHYDEV_ADDR + 0x300))
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#define IMAP_ADDR (get_immrbase())
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#define IMAP_SIZE ((uint)(64 * 1024))
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#define MPC8xx_CPM_OFFSET (0x9c0)
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#define CPM_MAP_ADDR (get_immrbase() + MPC8xx_CPM_OFFSET)
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#define CPM_IRQ_OFFSET 16 // for compability with cpm_uart driver
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@ -38,14 +38,7 @@
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#include <asm/fs_pd.h>
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#include <asm/prom.h>
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extern void cpm_reset(void);
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extern void mpc8xx_show_cpuinfo(struct seq_file *);
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extern void mpc8xx_restart(char *cmd);
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extern void mpc8xx_calibrate_decr(void);
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extern int mpc8xx_set_rtc_time(struct rtc_time *tm);
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extern void mpc8xx_get_rtc_time(struct rtc_time *tm);
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extern void m8xx_pic_init(void);
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extern unsigned int mpc8xx_get_irq(void);
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#include <sysdev/commproc.h>
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static void init_smc1_uart_ioports(struct fs_uart_platform_info *fpi);
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static void init_smc2_uart_ioports(struct fs_uart_platform_info *fpi);
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@ -430,7 +423,6 @@ define_machine(mpc885_ads)
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.probe = mpc885ads_probe,
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.setup_arch = mpc885ads_setup_arch,
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.init_IRQ = m8xx_pic_init,
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.show_cpuinfo = mpc8xx_show_cpuinfo,
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.get_irq = mpc8xx_get_irq,
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.restart = mpc8xx_restart,
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.calibrate_decr = mpc8xx_calibrate_decr,
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@ -47,8 +47,9 @@
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static void m8xx_cpm_dpinit(void);
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static uint host_buffer; /* One page of host buffer */
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static uint host_end; /* end + 1 */
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cpm8xx_t *cpmp; /* Pointer to comm processor space */
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cpic8xx_t *cpic_reg;
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cpm8xx_t __iomem *cpmp; /* Pointer to comm processor space */
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immap_t __iomem *mpc8xx_immr;
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static cpic8xx_t __iomem *cpic_reg;
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static struct irq_host *cpm_pic_host;
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@ -133,16 +134,19 @@ unsigned int cpm_pic_init(void)
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pr_debug("cpm_pic_init\n");
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np = of_find_compatible_node(NULL, "cpm-pic", "CPM");
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np = of_find_compatible_node(NULL, NULL, "fsl,cpm1-pic");
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if (np == NULL)
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np = of_find_compatible_node(NULL, "cpm-pic", "CPM");
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if (np == NULL) {
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printk(KERN_ERR "CPM PIC init: can not find cpm-pic node\n");
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return sirq;
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}
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ret = of_address_to_resource(np, 0, &res);
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if (ret)
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goto end;
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cpic_reg = (void *)ioremap(res.start, res.end - res.start + 1);
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cpic_reg = ioremap(res.start, res.end - res.start + 1);
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if (cpic_reg == NULL)
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goto end;
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@ -165,14 +169,16 @@ unsigned int cpm_pic_init(void)
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sirq = NO_IRQ;
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goto end;
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}
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of_node_put(np);
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/* Install our own error handler. */
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np = of_find_node_by_type(NULL, "cpm");
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np = of_find_compatible_node(NULL, NULL, "fsl,cpm1");
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if (np == NULL)
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np = of_find_node_by_type(NULL, "cpm");
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if (np == NULL) {
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printk(KERN_ERR "CPM PIC init: can not find cpm node\n");
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goto end;
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}
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eirq = irq_of_parse_and_map(np, 0);
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if (eirq == NO_IRQ)
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goto end;
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@ -189,21 +195,28 @@ end:
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|
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void cpm_reset(void)
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{
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cpm8xx_t *commproc;
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sysconf8xx_t *siu_conf;
|
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sysconf8xx_t __iomem *siu_conf;
|
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|
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commproc = (cpm8xx_t *)ioremap(CPM_MAP_ADDR, CPM_MAP_SIZE);
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mpc8xx_immr = ioremap(get_immrbase(), 0x4000);
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if (!mpc8xx_immr) {
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printk(KERN_CRIT "Could not map IMMR\n");
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return;
|
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}
|
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|
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#ifdef CONFIG_UCODE_PATCH
|
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cpmp = &mpc8xx_immr->im_cpm;
|
||||
|
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#ifndef CONFIG_PPC_EARLY_DEBUG_CPM
|
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/* Perform a reset.
|
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*/
|
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out_be16(&commproc->cp_cpcr, CPM_CR_RST | CPM_CR_FLG);
|
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out_be16(&cpmp->cp_cpcr, CPM_CR_RST | CPM_CR_FLG);
|
||||
|
||||
/* Wait for it.
|
||||
*/
|
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while (in_be16(&commproc->cp_cpcr) & CPM_CR_FLG);
|
||||
while (in_be16(&cpmp->cp_cpcr) & CPM_CR_FLG);
|
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#endif
|
||||
|
||||
cpm_load_patch(commproc);
|
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#ifdef CONFIG_UCODE_PATCH
|
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cpm_load_patch(cpmp);
|
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#endif
|
||||
|
||||
/* Set SDMA Bus Request priority 5.
|
||||
|
|
@ -212,16 +225,12 @@ void cpm_reset(void)
|
|||
* manual recommends it.
|
||||
* Bit 25, FAM can also be set to use FEC aggressive mode (860T).
|
||||
*/
|
||||
siu_conf = (sysconf8xx_t*)immr_map(im_siu_conf);
|
||||
siu_conf = immr_map(im_siu_conf);
|
||||
out_be32(&siu_conf->sc_sdcr, 1);
|
||||
immr_unmap(siu_conf);
|
||||
|
||||
/* Reclaim the DP memory for our use. */
|
||||
m8xx_cpm_dpinit();
|
||||
|
||||
/* Tell everyone where the comm processor resides.
|
||||
*/
|
||||
cpmp = commproc;
|
||||
}
|
||||
|
||||
/* We used to do this earlier, but have to postpone as long as possible
|
||||
|
|
@ -271,20 +280,20 @@ m8xx_cpm_hostalloc(uint size)
|
|||
void
|
||||
cpm_setbrg(uint brg, uint rate)
|
||||
{
|
||||
volatile uint *bp;
|
||||
u32 __iomem *bp;
|
||||
|
||||
/* This is good enough to get SMCs running.....
|
||||
*/
|
||||
bp = (uint *)&cpmp->cp_brgc1;
|
||||
bp = &cpmp->cp_brgc1;
|
||||
bp += brg;
|
||||
/* The BRG has a 12-bit counter. For really slow baud rates (or
|
||||
* really fast processors), we may have to further divide by 16.
|
||||
*/
|
||||
if (((BRG_UART_CLK / rate) - 1) < 4096)
|
||||
*bp = (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN;
|
||||
out_be32(bp, (((BRG_UART_CLK / rate) - 1) << 1) | CPM_BRG_EN);
|
||||
else
|
||||
*bp = (((BRG_UART_CLK_DIV16 / rate) - 1) << 1) |
|
||||
CPM_BRG_EN | CPM_BRG_DIV16;
|
||||
out_be32(bp, (((BRG_UART_CLK_DIV16 / rate) - 1) << 1) |
|
||||
CPM_BRG_EN | CPM_BRG_DIV16);
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -299,15 +308,15 @@ static rh_block_t cpm_boot_dpmem_rh_block[16];
|
|||
static rh_info_t cpm_dpmem_info;
|
||||
|
||||
#define CPM_DPMEM_ALIGNMENT 8
|
||||
static u8 *dpram_vbase;
|
||||
static uint dpram_pbase;
|
||||
static u8 __iomem *dpram_vbase;
|
||||
static phys_addr_t dpram_pbase;
|
||||
|
||||
void m8xx_cpm_dpinit(void)
|
||||
static void m8xx_cpm_dpinit(void)
|
||||
{
|
||||
spin_lock_init(&cpm_dpmem_lock);
|
||||
|
||||
dpram_vbase = immr_map_size(im_cpm.cp_dpmem, CPM_DATAONLY_BASE + CPM_DATAONLY_SIZE);
|
||||
dpram_pbase = (uint)&((immap_t *)IMAP_ADDR)->im_cpm.cp_dpmem;
|
||||
dpram_vbase = cpmp->cp_dpmem;
|
||||
dpram_pbase = get_immrbase() + offsetof(immap_t, im_cpm.cp_dpmem);
|
||||
|
||||
/* Initialize the info header */
|
||||
rh_init(&cpm_dpmem_info, CPM_DPMEM_ALIGNMENT,
|
||||
|
|
@ -383,7 +392,7 @@ void *cpm_dpram_addr(unsigned long offset)
|
|||
}
|
||||
EXPORT_SYMBOL(cpm_dpram_addr);
|
||||
|
||||
uint cpm_dpram_phys(u8* addr)
|
||||
uint cpm_dpram_phys(u8 *addr)
|
||||
{
|
||||
return (dpram_pbase + (uint)(addr - dpram_vbase));
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1,12 @@
|
|||
#ifndef _POWERPC_SYSDEV_COMMPROC_H
|
||||
#define _POWERPC_SYSDEV_COMMPROC_H
|
||||
|
||||
extern void cpm_reset(void);
|
||||
extern void mpc8xx_restart(char *cmd);
|
||||
extern void mpc8xx_calibrate_decr(void);
|
||||
extern int mpc8xx_set_rtc_time(struct rtc_time *tm);
|
||||
extern void mpc8xx_get_rtc_time(struct rtc_time *tm);
|
||||
extern void m8xx_pic_init(void);
|
||||
extern unsigned int mpc8xx_get_irq(void);
|
||||
|
||||
#endif
|
||||
|
|
@ -22,7 +22,7 @@ extern int cpm_get_irq(struct pt_regs *regs);
|
|||
static struct irq_host *mpc8xx_pic_host;
|
||||
#define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
|
||||
static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
|
||||
static sysconf8xx_t *siu_reg;
|
||||
static sysconf8xx_t __iomem *siu_reg;
|
||||
|
||||
int cpm_get_irq(struct pt_regs *regs);
|
||||
|
||||
|
|
@ -159,13 +159,14 @@ static struct irq_host_ops mpc8xx_pic_host_ops = {
|
|||
int mpc8xx_pic_init(void)
|
||||
{
|
||||
struct resource res;
|
||||
struct device_node *np = NULL;
|
||||
struct device_node *np;
|
||||
int ret;
|
||||
|
||||
np = of_find_node_by_type(np, "mpc8xx-pic");
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "fsl,pq1-pic");
|
||||
if (np == NULL)
|
||||
np = of_find_node_by_type(NULL, "mpc8xx-pic");
|
||||
if (np == NULL) {
|
||||
printk(KERN_ERR "Could not find open-pic node\n");
|
||||
printk(KERN_ERR "Could not find fsl,pq1-pic node\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
|
|
@ -173,11 +174,9 @@ int mpc8xx_pic_init(void)
|
|||
if (ret)
|
||||
goto out;
|
||||
|
||||
siu_reg = (void *)ioremap(res.start, res.end - res.start + 1);
|
||||
if (siu_reg == NULL) {
|
||||
ret = -EINVAL;
|
||||
goto out;
|
||||
}
|
||||
siu_reg = ioremap(res.start, res.end - res.start + 1);
|
||||
if (siu_reg == NULL)
|
||||
return -EINVAL;
|
||||
|
||||
mpc8xx_pic_host = irq_alloc_host(of_node_get(np), IRQ_HOST_MAP_LINEAR,
|
||||
64, &mpc8xx_pic_host_ops, 64);
|
||||
|
|
|
|||
|
|
@ -66,7 +66,7 @@
|
|||
/* Export the base address of the communication processor registers
|
||||
* and dual port ram.
|
||||
*/
|
||||
extern cpm8xx_t *cpmp; /* Pointer to comm processor */
|
||||
extern cpm8xx_t __iomem *cpmp; /* Pointer to comm processor */
|
||||
extern unsigned long cpm_dpalloc(uint size, uint align);
|
||||
extern int cpm_dpfree(unsigned long offset);
|
||||
extern unsigned long cpm_dpalloc_fixed(unsigned long offset, uint size, uint align);
|
||||
|
|
@ -689,4 +689,6 @@ typedef struct risc_timer_pram {
|
|||
extern void cpm_install_handler(int vec, void (*handler)(void *), void *dev_id);
|
||||
extern void cpm_free_handler(int vec);
|
||||
|
||||
#define IMAP_ADDR (get_immrbase())
|
||||
|
||||
#endif /* __CPM_8XX__ */
|
||||
|
|
|
|||
|
|
@ -45,22 +45,11 @@
|
|||
#include <asm/8xx_immap.h>
|
||||
#include <asm/mpc8xx.h>
|
||||
|
||||
#define immr_map(member) \
|
||||
({ \
|
||||
u32 offset = offsetof(immap_t, member); \
|
||||
void *addr = ioremap (IMAP_ADDR + offset, \
|
||||
sizeof( ((immap_t*)0)->member)); \
|
||||
addr; \
|
||||
})
|
||||
extern immap_t __iomem *mpc8xx_immr;
|
||||
|
||||
#define immr_map_size(member, size) \
|
||||
({ \
|
||||
u32 offset = offsetof(immap_t, member); \
|
||||
void *addr = ioremap (IMAP_ADDR + offset, size); \
|
||||
addr; \
|
||||
})
|
||||
|
||||
#define immr_unmap(addr) iounmap(addr)
|
||||
#define immr_map(member) (&mpc8xx_immr->member)
|
||||
#define immr_map_size(member, size) (&mpc8xx_immr->member)
|
||||
#define immr_unmap(addr) do {} while (0)
|
||||
#endif
|
||||
|
||||
static inline int uart_baudrate(void)
|
||||
|
|
|
|||
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