ARM: at91/pm_slowclock: add runtime detection of memory contoller
This will allow to have all SoC in one kernel image. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
This commit is contained in:
Jean-Christophe PLAGNIOL-VILLARD
Nicolas Ferre
Родитель
f363c407b4
Коммит
fb7e197bec
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@ -21,11 +21,12 @@ extern void __iomem *at91_ramc_base[];
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.extern at91_ramc_base
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#endif
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#ifdef CONFIG_ARCH_AT91RM9200
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#include <mach/at91rm9200_mc.h>
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#else
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#define AT91_MEMCTRL_MC 0
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#define AT91_MEMCTRL_SDRAMC 1
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#define AT91_MEMCTRL_DDRSDR 2
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#include <mach/at91rm9200_sdramc.h>
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#include <mach/at91sam9_ddrsdr.h>
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#include <mach/at91sam9_sdramc.h>
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#endif
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#endif /* __AT91_RAMC_H__ */
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@ -188,10 +188,12 @@ int at91_suspend_entering_slow_clock(void)
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EXPORT_SYMBOL(at91_suspend_entering_slow_clock);
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static void (*slow_clock)(void __iomem *pmc, void __iomem *ramc0, void __iomem *ramc1);
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static void (*slow_clock)(void __iomem *pmc, void __iomem *ramc0,
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void __iomem *ramc1, int memctrl);
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#ifdef CONFIG_AT91_SLOW_CLOCK
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extern void at91_slow_clock(void __iomem *pmc, void __iomem *ramc0, void __iomem *ramc1);
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extern void at91_slow_clock(void __iomem *pmc, void __iomem *ramc0,
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void __iomem *ramc1, int memctrl);
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extern u32 at91_slow_clock_sz;
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#endif
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@ -241,11 +243,18 @@ static int at91_pm_enter(suspend_state_t state)
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* turning off the main oscillator; reverse on wakeup.
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*/
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if (slow_clock) {
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int memctrl = AT91_MEMCTRL_SDRAMC;
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if (cpu_is_at91rm9200())
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memctrl = AT91_MEMCTRL_MC;
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else if (cpu_is_at91sam9g45())
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memctrl = AT91_MEMCTRL_DDRSDR;
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#ifdef CONFIG_AT91_SLOW_CLOCK
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/* copy slow_clock handler to SRAM, and call it */
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memcpy(slow_clock, at91_slow_clock, at91_slow_clock_sz);
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#endif
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slow_clock(at91_pmc_base, at91_ramc_base[0], at91_ramc_base[1]);
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slow_clock(at91_pmc_base, at91_ramc_base[0],
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at91_ramc_base[1], memctrl);
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break;
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} else {
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pr_info("AT91: PM - no slow clock mode enabled ...\n");
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@ -42,8 +42,9 @@
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pmc .req r0
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sdramc .req r1
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ramc1 .req r2
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tmp1 .req r3
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tmp2 .req r4
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memctrl .req r3
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tmp1 .req r4
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tmp2 .req r5
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/*
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* Wait until master clock is ready (after switching master clock source)
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@ -103,29 +104,44 @@ tmp2 .req r4
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.text
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/* void at91_slow_clock(void __iomem *pmc, void __iomem *sdramc, void __iomem *ramc1) */
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/* void at91_slow_clock(void __iomem *pmc, void __iomem *sdramc,
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* void __iomem *ramc1, int memctrl)
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*/
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ENTRY(at91_slow_clock)
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/* Save registers on stack */
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stmfd sp!, {r3 - r12, lr}
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stmfd sp!, {r4 - r12, lr}
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/*
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* Register usage:
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* R0 = Base address of AT91_PMC
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* R1 = Base address of RAM Controller (SDRAM, DDRSDR, or AT91_SYS)
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* R2 = Base address of second RAM Controller or 0 if not present
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* R3 = temporary register
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* R3 = Memory controller
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* R4 = temporary register
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* R5 = temporary register
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*/
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/* Drain write buffer */
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mov tmp1, #0
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mcr p15, 0, tmp1, c7, c10, 4
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#ifdef CONFIG_ARCH_AT91RM9200
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cmp memctrl, #AT91_MEMCTRL_MC
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bne ddr_sr_enable
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/*
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* at91rm9200 Memory controller
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*/
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/* Put SDRAM in self-refresh mode */
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mov tmp1, #1
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str tmp1, [sdramc, #AT91RM9200_SDRAMC_SRR]
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#elif defined(CONFIG_ARCH_AT91SAM9G45)
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b sdr_sr_done
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/*
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* DDRSDR Memory controller
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*/
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ddr_sr_enable:
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cmp memctrl, #AT91_MEMCTRL_DDRSDR
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bne sdr_sr_enable
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/* prepare for DDRAM self-refresh mode */
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ldr tmp1, [sdramc, #AT91_DDRSDRC_LPR]
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@ -143,7 +159,13 @@ ENTRY(at91_slow_clock)
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/* Enable DDRAM self-refresh mode */
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str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
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strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
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#else
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b sdr_sr_done
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/*
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* SDRAMC Memory controller
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*/
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sdr_sr_enable:
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/* Enable SDRAM self-refresh mode */
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ldr tmp1, [sdramc, #AT91_SDRAMC_LPR]
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str tmp1, .saved_sam9_lpr
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@ -151,8 +173,8 @@ ENTRY(at91_slow_clock)
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bic tmp1, #AT91_SDRAMC_LPCB
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orr tmp1, #AT91_SDRAMC_LPCB_SELF_REFRESH
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str tmp1, [sdramc, #AT91_SDRAMC_LPR]
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#endif
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sdr_sr_done:
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/* Save Master clock setting */
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ldr tmp1, [pmc, #(AT91_PMC_MCKR - AT91_PMC)]
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str tmp1, .saved_mckr
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@ -255,9 +277,18 @@ ENTRY(at91_slow_clock)
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wait_mckrdy
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#ifdef CONFIG_ARCH_AT91RM9200
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/* Do nothing - self-refresh is automatically disabled. */
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#elif defined(CONFIG_ARCH_AT91SAM9G45)
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/*
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* at91rm9200 Memory controller
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* Do nothing - self-refresh is automatically disabled.
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*/
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cmp memctrl, #AT91_MEMCTRL_MC
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beq ram_restored
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/*
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* DDRSDR Memory controller
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*/
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cmp memctrl, #AT91_MEMCTRL_DDRSDR
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bne sdr_en_restore
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/* Restore LPR on AT91 with DDRAM */
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ldr tmp1, .saved_sam9_lpr
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str tmp1, [sdramc, #AT91_DDRSDRC_LPR]
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@ -267,14 +298,19 @@ ENTRY(at91_slow_clock)
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ldrne tmp2, .saved_sam9_lpr1
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strne tmp2, [ramc1, #AT91_DDRSDRC_LPR]
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#else
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b ram_restored
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/*
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* SDRAMC Memory controller
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*/
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sdr_en_restore:
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/* Restore LPR on AT91 with SDRAM */
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ldr tmp1, .saved_sam9_lpr
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str tmp1, [sdramc, #AT91_SDRAMC_LPR]
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#endif
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ram_restored:
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/* Restore registers, and return */
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ldmfd sp!, {r3 - r12, pc}
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ldmfd sp!, {r4 - r12, pc}
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.saved_mckr:
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